* [RFC v6 00/11] i386 cleanup
@ 2020-11-26 22:32 Claudio Fontana
2020-11-26 22:32 ` [RFC v6 01/11] i386: move kvm accel files into kvm/ Claudio Fontana
` (10 more replies)
0 siblings, 11 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Hi all, this is v6 of the i386 cleanup,
with the most interesting patches at the end.
v5 -> v6: remove MODULE_INIT_ACCEL_CPU
instead, use a call to accel_init_interfaces().
* The class lookups are now general and performed in accel/
new AccelCPUClass for new archs are supported as new
ones appear in the class hierarchy, no need for stubs.
* Split the code a bit better
Thanks,
Claudio
v4 -> v5: centralized and simplified initializations
I put in Cc: Emilio G. Cota, specifically because in patch 8
I (re)moved for user-mode the call to tcg_regions_init().
The call happens now inside the tcg AccelClass machine_init,
(so earlier). This seems to work fine, but thought to get the
author opinion on this.
Rebased on "tcg-cpus: split into 3 tcg variants" series
(queued by Richard), to avoid some code churn:
https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg04356.html
* Extended AccelClass to user-mode.
user-mode now does not call tcg_exec_init directly,
instead it uses the tcg accel class, and its init_machine method.
Since user-mode does not define or use a machine state,
the machine is just passed as NULL.
The immediate advantage is that now we can call current_accel()
from both user mode and softmmu, so we can work out the correct
class to use for accelerator initializations.
* QOMification of CpusAccelOps
simple QOMification of CpusAccelOps abstract class.
* Centralized all accel_cpu_init, so only one per cpu-arch,
plus one for all accels will remain.
So we can expect accel_cpu_init() to be limited to:
softmmu/cpus.c - initializes the chosen softmmu accel ops for the cpus module.
target/ARCH/cpu.c - initializes the chosen arch-specific cpu accelerator.
These changes are meant to address concerns/issues (Paolo):
1) the use of if (tcg_enabled()) and similar in the module_init call path
2) the excessive number of accel_cpu_init() to hunt down in the codebase.
* Fixed wrong use of host_cpu_class_init (Eduardo)
v3 -> v4: QOMification of X86CPUAccelClass
In this version I basically QOMified X86CPUAccel, taking the
suggestions from Eduardo as the starting point,
but stopping just short of making it an actual QOM interface,
using a plain abstract class, and then subclasses for the
actual objects.
Initialization is still using the existing qemu initialization
framework (module_call_init), which is I still think is better
than the alternatives proposed, in the current state.
Possibly some improvements could be developed in the future here.
In this case, effort should be put in keeping things extendible,
in order not to be blocked once accelerators also become modules.
Motivation and higher level steps:
https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html
Looking forward to your comments on this proposal,
Ciao,
Claudio
Claudio Fontana (11):
i386: move kvm accel files into kvm/
i386: move whpx accel files into whpx/
i386: move hax accel files into hax/
i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
i386: move TCG accel files into tcg/
i386: move cpu dump out of helper.c into cpu-dump.c
i386: move TCG cpu class initialization out of helper.c
accel: extend AccelState and AccelClass to user-mode
accel: replace struct CpusAccel with AccelOpsClass
accel: introduce AccelCPUClass extending CPUClass
i386: split cpu accelerators from cpu.c, using AccelCPUClass
MAINTAINERS | 18 +-
accel/accel-common.c | 104 +++++
accel/{accel.c => accel-softmmu.c} | 60 +--
accel/accel-softmmu.h | 15 +
accel/accel-user.c | 24 ++
accel/kvm/kvm-all.c | 2 -
accel/kvm/kvm-cpus.c | 26 +-
accel/kvm/kvm-cpus.h | 2 -
accel/meson.build | 4 +-
accel/qtest/qtest.c | 25 +-
accel/tcg/meson.build | 2 +-
accel/tcg/tcg-all.c | 11 +-
accel/tcg/tcg-cpus-icount.c | 11 +-
accel/tcg/tcg-cpus-icount.h | 2 +
accel/tcg/tcg-cpus-mttcg.c | 12 +-
accel/tcg/tcg-cpus-mttcg.h | 19 +
accel/tcg/tcg-cpus-rr.c | 7 -
accel/tcg/tcg-cpus.c | 43 ++
accel/tcg/tcg-cpus.h | 4 -
accel/xen/xen-all.c | 24 +-
bsd-user/main.c | 12 +-
hw/i386/fw_cfg.c | 2 +-
hw/i386/intel_iommu.c | 2 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvm/clock.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/i386/pc_piix.c | 1 +
hw/i386/x86.c | 2 +-
include/hw/boards.h | 2 +-
include/hw/core/accel-cpu.h | 28 ++
include/hw/core/cpu.h | 4 +
include/{sysemu => qemu}/accel.h | 16 +-
include/sysemu/accel-ops.h | 45 +++
include/sysemu/cpus.h | 26 +-
include/sysemu/hvf.h | 2 +-
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 2 +-
linux-user/main.c | 8 +-
meson.build | 1 +
softmmu/cpus.c | 12 +-
softmmu/memory.c | 2 +-
softmmu/qtest.c | 2 +-
softmmu/vl.c | 10 +-
target/i386/cpu-dump.c | 538 +++++++++++++++++++++++++
target/i386/cpu.c | 411 +++-----------------
target/i386/cpu.h | 120 +-----
target/i386/{ => hax}/hax-all.c | 5 +-
target/i386/{ => hax}/hax-cpus.c | 29 +-
target/i386/{ => hax}/hax-cpus.h | 2 -
target/i386/{ => hax}/hax-i386.h | 6 +-
target/i386/{ => hax}/hax-interface.h | 0
target/i386/{ => hax}/hax-mem.c | 0
target/i386/{ => hax}/hax-posix.c | 0
target/i386/{ => hax}/hax-posix.h | 0
target/i386/{ => hax}/hax-windows.c | 0
target/i386/{ => hax}/hax-windows.h | 0
target/i386/hax/meson.build | 7 +
target/i386/helper-tcg.h | 112 ++++++
target/i386/helper.c | 539 +-------------------------
target/i386/host-cpu.c | 198 ++++++++++
target/i386/host-cpu.h | 19 +
target/i386/hvf/cpu.c | 65 ++++
target/i386/hvf/hvf-cpus.c | 27 +-
target/i386/hvf/hvf-cpus.h | 2 -
target/i386/hvf/hvf-i386.h | 2 +-
target/i386/hvf/hvf.c | 3 +-
target/i386/hvf/meson.build | 1 +
target/i386/hvf/x86_task.c | 2 +-
target/i386/kvm/cpu.c | 148 +++++++
target/i386/{ => kvm}/hyperv-proto.h | 0
target/i386/{ => kvm}/hyperv-stub.c | 0
target/i386/{ => kvm}/hyperv.c | 0
target/i386/{ => kvm}/hyperv.h | 0
target/i386/kvm/kvm-cpu.h | 41 ++
target/i386/{ => kvm}/kvm-stub.c | 0
target/i386/{ => kvm}/kvm.c | 3 +-
target/i386/{ => kvm}/kvm_i386.h | 0
target/i386/kvm/meson.build | 8 +
target/i386/kvm/trace-events | 7 +
target/i386/kvm/trace.h | 1 +
target/i386/machine.c | 4 +-
target/i386/meson.build | 39 +-
target/i386/{ => tcg}/bpt_helper.c | 1 +
target/i386/{ => tcg}/cc_helper.c | 1 +
target/i386/tcg/cpu.c | 173 +++++++++
target/i386/{ => tcg}/excp_helper.c | 1 +
target/i386/{ => tcg}/fpu_helper.c | 33 +-
target/i386/{ => tcg}/int_helper.c | 1 +
target/i386/{ => tcg}/mem_helper.c | 1 +
target/i386/tcg/meson.build | 14 +
target/i386/{ => tcg}/misc_helper.c | 1 +
target/i386/{ => tcg}/mpx_helper.c | 1 +
target/i386/{ => tcg}/seg_helper.c | 1 +
target/i386/{ => tcg}/smm_helper.c | 2 +
target/i386/{ => tcg}/svm_helper.c | 1 +
target/i386/{ => tcg}/tcg-stub.c | 0
target/i386/{ => tcg}/translate.c | 1 +
target/i386/trace-events | 6 -
target/i386/whpx/meson.build | 4 +
target/i386/{ => whpx}/whp-dispatch.h | 0
target/i386/{ => whpx}/whpx-all.c | 4 +-
target/i386/{ => whpx}/whpx-cpus.c | 29 +-
target/i386/{ => whpx}/whpx-cpus.h | 2 -
104 files changed, 1965 insertions(+), 1255 deletions(-)
create mode 100644 accel/accel-common.c
rename accel/{accel.c => accel-softmmu.c} (64%)
create mode 100644 accel/accel-softmmu.h
create mode 100644 accel/accel-user.c
create mode 100644 accel/tcg/tcg-cpus-mttcg.h
create mode 100644 include/hw/core/accel-cpu.h
rename include/{sysemu => qemu}/accel.h (93%)
create mode 100644 include/sysemu/accel-ops.h
create mode 100644 target/i386/cpu-dump.c
rename target/i386/{ => hax}/hax-all.c (99%)
rename target/i386/{ => hax}/hax-cpus.c (71%)
rename target/i386/{ => hax}/hax-cpus.h (95%)
rename target/i386/{ => hax}/hax-i386.h (95%)
rename target/i386/{ => hax}/hax-interface.h (100%)
rename target/i386/{ => hax}/hax-mem.c (100%)
rename target/i386/{ => hax}/hax-posix.c (100%)
rename target/i386/{ => hax}/hax-posix.h (100%)
rename target/i386/{ => hax}/hax-windows.c (100%)
rename target/i386/{ => hax}/hax-windows.h (100%)
create mode 100644 target/i386/hax/meson.build
create mode 100644 target/i386/helper-tcg.h
create mode 100644 target/i386/host-cpu.c
create mode 100644 target/i386/host-cpu.h
create mode 100644 target/i386/hvf/cpu.c
create mode 100644 target/i386/kvm/cpu.c
rename target/i386/{ => kvm}/hyperv-proto.h (100%)
rename target/i386/{ => kvm}/hyperv-stub.c (100%)
rename target/i386/{ => kvm}/hyperv.c (100%)
rename target/i386/{ => kvm}/hyperv.h (100%)
create mode 100644 target/i386/kvm/kvm-cpu.h
rename target/i386/{ => kvm}/kvm-stub.c (100%)
rename target/i386/{ => kvm}/kvm.c (99%)
rename target/i386/{ => kvm}/kvm_i386.h (100%)
create mode 100644 target/i386/kvm/meson.build
create mode 100644 target/i386/kvm/trace-events
create mode 100644 target/i386/kvm/trace.h
rename target/i386/{ => tcg}/bpt_helper.c (99%)
rename target/i386/{ => tcg}/cc_helper.c (99%)
create mode 100644 target/i386/tcg/cpu.c
rename target/i386/{ => tcg}/excp_helper.c (99%)
rename target/i386/{ => tcg}/fpu_helper.c (99%)
rename target/i386/{ => tcg}/int_helper.c (99%)
rename target/i386/{ => tcg}/mem_helper.c (99%)
create mode 100644 target/i386/tcg/meson.build
rename target/i386/{ => tcg}/misc_helper.c (99%)
rename target/i386/{ => tcg}/mpx_helper.c (99%)
rename target/i386/{ => tcg}/seg_helper.c (99%)
rename target/i386/{ => tcg}/smm_helper.c (99%)
rename target/i386/{ => tcg}/svm_helper.c (99%)
rename target/i386/{ => tcg}/tcg-stub.c (100%)
rename target/i386/{ => tcg}/translate.c (99%)
create mode 100644 target/i386/whpx/meson.build
rename target/i386/{ => whpx}/whp-dispatch.h (100%)
rename target/i386/{ => whpx}/whpx-all.c (99%)
rename target/i386/{ => whpx}/whpx-cpus.c (73%)
rename target/i386/{ => whpx}/whpx-cpus.h (96%)
--
2.26.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFC v6 01/11] i386: move kvm accel files into kvm/
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 02/11] i386: move whpx accel files into whpx/ Claudio Fontana
` (9 subsequent siblings)
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 2 +-
hw/i386/fw_cfg.c | 2 +-
hw/i386/intel_iommu.c | 2 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvm/clock.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/i386/x86.c | 2 +-
meson.build | 1 +
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 +-
target/i386/helper.c | 2 +-
target/i386/{ => kvm}/hyperv-proto.h | 0
target/i386/{ => kvm}/hyperv-stub.c | 0
target/i386/{ => kvm}/hyperv.c | 0
target/i386/{ => kvm}/hyperv.h | 0
target/i386/{ => kvm}/kvm-stub.c | 0
target/i386/{ => kvm}/kvm.c | 0
target/i386/{ => kvm}/kvm_i386.h | 0
target/i386/kvm/meson.build | 3 +++
target/i386/kvm/trace-events | 7 +++++++
target/i386/kvm/trace.h | 1 +
target/i386/machine.c | 4 ++--
target/i386/meson.build | 4 +---
target/i386/trace-events | 6 ------
25 files changed, 26 insertions(+), 22 deletions(-)
rename target/i386/{ => kvm}/hyperv-proto.h (100%)
rename target/i386/{ => kvm}/hyperv-stub.c (100%)
rename target/i386/{ => kvm}/hyperv.c (100%)
rename target/i386/{ => kvm}/hyperv.h (100%)
rename target/i386/{ => kvm}/kvm-stub.c (100%)
rename target/i386/{ => kvm}/kvm.c (100%)
rename target/i386/{ => kvm}/kvm_i386.h (100%)
create mode 100644 target/i386/kvm/meson.build
create mode 100644 target/i386/kvm/trace-events
create mode 100644 target/i386/kvm/trace.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2e018a0c1d..6a77faccf6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -424,7 +424,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Marcelo Tosatti <mtosatti@redhat.com>
L: kvm@vger.kernel.org
S: Supported
-F: target/i386/kvm.c
+F: target/i386/kvm/
F: scripts/kvm/vmxcap
Guest CPU Cores (other accelerators)
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
index e06579490c..fae1bb380f 100644
--- a/hw/i386/fw_cfg.c
+++ b/hw/i386/fw_cfg.c
@@ -21,7 +21,7 @@
#include "hw/timer/hpet.h"
#include "hw/nvram/fw_cfg.h"
#include "e820_memory_layout.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include CONFIG_DEVICES
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 70ac837733..361b6cd238 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -37,7 +37,7 @@
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "hw/i386/apic_internal.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "trace.h"
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c
index dd29906061..07bebc1282 100644
--- a/hw/i386/kvm/apic.c
+++ b/hw/i386/kvm/apic.c
@@ -17,7 +17,7 @@
#include "hw/pci/msi.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
-#include "target/i386/kvm_i386.h"
+#include "kvm/kvm_i386.h"
static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
int reg_id, uint32_t val)
diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c
index 24fe5091b6..2d8a366369 100644
--- a/hw/i386/kvm/clock.c
+++ b/hw/i386/kvm/clock.c
@@ -20,7 +20,7 @@
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "sysemu/hw_accel.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/kvm/clock.h"
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 5428448b70..3ed6adff83 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -51,7 +51,7 @@
#include "cpu.h"
#include "elf.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "hw/xen/start_info.h"
#define MICROVM_QBOOT_FILENAME "qboot.rom"
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 17b514d1da..299aaba8e9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -61,7 +61,7 @@
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "hw/xen/xen.h"
#include "hw/xen/start_info.h"
#include "ui/qemu-spice.h"
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 5944fc44ed..88d0c70e12 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -52,7 +52,7 @@
#include "elf.h"
#include "standard-headers/asm-x86/bootparam.h"
#include CONFIG_DEVICES
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#define BIOS_FILENAME "bios.bin"
diff --git a/meson.build b/meson.build
index 5062407c70..d6158172b0 100644
--- a/meson.build
+++ b/meson.build
@@ -1468,6 +1468,7 @@ trace_events_subdirs += [
'target/arm',
'target/hppa',
'target/i386',
+ 'target/i386/kvm',
'target/mips',
'target/ppc',
'target/riscv',
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5a8c96072e..b9bd249c8f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -30,7 +30,7 @@
#include "sysemu/hvf.h"
#include "sysemu/cpus.h"
#include "sysemu/xen.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "sev_i386.h"
#include "qemu/error-report.h"
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 88e8586f8f..9ecda75aec 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -22,7 +22,7 @@
#include "sysemu/tcg.h"
#include "cpu-qom.h"
-#include "hyperv-proto.h"
+#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 034f46bcc2..a1b3367ab2 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -24,7 +24,7 @@
#include "qemu/qemu-print.h"
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/tcg.h"
#include "sysemu/hw_accel.h"
diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h
similarity index 100%
rename from target/i386/hyperv-proto.h
rename to target/i386/kvm/hyperv-proto.h
diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c
similarity index 100%
rename from target/i386/hyperv-stub.c
rename to target/i386/kvm/hyperv-stub.c
diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c
similarity index 100%
rename from target/i386/hyperv.c
rename to target/i386/kvm/hyperv.c
diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h
similarity index 100%
rename from target/i386/hyperv.h
rename to target/i386/kvm/hyperv.h
diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c
similarity index 100%
rename from target/i386/kvm-stub.c
rename to target/i386/kvm/kvm-stub.c
diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c
similarity index 100%
rename from target/i386/kvm.c
rename to target/i386/kvm/kvm.c
diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h
similarity index 100%
rename from target/i386/kvm_i386.h
rename to target/i386/kvm/kvm_i386.h
diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build
new file mode 100644
index 0000000000..1d66559187
--- /dev/null
+++ b/target/i386/kvm/meson.build
@@ -0,0 +1,3 @@
+i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
+i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events
new file mode 100644
index 0000000000..b4e2d9e4ea
--- /dev/null
+++ b/target/i386/kvm/trace-events
@@ -0,0 +1,7 @@
+# See docs/devel/tracing.txt for syntax documentation.
+
+# kvm.c
+kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32
+kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d"
+kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d"
+kvm_x86_update_msi_routes(int num) "Updated %d MSI routes"
diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h
new file mode 100644
index 0000000000..46b75c6942
--- /dev/null
+++ b/target/i386/kvm/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-target_i386_kvm.h"
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 233e46bb70..1614e8c2f8 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -3,9 +3,9 @@
#include "exec/exec-all.h"
#include "hw/isa/isa.h"
#include "migration/cpu.h"
-#include "hyperv.h"
+#include "kvm/hyperv.h"
#include "hw/i386/x86.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "sysemu/kvm.h"
#include "sysemu/tcg.h"
diff --git a/target/i386/meson.build b/target/i386/meson.build
index a1a02f3e99..0209542a8a 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
'smm_helper.c',
'svm_helper.c',
'translate.c'), if_false: files('tcg-stub.c'))
-i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
i386_softmmu_ss = ss.source_set()
@@ -28,8 +27,6 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
-i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
-i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
'whpx-all.c',
'whpx-cpus.c',
@@ -42,6 +39,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
+subdir('kvm')
subdir('hvf')
target_arch += {'i386': i386_ss}
diff --git a/target/i386/trace-events b/target/i386/trace-events
index 789c700d4a..d166f9d5e0 100644
--- a/target/i386/trace-events
+++ b/target/i386/trace-events
@@ -1,11 +1,5 @@
# See docs/devel/tracing.txt for syntax documentation.
-# kvm.c
-kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32
-kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d"
-kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d"
-kvm_x86_update_msi_routes(int num) "Updated %d MSI routes"
-
# sev.c
kvm_sev_init(void) ""
kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zu"
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 02/11] i386: move whpx accel files into whpx/
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
2020-11-26 22:32 ` [RFC v6 01/11] i386: move kvm accel files into kvm/ Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 03/11] i386: move hax accel files into hax/ Claudio Fontana
` (8 subsequent siblings)
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 5 +----
target/i386/meson.build | 5 +----
target/i386/whpx/meson.build | 4 ++++
target/i386/{ => whpx}/whp-dispatch.h | 0
target/i386/{ => whpx}/whpx-all.c | 0
target/i386/{ => whpx}/whpx-cpus.c | 0
target/i386/{ => whpx}/whpx-cpus.h | 0
7 files changed, 6 insertions(+), 8 deletions(-)
create mode 100644 target/i386/whpx/meson.build
rename target/i386/{ => whpx}/whp-dispatch.h (100%)
rename target/i386/{ => whpx}/whpx-all.c (100%)
rename target/i386/{ => whpx}/whpx-cpus.c (100%)
rename target/i386/{ => whpx}/whpx-cpus.h (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6a77faccf6..02bc29ea2b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -450,10 +450,7 @@ F: include/sysemu/hvf.h
WHPX CPUs
M: Sunil Muthuswamy <sunilmut@microsoft.com>
S: Supported
-F: target/i386/whpx-all.c
-F: target/i386/whpx-cpus.c
-F: target/i386/whp-dispatch.h
-F: accel/stubs/whpx-stub.c
+F: target/i386/whpx/
F: include/sysemu/whpx.h
Guest CPU Cores (Xen)
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 0209542a8a..62cd042915 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -27,10 +27,6 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
-i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
- 'whpx-all.c',
- 'whpx-cpus.c',
-))
i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
'hax-all.c',
'hax-mem.c',
@@ -40,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-po
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
subdir('kvm')
+subdir('whpx')
subdir('hvf')
target_arch += {'i386': i386_ss}
diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build
new file mode 100644
index 0000000000..94a72c8efc
--- /dev/null
+++ b/target/i386/whpx/meson.build
@@ -0,0 +1,4 @@
+i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
+ 'whpx-all.c',
+ 'whpx-cpus.c',
+))
diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h
similarity index 100%
rename from target/i386/whp-dispatch.h
rename to target/i386/whpx/whp-dispatch.h
diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c
similarity index 100%
rename from target/i386/whpx-all.c
rename to target/i386/whpx/whpx-all.c
diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c
similarity index 100%
rename from target/i386/whpx-cpus.c
rename to target/i386/whpx/whpx-cpus.c
diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h
similarity index 100%
rename from target/i386/whpx-cpus.h
rename to target/i386/whpx/whpx-cpus.h
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 03/11] i386: move hax accel files into hax/
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
2020-11-26 22:32 ` [RFC v6 01/11] i386: move kvm accel files into kvm/ Claudio Fontana
2020-11-26 22:32 ` [RFC v6 02/11] i386: move whpx accel files into whpx/ Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 04/11] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Claudio Fontana
` (7 subsequent siblings)
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 2 +-
target/i386/{ => hax}/hax-all.c | 0
target/i386/{ => hax}/hax-cpus.c | 0
target/i386/{ => hax}/hax-cpus.h | 0
target/i386/{ => hax}/hax-i386.h | 6 +++---
target/i386/{ => hax}/hax-interface.h | 0
target/i386/{ => hax}/hax-mem.c | 0
target/i386/{ => hax}/hax-posix.c | 0
target/i386/{ => hax}/hax-posix.h | 0
target/i386/{ => hax}/hax-windows.c | 0
target/i386/{ => hax}/hax-windows.h | 0
target/i386/hax/meson.build | 7 +++++++
target/i386/meson.build | 8 +-------
13 files changed, 12 insertions(+), 11 deletions(-)
rename target/i386/{ => hax}/hax-all.c (100%)
rename target/i386/{ => hax}/hax-cpus.c (100%)
rename target/i386/{ => hax}/hax-cpus.h (100%)
rename target/i386/{ => hax}/hax-i386.h (95%)
rename target/i386/{ => hax}/hax-interface.h (100%)
rename target/i386/{ => hax}/hax-mem.c (100%)
rename target/i386/{ => hax}/hax-posix.c (100%)
rename target/i386/{ => hax}/hax-posix.h (100%)
rename target/i386/{ => hax}/hax-windows.c (100%)
rename target/i386/{ => hax}/hax-windows.h (100%)
create mode 100644 target/i386/hax/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index 02bc29ea2b..463317784c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,7 +490,7 @@ W: https://github.com/intel/haxm/issues
S: Maintained
F: accel/stubs/hax-stub.c
F: include/sysemu/hax.h
-F: target/i386/hax-*
+F: target/i386/hax/
Hosts
-----
diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c
similarity index 100%
rename from target/i386/hax-all.c
rename to target/i386/hax/hax-all.c
diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c
similarity index 100%
rename from target/i386/hax-cpus.c
rename to target/i386/hax/hax-cpus.c
diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h
similarity index 100%
rename from target/i386/hax-cpus.h
rename to target/i386/hax/hax-cpus.h
diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h
similarity index 95%
rename from target/i386/hax-i386.h
rename to target/i386/hax/hax-i386.h
index 48c4abe14e..efbb346238 100644
--- a/target/i386/hax-i386.h
+++ b/target/i386/hax/hax-i386.h
@@ -84,13 +84,13 @@ void hax_memory_init(void);
#ifdef CONFIG_POSIX
-#include "target/i386/hax-posix.h"
+#include "hax-posix.h"
#endif
#ifdef CONFIG_WIN32
-#include "target/i386/hax-windows.h"
+#include "hax-windows.h"
#endif
-#include "target/i386/hax-interface.h"
+#include "hax-interface.h"
#endif
diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h
similarity index 100%
rename from target/i386/hax-interface.h
rename to target/i386/hax/hax-interface.h
diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c
similarity index 100%
rename from target/i386/hax-mem.c
rename to target/i386/hax/hax-mem.c
diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c
similarity index 100%
rename from target/i386/hax-posix.c
rename to target/i386/hax/hax-posix.c
diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h
similarity index 100%
rename from target/i386/hax-posix.h
rename to target/i386/hax/hax-posix.h
diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c
similarity index 100%
rename from target/i386/hax-windows.c
rename to target/i386/hax/hax-windows.c
diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h
similarity index 100%
rename from target/i386/hax-windows.h
rename to target/i386/hax/hax-windows.h
diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build
new file mode 100644
index 0000000000..77ea431b30
--- /dev/null
+++ b/target/i386/hax/meson.build
@@ -0,0 +1,7 @@
+i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
+ 'hax-all.c',
+ 'hax-mem.c',
+ 'hax-cpus.c',
+))
+i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
+i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 62cd042915..284d52ab81 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -27,15 +27,9 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
-i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
- 'hax-all.c',
- 'hax-mem.c',
- 'hax-cpus.c',
-))
-i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
-i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
subdir('kvm')
+subdir('hax')
subdir('whpx')
subdir('hvf')
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 04/11] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (2 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 03/11] i386: move hax accel files into hax/ Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 05/11] i386: move TCG accel files into tcg/ Claudio Fontana
` (6 subsequent siblings)
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 463317784c..e892dd2220 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -443,7 +443,6 @@ M: Cameron Esfahani <dirty@apple.com>
M: Roman Bolshakov <r.bolshakov@yadro.com>
W: https://wiki.qemu.org/Features/HVF
S: Maintained
-F: accel/stubs/hvf-stub.c
F: target/i386/hvf/
F: include/sysemu/hvf.h
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 05/11] i386: move TCG accel files into tcg/
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (3 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 04/11] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 06/11] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
` (5 subsequent siblings)
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/i386/meson.build | 14 +-------------
target/i386/{ => tcg}/bpt_helper.c | 0
target/i386/{ => tcg}/cc_helper.c | 0
target/i386/{ => tcg}/excp_helper.c | 0
target/i386/{ => tcg}/fpu_helper.c | 0
target/i386/{ => tcg}/int_helper.c | 0
target/i386/{ => tcg}/mem_helper.c | 0
target/i386/tcg/meson.build | 13 +++++++++++++
target/i386/{ => tcg}/misc_helper.c | 0
target/i386/{ => tcg}/mpx_helper.c | 0
target/i386/{ => tcg}/seg_helper.c | 0
target/i386/{ => tcg}/smm_helper.c | 0
target/i386/{ => tcg}/svm_helper.c | 0
target/i386/{ => tcg}/tcg-stub.c | 0
target/i386/{ => tcg}/translate.c | 0
15 files changed, 14 insertions(+), 13 deletions(-)
rename target/i386/{ => tcg}/bpt_helper.c (100%)
rename target/i386/{ => tcg}/cc_helper.c (100%)
rename target/i386/{ => tcg}/excp_helper.c (100%)
rename target/i386/{ => tcg}/fpu_helper.c (100%)
rename target/i386/{ => tcg}/int_helper.c (100%)
rename target/i386/{ => tcg}/mem_helper.c (100%)
create mode 100644 target/i386/tcg/meson.build
rename target/i386/{ => tcg}/misc_helper.c (100%)
rename target/i386/{ => tcg}/mpx_helper.c (100%)
rename target/i386/{ => tcg}/seg_helper.c (100%)
rename target/i386/{ => tcg}/smm_helper.c (100%)
rename target/i386/{ => tcg}/svm_helper.c (100%)
rename target/i386/{ => tcg}/tcg-stub.c (100%)
rename target/i386/{ => tcg}/translate.c (100%)
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 284d52ab81..750471c9f3 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -5,19 +5,6 @@ i386_ss.add(files(
'helper.c',
'xsave_helper.c',
))
-i386_ss.add(when: 'CONFIG_TCG', if_true: files(
- 'bpt_helper.c',
- 'cc_helper.c',
- 'excp_helper.c',
- 'fpu_helper.c',
- 'int_helper.c',
- 'mem_helper.c',
- 'misc_helper.c',
- 'mpx_helper.c',
- 'seg_helper.c',
- 'smm_helper.c',
- 'svm_helper.c',
- 'translate.c'), if_false: files('tcg-stub.c'))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
i386_softmmu_ss = ss.source_set()
@@ -32,6 +19,7 @@ subdir('kvm')
subdir('hax')
subdir('whpx')
subdir('hvf')
+subdir('tcg')
target_arch += {'i386': i386_ss}
target_softmmu_arch += {'i386': i386_softmmu_ss}
diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c
similarity index 100%
rename from target/i386/bpt_helper.c
rename to target/i386/tcg/bpt_helper.c
diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c
similarity index 100%
rename from target/i386/cc_helper.c
rename to target/i386/tcg/cc_helper.c
diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c
similarity index 100%
rename from target/i386/excp_helper.c
rename to target/i386/tcg/excp_helper.c
diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c
similarity index 100%
rename from target/i386/fpu_helper.c
rename to target/i386/tcg/fpu_helper.c
diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c
similarity index 100%
rename from target/i386/int_helper.c
rename to target/i386/tcg/int_helper.c
diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c
similarity index 100%
rename from target/i386/mem_helper.c
rename to target/i386/tcg/mem_helper.c
diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
new file mode 100644
index 0000000000..02794226c2
--- /dev/null
+++ b/target/i386/tcg/meson.build
@@ -0,0 +1,13 @@
+i386_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'bpt_helper.c',
+ 'cc_helper.c',
+ 'excp_helper.c',
+ 'fpu_helper.c',
+ 'int_helper.c',
+ 'mem_helper.c',
+ 'misc_helper.c',
+ 'mpx_helper.c',
+ 'seg_helper.c',
+ 'smm_helper.c',
+ 'svm_helper.c',
+ 'translate.c'), if_false: files('tcg-stub.c'))
diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c
similarity index 100%
rename from target/i386/misc_helper.c
rename to target/i386/tcg/misc_helper.c
diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c
similarity index 100%
rename from target/i386/mpx_helper.c
rename to target/i386/tcg/mpx_helper.c
diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c
similarity index 100%
rename from target/i386/seg_helper.c
rename to target/i386/tcg/seg_helper.c
diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c
similarity index 100%
rename from target/i386/smm_helper.c
rename to target/i386/tcg/smm_helper.c
diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c
similarity index 100%
rename from target/i386/svm_helper.c
rename to target/i386/tcg/svm_helper.c
diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c
similarity index 100%
rename from target/i386/tcg-stub.c
rename to target/i386/tcg/tcg-stub.c
diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c
similarity index 100%
rename from target/i386/translate.c
rename to target/i386/tcg/translate.c
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 06/11] i386: move cpu dump out of helper.c into cpu-dump.c
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (4 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 05/11] i386: move TCG accel files into tcg/ Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
` (4 subsequent siblings)
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/i386/cpu-dump.c | 538 ++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 1 +
target/i386/helper.c | 514 --------------------------------------
target/i386/meson.build | 1 +
4 files changed, 540 insertions(+), 514 deletions(-)
create mode 100644 target/i386/cpu-dump.c
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
new file mode 100644
index 0000000000..1ddc47fb0c
--- /dev/null
+++ b/target/i386/cpu-dump.c
@@ -0,0 +1,538 @@
+/*
+ * i386 CPU dump to FILE
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/qemu-print.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/i386/apic_internal.h"
+#endif
+
+/***********************************************************/
+/* x86 debug */
+
+static const char *cc_op_str[CC_OP_NB] = {
+ "DYNAMIC",
+ "EFLAGS",
+
+ "MULB",
+ "MULW",
+ "MULL",
+ "MULQ",
+
+ "ADDB",
+ "ADDW",
+ "ADDL",
+ "ADDQ",
+
+ "ADCB",
+ "ADCW",
+ "ADCL",
+ "ADCQ",
+
+ "SUBB",
+ "SUBW",
+ "SUBL",
+ "SUBQ",
+
+ "SBBB",
+ "SBBW",
+ "SBBL",
+ "SBBQ",
+
+ "LOGICB",
+ "LOGICW",
+ "LOGICL",
+ "LOGICQ",
+
+ "INCB",
+ "INCW",
+ "INCL",
+ "INCQ",
+
+ "DECB",
+ "DECW",
+ "DECL",
+ "DECQ",
+
+ "SHLB",
+ "SHLW",
+ "SHLL",
+ "SHLQ",
+
+ "SARB",
+ "SARW",
+ "SARL",
+ "SARQ",
+
+ "BMILGB",
+ "BMILGW",
+ "BMILGL",
+ "BMILGQ",
+
+ "ADCX",
+ "ADOX",
+ "ADCOX",
+
+ "CLR",
+};
+
+static void
+cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
+ const char *name, struct SegmentCache *sc)
+{
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_CS64_MASK) {
+ qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
+ sc->selector, sc->base, sc->limit,
+ sc->flags & 0x00ffff00);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
+ (uint32_t)sc->base, sc->limit,
+ sc->flags & 0x00ffff00);
+ }
+
+ if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
+ goto done;
+
+ qemu_fprintf(f, " DPL=%d ",
+ (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
+ if (sc->flags & DESC_S_MASK) {
+ if (sc->flags & DESC_CS_MASK) {
+ qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
+ ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
+ qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
+ (sc->flags & DESC_R_MASK) ? 'R' : '-');
+ } else {
+ qemu_fprintf(f, (sc->flags & DESC_B_MASK
+ || env->hflags & HF_LMA_MASK)
+ ? "DS " : "DS16");
+ qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
+ (sc->flags & DESC_W_MASK) ? 'W' : '-');
+ }
+ qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
+ } else {
+ static const char *sys_type_name[2][16] = {
+ { /* 32 bit mode */
+ "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
+ "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
+ "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
+ "CallGate32", "Reserved", "IntGate32", "TrapGate32"
+ },
+ { /* 64 bit mode */
+ "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
+ "Reserved", "Reserved", "Reserved", "Reserved",
+ "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
+ "Reserved", "IntGate64", "TrapGate64"
+ }
+ };
+ qemu_fprintf(f, "%s",
+ sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
+ [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
+ }
+done:
+ qemu_fprintf(f, "\n");
+}
+
+#ifndef CONFIG_USER_ONLY
+
+/* ARRAY_SIZE check is not required because
+ * DeliveryMode(dm) has a size of 3 bit.
+ */
+static inline const char *dm2str(uint32_t dm)
+{
+ static const char *str[] = {
+ "Fixed",
+ "...",
+ "SMI",
+ "...",
+ "NMI",
+ "INIT",
+ "...",
+ "ExtINT"
+ };
+ return str[dm];
+}
+
+static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
+{
+ uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
+ qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
+ name, lvt,
+ lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
+ lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
+ lvt & APIC_LVT_MASKED ? "masked" : "",
+ lvt & APIC_LVT_DELIV_STS ? "pending" : "",
+ !is_timer ?
+ "" : lvt & APIC_LVT_TIMER_PERIODIC ?
+ "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
+ "tsc-deadline" : "one-shot",
+ dm2str(dm));
+ if (dm != APIC_DM_NMI) {
+ qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
+ } else {
+ qemu_printf("\n");
+ }
+}
+
+/* ARRAY_SIZE check is not required because
+ * destination shorthand has a size of 2 bit.
+ */
+static inline const char *shorthand2str(uint32_t shorthand)
+{
+ const char *str[] = {
+ "no-shorthand", "self", "all-self", "all"
+ };
+ return str[shorthand];
+}
+
+static inline uint8_t divider_conf(uint32_t divide_conf)
+{
+ uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
+
+ return divide_val == 7 ? 1 : 2 << divide_val;
+}
+
+static inline void mask2str(char *str, uint32_t val, uint8_t size)
+{
+ while (size--) {
+ *str++ = (val >> size) & 1 ? '1' : '0';
+ }
+ *str = 0;
+}
+
+#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
+
+static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
+{
+ uint32_t icr = s->icr[0], icr2 = s->icr[1];
+ uint8_t dest_shorthand = \
+ (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
+ bool logical_mod = icr & APIC_ICR_DEST_MOD;
+ char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
+ uint32_t dest_field;
+ bool x2apic;
+
+ qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
+ icr,
+ logical_mod ? "logical" : "physical",
+ icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
+ icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
+ shorthand2str(dest_shorthand));
+
+ qemu_printf("ICR2\t 0x%08x", icr2);
+ if (dest_shorthand != 0) {
+ qemu_printf("\n");
+ return;
+ }
+ x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
+ dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
+
+ if (!logical_mod) {
+ if (x2apic) {
+ qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
+ } else {
+ qemu_printf(" cpu %u (APIC ID)\n",
+ dest_field & APIC_LOGDEST_XAPIC_ID);
+ }
+ return;
+ }
+
+ if (s->dest_mode == 0xf) { /* flat mode */
+ mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
+ qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
+ } else if (s->dest_mode == 0) { /* cluster mode */
+ if (x2apic) {
+ mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
+ qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
+ dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
+ } else {
+ mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
+ qemu_printf(" cluster %u mask %s (APIC ID)\n",
+ dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
+ }
+ }
+}
+
+static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
+ uint32_t *tmr_tab)
+{
+ int i, empty = true;
+
+ qemu_printf("%s\t ", name);
+ for (i = 0; i < 256; i++) {
+ if (apic_get_bit(ireg_tab, i)) {
+ qemu_printf("%u%s ", i,
+ apic_get_bit(tmr_tab, i) ? "(level)" : "");
+ empty = false;
+ }
+ }
+ qemu_printf("%s\n", empty ? "(none)" : "");
+}
+
+void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ APICCommonState *s = APIC_COMMON(cpu->apic_state);
+ if (!s) {
+ qemu_printf("local apic state not available\n");
+ return;
+ }
+ uint32_t *lvt = s->lvt;
+
+ qemu_printf("dumping local APIC state for CPU %-2u\n\n",
+ CPU(cpu)->cpu_index);
+ dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
+ dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
+ dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
+ dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
+ dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
+ dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
+
+ qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
+ " current_count = %u\n",
+ s->divide_conf & APIC_DCR_MASK,
+ divider_conf(s->divide_conf),
+ s->initial_count, apic_get_current_count(s));
+
+ qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
+ s->spurious_vec,
+ s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
+ s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
+ s->spurious_vec & APIC_VECTOR_MASK);
+
+ dump_apic_icr(s, &cpu->env);
+
+ qemu_printf("ESR\t 0x%08x\n", s->esr);
+
+ dump_apic_interrupt("ISR", s->isr, s->tmr);
+ dump_apic_interrupt("IRR", s->irr, s->tmr);
+
+ qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
+ s->arb_id, s->tpr, s->dest_mode, s->log_dest);
+ if (s->dest_mode == 0) {
+ qemu_printf("(cluster %u: id %u)",
+ s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
+ s->log_dest & APIC_LOGDEST_XAPIC_ID);
+ }
+ qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
+}
+#else
+void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
+{
+}
+#endif /* !CONFIG_USER_ONLY */
+
+#define DUMP_CODE_BYTES_TOTAL 50
+#define DUMP_CODE_BYTES_BACKWARD 20
+
+void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ int eflags, i, nb;
+ char cc_op_name[32];
+ static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
+
+ eflags = cpu_compute_eflags(env);
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_CS64_MASK) {
+ qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
+ "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
+ "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
+ "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
+ "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
+ env->regs[R_EAX],
+ env->regs[R_EBX],
+ env->regs[R_ECX],
+ env->regs[R_EDX],
+ env->regs[R_ESI],
+ env->regs[R_EDI],
+ env->regs[R_EBP],
+ env->regs[R_ESP],
+ env->regs[8],
+ env->regs[9],
+ env->regs[10],
+ env->regs[11],
+ env->regs[12],
+ env->regs[13],
+ env->regs[14],
+ env->regs[15],
+ env->eip, eflags,
+ eflags & DF_MASK ? 'D' : '-',
+ eflags & CC_O ? 'O' : '-',
+ eflags & CC_S ? 'S' : '-',
+ eflags & CC_Z ? 'Z' : '-',
+ eflags & CC_A ? 'A' : '-',
+ eflags & CC_P ? 'P' : '-',
+ eflags & CC_C ? 'C' : '-',
+ env->hflags & HF_CPL_MASK,
+ (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
+ (env->a20_mask >> 20) & 1,
+ (env->hflags >> HF_SMM_SHIFT) & 1,
+ cs->halted);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
+ "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
+ "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
+ (uint32_t)env->regs[R_EAX],
+ (uint32_t)env->regs[R_EBX],
+ (uint32_t)env->regs[R_ECX],
+ (uint32_t)env->regs[R_EDX],
+ (uint32_t)env->regs[R_ESI],
+ (uint32_t)env->regs[R_EDI],
+ (uint32_t)env->regs[R_EBP],
+ (uint32_t)env->regs[R_ESP],
+ (uint32_t)env->eip, eflags,
+ eflags & DF_MASK ? 'D' : '-',
+ eflags & CC_O ? 'O' : '-',
+ eflags & CC_S ? 'S' : '-',
+ eflags & CC_Z ? 'Z' : '-',
+ eflags & CC_A ? 'A' : '-',
+ eflags & CC_P ? 'P' : '-',
+ eflags & CC_C ? 'C' : '-',
+ env->hflags & HF_CPL_MASK,
+ (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
+ (env->a20_mask >> 20) & 1,
+ (env->hflags >> HF_SMM_SHIFT) & 1,
+ cs->halted);
+ }
+
+ for(i = 0; i < 6; i++) {
+ cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
+ }
+ cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
+ cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
+
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_LMA_MASK) {
+ qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
+ env->gdt.base, env->gdt.limit);
+ qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
+ env->idt.base, env->idt.limit);
+ qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
+ (uint32_t)env->cr[0],
+ env->cr[2],
+ env->cr[3],
+ (uint32_t)env->cr[4]);
+ for(i = 0; i < 4; i++)
+ qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
+ qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
+ env->dr[6], env->dr[7]);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "GDT= %08x %08x\n",
+ (uint32_t)env->gdt.base, env->gdt.limit);
+ qemu_fprintf(f, "IDT= %08x %08x\n",
+ (uint32_t)env->idt.base, env->idt.limit);
+ qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
+ (uint32_t)env->cr[0],
+ (uint32_t)env->cr[2],
+ (uint32_t)env->cr[3],
+ (uint32_t)env->cr[4]);
+ for(i = 0; i < 4; i++) {
+ qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
+ }
+ qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
+ env->dr[6], env->dr[7]);
+ }
+ if (flags & CPU_DUMP_CCOP) {
+ if ((unsigned)env->cc_op < CC_OP_NB)
+ snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
+ else
+ snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_CS64_MASK) {
+ qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
+ env->cc_src, env->cc_dst,
+ cc_op_name);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
+ (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
+ cc_op_name);
+ }
+ }
+ qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
+ if (flags & CPU_DUMP_FPU) {
+ int fptag;
+ fptag = 0;
+ for(i = 0; i < 8; i++) {
+ fptag |= ((!env->fptags[i]) << i);
+ }
+ update_mxcsr_from_sse_status(env);
+ qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
+ env->fpuc,
+ (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
+ env->fpstt,
+ fptag,
+ env->mxcsr);
+ for(i=0;i<8;i++) {
+ CPU_LDoubleU u;
+ u.d = env->fpregs[i].d;
+ qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
+ i, u.l.lower, u.l.upper);
+ if ((i & 1) == 1)
+ qemu_fprintf(f, "\n");
+ else
+ qemu_fprintf(f, " ");
+ }
+ if (env->hflags & HF_CS64_MASK)
+ nb = 16;
+ else
+ nb = 8;
+ for(i=0;i<nb;i++) {
+ qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
+ i,
+ env->xmm_regs[i].ZMM_L(3),
+ env->xmm_regs[i].ZMM_L(2),
+ env->xmm_regs[i].ZMM_L(1),
+ env->xmm_regs[i].ZMM_L(0));
+ if ((i & 1) == 1)
+ qemu_fprintf(f, "\n");
+ else
+ qemu_fprintf(f, " ");
+ }
+ }
+ if (flags & CPU_DUMP_CODE) {
+ target_ulong base = env->segs[R_CS].base + env->eip;
+ target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
+ uint8_t code;
+ char codestr[3];
+
+ qemu_fprintf(f, "Code=");
+ for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
+ if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
+ snprintf(codestr, sizeof(codestr), "%02x", code);
+ } else {
+ snprintf(codestr, sizeof(codestr), "??");
+ }
+ qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
+ i == offs ? "<" : "", codestr, i == offs ? ">" : "");
+ }
+ qemu_fprintf(f, "\n");
+ }
+}
+
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9ecda75aec..d6ed45c5d7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2232,6 +2232,7 @@ void enable_compat_apic_id_mode(void);
#define APIC_DEFAULT_ADDRESS 0xfee00000
#define APIC_SPACE_SIZE 0x100000
+/* cpu-dump.c */
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
/* cpu.c */
diff --git a/target/i386/helper.c b/target/i386/helper.c
index a1b3367ab2..6e7e0f507c 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -21,8 +21,6 @@
#include "qapi/qapi-events-run-state.h"
#include "cpu.h"
#include "exec/exec-all.h"
-#include "qemu/qemu-print.h"
-#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
@@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env)
return 0;
}
-/***********************************************************/
-/* x86 debug */
-
-static const char *cc_op_str[CC_OP_NB] = {
- "DYNAMIC",
- "EFLAGS",
-
- "MULB",
- "MULW",
- "MULL",
- "MULQ",
-
- "ADDB",
- "ADDW",
- "ADDL",
- "ADDQ",
-
- "ADCB",
- "ADCW",
- "ADCL",
- "ADCQ",
-
- "SUBB",
- "SUBW",
- "SUBL",
- "SUBQ",
-
- "SBBB",
- "SBBW",
- "SBBL",
- "SBBQ",
-
- "LOGICB",
- "LOGICW",
- "LOGICL",
- "LOGICQ",
-
- "INCB",
- "INCW",
- "INCL",
- "INCQ",
-
- "DECB",
- "DECW",
- "DECL",
- "DECQ",
-
- "SHLB",
- "SHLW",
- "SHLL",
- "SHLQ",
-
- "SARB",
- "SARW",
- "SARL",
- "SARQ",
-
- "BMILGB",
- "BMILGW",
- "BMILGL",
- "BMILGQ",
-
- "ADCX",
- "ADOX",
- "ADCOX",
-
- "CLR",
-};
-
-static void
-cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
- const char *name, struct SegmentCache *sc)
-{
-#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
- sc->selector, sc->base, sc->limit,
- sc->flags & 0x00ffff00);
- } else
-#endif
- {
- qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
- (uint32_t)sc->base, sc->limit,
- sc->flags & 0x00ffff00);
- }
-
- if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
- goto done;
-
- qemu_fprintf(f, " DPL=%d ",
- (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
- if (sc->flags & DESC_S_MASK) {
- if (sc->flags & DESC_CS_MASK) {
- qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
- ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
- qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
- (sc->flags & DESC_R_MASK) ? 'R' : '-');
- } else {
- qemu_fprintf(f, (sc->flags & DESC_B_MASK
- || env->hflags & HF_LMA_MASK)
- ? "DS " : "DS16");
- qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
- (sc->flags & DESC_W_MASK) ? 'W' : '-');
- }
- qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
- } else {
- static const char *sys_type_name[2][16] = {
- { /* 32 bit mode */
- "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
- "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
- "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
- "CallGate32", "Reserved", "IntGate32", "TrapGate32"
- },
- { /* 64 bit mode */
- "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
- "Reserved", "Reserved", "Reserved", "Reserved",
- "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
- "Reserved", "IntGate64", "TrapGate64"
- }
- };
- qemu_fprintf(f, "%s",
- sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
- [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
- }
-done:
- qemu_fprintf(f, "\n");
-}
-
-#ifndef CONFIG_USER_ONLY
-
-/* ARRAY_SIZE check is not required because
- * DeliveryMode(dm) has a size of 3 bit.
- */
-static inline const char *dm2str(uint32_t dm)
-{
- static const char *str[] = {
- "Fixed",
- "...",
- "SMI",
- "...",
- "NMI",
- "INIT",
- "...",
- "ExtINT"
- };
- return str[dm];
-}
-
-static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
-{
- uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
- qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
- name, lvt,
- lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
- lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
- lvt & APIC_LVT_MASKED ? "masked" : "",
- lvt & APIC_LVT_DELIV_STS ? "pending" : "",
- !is_timer ?
- "" : lvt & APIC_LVT_TIMER_PERIODIC ?
- "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
- "tsc-deadline" : "one-shot",
- dm2str(dm));
- if (dm != APIC_DM_NMI) {
- qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
- } else {
- qemu_printf("\n");
- }
-}
-
-/* ARRAY_SIZE check is not required because
- * destination shorthand has a size of 2 bit.
- */
-static inline const char *shorthand2str(uint32_t shorthand)
-{
- const char *str[] = {
- "no-shorthand", "self", "all-self", "all"
- };
- return str[shorthand];
-}
-
-static inline uint8_t divider_conf(uint32_t divide_conf)
-{
- uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
-
- return divide_val == 7 ? 1 : 2 << divide_val;
-}
-
-static inline void mask2str(char *str, uint32_t val, uint8_t size)
-{
- while (size--) {
- *str++ = (val >> size) & 1 ? '1' : '0';
- }
- *str = 0;
-}
-
-#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
-
-static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
-{
- uint32_t icr = s->icr[0], icr2 = s->icr[1];
- uint8_t dest_shorthand = \
- (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
- bool logical_mod = icr & APIC_ICR_DEST_MOD;
- char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
- uint32_t dest_field;
- bool x2apic;
-
- qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
- icr,
- logical_mod ? "logical" : "physical",
- icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
- icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
- shorthand2str(dest_shorthand));
-
- qemu_printf("ICR2\t 0x%08x", icr2);
- if (dest_shorthand != 0) {
- qemu_printf("\n");
- return;
- }
- x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
- dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
-
- if (!logical_mod) {
- if (x2apic) {
- qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
- } else {
- qemu_printf(" cpu %u (APIC ID)\n",
- dest_field & APIC_LOGDEST_XAPIC_ID);
- }
- return;
- }
-
- if (s->dest_mode == 0xf) { /* flat mode */
- mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
- qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
- } else if (s->dest_mode == 0) { /* cluster mode */
- if (x2apic) {
- mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
- qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
- dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
- } else {
- mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
- qemu_printf(" cluster %u mask %s (APIC ID)\n",
- dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
- }
- }
-}
-
-static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
- uint32_t *tmr_tab)
-{
- int i, empty = true;
-
- qemu_printf("%s\t ", name);
- for (i = 0; i < 256; i++) {
- if (apic_get_bit(ireg_tab, i)) {
- qemu_printf("%u%s ", i,
- apic_get_bit(tmr_tab, i) ? "(level)" : "");
- empty = false;
- }
- }
- qemu_printf("%s\n", empty ? "(none)" : "");
-}
-
-void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
-{
- X86CPU *cpu = X86_CPU(cs);
- APICCommonState *s = APIC_COMMON(cpu->apic_state);
- if (!s) {
- qemu_printf("local apic state not available\n");
- return;
- }
- uint32_t *lvt = s->lvt;
-
- qemu_printf("dumping local APIC state for CPU %-2u\n\n",
- CPU(cpu)->cpu_index);
- dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
- dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
- dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
- dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
- dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
- dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
-
- qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
- " current_count = %u\n",
- s->divide_conf & APIC_DCR_MASK,
- divider_conf(s->divide_conf),
- s->initial_count, apic_get_current_count(s));
-
- qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
- s->spurious_vec,
- s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
- s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
- s->spurious_vec & APIC_VECTOR_MASK);
-
- dump_apic_icr(s, &cpu->env);
-
- qemu_printf("ESR\t 0x%08x\n", s->esr);
-
- dump_apic_interrupt("ISR", s->isr, s->tmr);
- dump_apic_interrupt("IRR", s->irr, s->tmr);
-
- qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
- s->arb_id, s->tpr, s->dest_mode, s->log_dest);
- if (s->dest_mode == 0) {
- qemu_printf("(cluster %u: id %u)",
- s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
- s->log_dest & APIC_LOGDEST_XAPIC_ID);
- }
- qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
-}
-#else
-void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
-{
-}
-#endif /* !CONFIG_USER_ONLY */
-
-#define DUMP_CODE_BYTES_TOTAL 50
-#define DUMP_CODE_BYTES_BACKWARD 20
-
-void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
- int eflags, i, nb;
- char cc_op_name[32];
- static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
-
- eflags = cpu_compute_eflags(env);
-#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
- "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
- "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
- "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
- "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
- env->regs[R_EAX],
- env->regs[R_EBX],
- env->regs[R_ECX],
- env->regs[R_EDX],
- env->regs[R_ESI],
- env->regs[R_EDI],
- env->regs[R_EBP],
- env->regs[R_ESP],
- env->regs[8],
- env->regs[9],
- env->regs[10],
- env->regs[11],
- env->regs[12],
- env->regs[13],
- env->regs[14],
- env->regs[15],
- env->eip, eflags,
- eflags & DF_MASK ? 'D' : '-',
- eflags & CC_O ? 'O' : '-',
- eflags & CC_S ? 'S' : '-',
- eflags & CC_Z ? 'Z' : '-',
- eflags & CC_A ? 'A' : '-',
- eflags & CC_P ? 'P' : '-',
- eflags & CC_C ? 'C' : '-',
- env->hflags & HF_CPL_MASK,
- (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (env->a20_mask >> 20) & 1,
- (env->hflags >> HF_SMM_SHIFT) & 1,
- cs->halted);
- } else
-#endif
- {
- qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
- "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
- "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
- (uint32_t)env->regs[R_EAX],
- (uint32_t)env->regs[R_EBX],
- (uint32_t)env->regs[R_ECX],
- (uint32_t)env->regs[R_EDX],
- (uint32_t)env->regs[R_ESI],
- (uint32_t)env->regs[R_EDI],
- (uint32_t)env->regs[R_EBP],
- (uint32_t)env->regs[R_ESP],
- (uint32_t)env->eip, eflags,
- eflags & DF_MASK ? 'D' : '-',
- eflags & CC_O ? 'O' : '-',
- eflags & CC_S ? 'S' : '-',
- eflags & CC_Z ? 'Z' : '-',
- eflags & CC_A ? 'A' : '-',
- eflags & CC_P ? 'P' : '-',
- eflags & CC_C ? 'C' : '-',
- env->hflags & HF_CPL_MASK,
- (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (env->a20_mask >> 20) & 1,
- (env->hflags >> HF_SMM_SHIFT) & 1,
- cs->halted);
- }
-
- for(i = 0; i < 6; i++) {
- cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
- }
- cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
- cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
-
-#ifdef TARGET_X86_64
- if (env->hflags & HF_LMA_MASK) {
- qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
- env->gdt.base, env->gdt.limit);
- qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
- env->idt.base, env->idt.limit);
- qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
- (uint32_t)env->cr[0],
- env->cr[2],
- env->cr[3],
- (uint32_t)env->cr[4]);
- for(i = 0; i < 4; i++)
- qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
- qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
- env->dr[6], env->dr[7]);
- } else
-#endif
- {
- qemu_fprintf(f, "GDT= %08x %08x\n",
- (uint32_t)env->gdt.base, env->gdt.limit);
- qemu_fprintf(f, "IDT= %08x %08x\n",
- (uint32_t)env->idt.base, env->idt.limit);
- qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
- (uint32_t)env->cr[0],
- (uint32_t)env->cr[2],
- (uint32_t)env->cr[3],
- (uint32_t)env->cr[4]);
- for(i = 0; i < 4; i++) {
- qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
- }
- qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
- env->dr[6], env->dr[7]);
- }
- if (flags & CPU_DUMP_CCOP) {
- if ((unsigned)env->cc_op < CC_OP_NB)
- snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
- else
- snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
-#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
- env->cc_src, env->cc_dst,
- cc_op_name);
- } else
-#endif
- {
- qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
- (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
- cc_op_name);
- }
- }
- qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
- if (flags & CPU_DUMP_FPU) {
- int fptag;
- fptag = 0;
- for(i = 0; i < 8; i++) {
- fptag |= ((!env->fptags[i]) << i);
- }
- update_mxcsr_from_sse_status(env);
- qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
- env->fpuc,
- (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
- env->fpstt,
- fptag,
- env->mxcsr);
- for(i=0;i<8;i++) {
- CPU_LDoubleU u;
- u.d = env->fpregs[i].d;
- qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
- i, u.l.lower, u.l.upper);
- if ((i & 1) == 1)
- qemu_fprintf(f, "\n");
- else
- qemu_fprintf(f, " ");
- }
- if (env->hflags & HF_CS64_MASK)
- nb = 16;
- else
- nb = 8;
- for(i=0;i<nb;i++) {
- qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
- i,
- env->xmm_regs[i].ZMM_L(3),
- env->xmm_regs[i].ZMM_L(2),
- env->xmm_regs[i].ZMM_L(1),
- env->xmm_regs[i].ZMM_L(0));
- if ((i & 1) == 1)
- qemu_fprintf(f, "\n");
- else
- qemu_fprintf(f, " ");
- }
- }
- if (flags & CPU_DUMP_CODE) {
- target_ulong base = env->segs[R_CS].base + env->eip;
- target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
- uint8_t code;
- char codestr[3];
-
- qemu_fprintf(f, "Code=");
- for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
- if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
- snprintf(codestr, sizeof(codestr), "%02x", code);
- } else {
- snprintf(codestr, sizeof(codestr), "??");
- }
- qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
- i == offs ? "<" : "", codestr, i == offs ? ">" : "");
- }
- qemu_fprintf(f, "\n");
- }
-}
-
/***********************************************************/
/* x86 mmu */
/* XXX: add PGE support */
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 750471c9f3..c4bf20b319 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -4,6 +4,7 @@ i386_ss.add(files(
'gdbstub.c',
'helper.c',
'xsave_helper.c',
+ 'cpu-dump.c',
))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (5 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 06/11] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-27 19:04 ` Eduardo Habkost
2020-11-26 22:32 ` [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode Claudio Fontana
` (3 subsequent siblings)
10 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/i386/cpu.c | 33 ++++------
target/i386/cpu.h | 97 ++---------------------------
target/i386/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++
target/i386/helper.c | 23 -------
target/i386/meson.build | 1 +
target/i386/tcg-cpu.c | 71 +++++++++++++++++++++
target/i386/tcg-cpu.h | 15 +++++
target/i386/tcg/bpt_helper.c | 1 +
target/i386/tcg/cc_helper.c | 1 +
target/i386/tcg/excp_helper.c | 1 +
target/i386/tcg/fpu_helper.c | 33 +++++-----
target/i386/tcg/int_helper.c | 1 +
target/i386/tcg/mem_helper.c | 1 +
target/i386/tcg/misc_helper.c | 1 +
target/i386/tcg/mpx_helper.c | 1 +
target/i386/tcg/seg_helper.c | 1 +
target/i386/tcg/smm_helper.c | 2 +
target/i386/tcg/svm_helper.c | 1 +
target/i386/tcg/translate.c | 1 +
19 files changed, 244 insertions(+), 153 deletions(-)
create mode 100644 target/i386/helper-tcg.h
create mode 100644 target/i386/tcg-cpu.c
create mode 100644 target/i386/tcg-cpu.h
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b9bd249c8f..3462d0143f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -24,6 +24,8 @@
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "tcg-cpu.h"
+#include "helper-tcg.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
@@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
cpu->env.features[FEAT_XSAVE_COMP_LO];
}
-const char *get_register_name_32(unsigned int reg)
+/* Return name of 32-bit register, from a R_* constant */
+static const char *get_register_name_32(unsigned int reg)
{
if (reg >= CPU_NB_REGS32) {
return NULL;
@@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.eip = value;
}
-static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
-{
- X86CPU *cpu = X86_CPU(cs);
-
- cpu->env.eip = tb->pc - tb->cs_base;
-}
-
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
@@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
+
#ifdef CONFIG_TCG
- cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
-#endif
+ tcg_cpu_common_class_init(cc);
+#endif /* CONFIG_TCG */
+
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
- cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
+
#ifndef CONFIG_USER_ONLY
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
@@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
-#endif
+#endif /* !CONFIG_USER_ONLY */
+
cc->gdb_arch_name = x86_gdb_arch_name;
#ifdef TARGET_X86_64
cc->gdb_core_xml_file = "i386-64bit.xml";
@@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#else
cc->gdb_core_xml_file = "i386-32bit.xml";
cc->gdb_num_core_regs = 50;
-#endif
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- cc->debug_excp_handler = breakpoint_handler;
-#endif
- cc->cpu_exec_enter = x86_cpu_exec_enter;
- cc->cpu_exec_exit = x86_cpu_exec_exit;
-#ifdef CONFIG_TCG
- cc->tcg_initialize = tcg_x86_init;
- cc->tlb_fill = x86_cpu_tlb_fill;
#endif
cc->disas_set_info = x86_disas_set_info;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d6ed45c5d7..a0d64613dc 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -31,9 +31,6 @@
#define KVM_HAVE_MCE_INJECTION 1
-/* Maximum instruction code size */
-#define TARGET_MAX_INSN_SIZE 16
-
/* support for self modifying code even if the modified instruction is
close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
@@ -1037,6 +1034,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
* using this information. Condition codes are not generated if they
* are only needed for conditional branches.
*/
+
+#define CC_DST (env->cc_dst)
+#define CC_SRC (env->cc_src)
+#define CC_SRC2 (env->cc_src2)
+#define CC_OP (env->cc_op)
+
typedef enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
@@ -1765,12 +1768,6 @@ struct X86CPU {
extern VMStateDescription vmstate_x86_cpu;
#endif
-/**
- * x86_cpu_do_interrupt:
- * @cpu: vCPU the interrupt is to be handled by.
- */
-void x86_cpu_do_interrupt(CPUState *cpu);
-bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -1793,9 +1790,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void x86_cpu_exec_enter(CPUState *cpu);
-void x86_cpu_exec_exit(CPUState *cpu);
-
void x86_cpu_list(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@@ -1920,9 +1914,6 @@ void host_cpuid(uint32_t function, uint32_t count,
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
/* helper.c */
-bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
#ifndef CONFIG_USER_ONLY
@@ -1947,8 +1938,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
#endif
-void breakpoint_handler(CPUState *cs);
-
/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
@@ -1958,16 +1947,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
-/* XXX: This value should match the one returned by CPUID
- * and in exec.c */
-# if defined(TARGET_X86_64)
-# define TCG_PHYS_ADDR_BITS 40
-# else
-# define TCG_PHYS_ADDR_BITS 36
-# endif
-
-#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
-
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
@@ -1999,30 +1978,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
}
-#define CC_DST (env->cc_dst)
-#define CC_SRC (env->cc_src)
-#define CC_SRC2 (env->cc_src2)
-#define CC_OP (env->cc_op)
-
-/* n must be a constant to be efficient */
-static inline target_long lshift(target_long x, int n)
-{
- if (n >= 0) {
- return x << n;
- } else {
- return x >> (-n);
- }
-}
-
-/* float macros */
-#define FT0 (env->ft0)
-#define ST0 (env->fpregs[env->fpstt].d)
-#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
-#define ST1 ST(1)
-
-/* translate.c */
-void tcg_x86_init(void);
-
typedef CPUX86State CPUArchState;
typedef X86CPU ArchCPU;
@@ -2052,19 +2007,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
uint64_t status, uint64_t mcg_status, uint64_t addr,
uint64_t misc, int flags);
-/* excp_helper.c */
-void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
-void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
- uintptr_t retaddr);
-void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
- int error_code);
-void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
- int error_code, uintptr_t retaddr);
-void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
- int error_code, int next_eip_addend);
-
-/* cc_helper.c */
-extern const uint8_t parity_table[256];
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
static inline uint32_t cpu_compute_eflags(CPUX86State *env)
@@ -2076,18 +2018,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env)
return eflags;
}
-/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
- * after generating a call to a helper that uses this.
- */
-static inline void cpu_load_eflags(CPUX86State *env, int eflags,
- int update_mask)
-{
- CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- CC_OP = CC_OP_EFLAGS;
- env->df = 1 - (2 * ((eflags >> 10) & 1));
- env->eflags = (env->eflags & ~update_mask) |
- (eflags & update_mask) | 0x2;
-}
/* load efer and update the corresponding hflags. XXX: do consistency
checks with cpuid bits? */
@@ -2176,16 +2106,6 @@ void helper_lock_init(void);
/* svm_helper.c */
void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
uint64_t param, uintptr_t retaddr);
-void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
- uint64_t exit_info_1, uintptr_t retaddr);
-void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
-
-/* seg_helper.c */
-void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
-
-/* smm_helper.c */
-void do_smm_enter(X86CPU *cpu);
-
/* apic.c */
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
@@ -2224,11 +2144,6 @@ typedef int X86CPUVersion;
*/
void x86_cpu_set_default_version(X86CPUVersion version);
-/* Return name of 32-bit register, from a R_* constant */
-const char *get_register_name_32(unsigned int reg);
-
-void enable_compat_apic_id_mode(void);
-
#define APIC_DEFAULT_ADDRESS 0xfee00000
#define APIC_SPACE_SIZE 0x100000
diff --git a/target/i386/helper-tcg.h b/target/i386/helper-tcg.h
new file mode 100644
index 0000000000..57b4391a7d
--- /dev/null
+++ b/target/i386/helper-tcg.h
@@ -0,0 +1,112 @@
+/*
+ * TCG specific prototypes for helpers
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef I386_HELPER_TCG_H
+#define I386_HELPER_TCG_H
+
+#include "exec/exec-all.h"
+
+/* Maximum instruction code size */
+#define TARGET_MAX_INSN_SIZE 16
+
+/*
+ * XXX: This value should match the one returned by CPUID
+ * and in exec.c
+ */
+# if defined(TARGET_X86_64)
+# define TCG_PHYS_ADDR_BITS 40
+# else
+# define TCG_PHYS_ADDR_BITS 36
+# endif
+
+#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
+
+/**
+ * x86_cpu_do_interrupt:
+ * @cpu: vCPU the interrupt is to be handled by.
+ */
+void x86_cpu_do_interrupt(CPUState *cpu);
+bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
+/* helper.c */
+bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+
+void breakpoint_handler(CPUState *cs);
+
+/* n must be a constant to be efficient */
+static inline target_long lshift(target_long x, int n)
+{
+ if (n >= 0) {
+ return x << n;
+ } else {
+ return x >> (-n);
+ }
+}
+
+/* float macros */
+#define FT0 (env->ft0)
+#define ST0 (env->fpregs[env->fpstt].d)
+#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
+#define ST1 ST(1)
+
+/* translate.c */
+void tcg_x86_init(void);
+
+/* excp_helper.c */
+void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
+void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
+ uintptr_t retaddr);
+void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
+ int error_code);
+void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
+ int error_code, uintptr_t retaddr);
+void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
+ int error_code, int next_eip_addend);
+
+/* cc_helper.c */
+extern const uint8_t parity_table[256];
+
+/*
+ * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
+ * after generating a call to a helper that uses this.
+ */
+static inline void cpu_load_eflags(CPUX86State *env, int eflags,
+ int update_mask)
+{
+ CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+ CC_OP = CC_OP_EFLAGS;
+ env->df = 1 - (2 * ((eflags >> 10) & 1));
+ env->eflags = (env->eflags & ~update_mask) |
+ (eflags & update_mask) | 0x2;
+}
+
+/* svm_helper.c */
+void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
+ uint64_t exit_info_1, uintptr_t retaddr);
+void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
+
+/* seg_helper.c */
+void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
+
+/* smm_helper.c */
+void do_smm_enter(X86CPU *cpu);
+
+#endif /* I386_HELPER_TCG_H */
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 6e7e0f507c..6bb0c53182 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -24,10 +24,8 @@
#include "sysemu/runstate.h"
#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
-#include "sysemu/tcg.h"
#include "sysemu/hw_accel.h"
#include "monitor/monitor.h"
-#include "hw/i386/apic_internal.h"
#endif
void cpu_sync_bndcs_hflags(CPUX86State *env)
@@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu)
}
#endif
-/* Frob eflags into and out of the CPU temporary format. */
-
-void x86_cpu_exec_enter(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- env->df = 1 - (2 * ((env->eflags >> 10) & 1));
- CC_OP = CC_OP_EFLAGS;
- env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
-}
-
-void x86_cpu_exec_exit(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- env->eflags = cpu_compute_eflags(env);
-}
-
#ifndef CONFIG_USER_ONLY
uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
{
diff --git a/target/i386/meson.build b/target/i386/meson.build
index c4bf20b319..9c20208e5a 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -6,6 +6,7 @@ i386_ss.add(files(
'xsave_helper.c',
'cpu-dump.c',
))
+i386_ss.add(when: 'CONFIG_TCG', if_true: files('tcg-cpu.c'))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
i386_softmmu_ss = ss.source_set()
diff --git a/target/i386/tcg-cpu.c b/target/i386/tcg-cpu.c
new file mode 100644
index 0000000000..628dd29fe7
--- /dev/null
+++ b/target/i386/tcg-cpu.c
@@ -0,0 +1,71 @@
+/*
+ * i386 TCG cpu class initialization
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg-cpu.h"
+#include "exec/exec-all.h"
+#include "sysemu/runstate.h"
+#include "helper-tcg.h"
+
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/i386/apic.h"
+#endif
+
+/* Frob eflags into and out of the CPU temporary format. */
+
+static void x86_cpu_exec_enter(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+ env->df = 1 - (2 * ((env->eflags >> 10) & 1));
+ CC_OP = CC_OP_EFLAGS;
+ env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+}
+
+static void x86_cpu_exec_exit(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ env->eflags = cpu_compute_eflags(env);
+}
+
+static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ cpu->env.eip = tb->pc - tb->cs_base;
+}
+
+void tcg_cpu_common_class_init(CPUClass *cc)
+{
+ cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->cpu_exec_enter = x86_cpu_exec_enter;
+ cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_initialize = tcg_x86_init;
+ cc->tlb_fill = x86_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->debug_excp_handler = breakpoint_handler;
+#endif
+}
diff --git a/target/i386/tcg-cpu.h b/target/i386/tcg-cpu.h
new file mode 100644
index 0000000000..81f02e562e
--- /dev/null
+++ b/target/i386/tcg-cpu.h
@@ -0,0 +1,15 @@
+/*
+ * i386 TCG CPU class initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPU_H
+#define TCG_CPU_H
+
+void tcg_cpu_common_class_init(CPUClass *cc);
+
+#endif /* TCG_CPU_H */
diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c
index e6cc2921e2..979230ac12 100644
--- a/target/i386/tcg/bpt_helper.c
+++ b/target/i386/tcg/bpt_helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "helper-tcg.h"
#ifndef CONFIG_USER_ONLY
diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c
index 924dd3cd57..cc7ea9e8b9 100644
--- a/target/i386/tcg/cc_helper.c
+++ b/target/i386/tcg/cc_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "helper-tcg.h"
const uint8_t parity_table[256] = {
CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c
index 191471749f..a0f44431fe 100644
--- a/target/i386/tcg/excp_helper.c
+++ b/target/i386/tcg/excp_helper.c
@@ -23,6 +23,7 @@
#include "qemu/log.h"
#include "sysemu/runstate.h"
#include "exec/helper-proto.h"
+#include "helper-tcg.h"
void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
{
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 03b35443a6..13f31b6ac7 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -26,6 +26,7 @@
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
#include "fpu/softfloat-macros.h"
+#include "helper-tcg.h"
#ifdef CONFIG_SOFTMMU
#include "hw/irq.h"
@@ -2986,23 +2987,21 @@ void update_mxcsr_status(CPUX86State *env)
void update_mxcsr_from_sse_status(CPUX86State *env)
{
- if (tcg_enabled()) {
- uint8_t flags = get_float_exception_flags(&env->sse_status);
- /*
- * The MXCSR denormal flag has opposite semantics to
- * float_flag_input_denormal (the softfloat code sets that flag
- * only when flushing input denormals to zero, but SSE sets it
- * only when not flushing them to zero), so is not converted
- * here.
- */
- env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
- (flags & float_flag_divbyzero ? FPUS_ZE : 0) |
- (flags & float_flag_overflow ? FPUS_OE : 0) |
- (flags & float_flag_underflow ? FPUS_UE : 0) |
- (flags & float_flag_inexact ? FPUS_PE : 0) |
- (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
- 0));
- }
+ uint8_t flags = get_float_exception_flags(&env->sse_status);
+ /*
+ * The MXCSR denormal flag has opposite semantics to
+ * float_flag_input_denormal (the softfloat code sets that flag
+ * only when flushing input denormals to zero, but SSE sets it
+ * only when not flushing them to zero), so is not converted
+ * here.
+ */
+ env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
+ (flags & float_flag_divbyzero ? FPUS_ZE : 0) |
+ (flags & float_flag_overflow ? FPUS_OE : 0) |
+ (flags & float_flag_underflow ? FPUS_UE : 0) |
+ (flags & float_flag_inexact ? FPUS_PE : 0) |
+ (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
+ 0));
}
void helper_update_mxcsr(CPUX86State *env)
diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c
index 4f89436b53..87fa7280ee 100644
--- a/target/i386/tcg/int_helper.c
+++ b/target/i386/tcg/int_helper.c
@@ -24,6 +24,7 @@
#include "exec/helper-proto.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
+#include "helper-tcg.h"
//#define DEBUG_MULDIV
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
index 21ca3e3e88..e5cd2de1bf 100644
--- a/target/i386/tcg/mem_helper.c
+++ b/target/i386/tcg/mem_helper.c
@@ -25,6 +25,7 @@
#include "qemu/int128.h"
#include "qemu/atomic128.h"
#include "tcg/tcg.h"
+#include "helper-tcg.h"
void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
{
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index ae259d9145..c99370e5e3 100644
--- a/target/i386/tcg/misc_helper.c
+++ b/target/i386/tcg/misc_helper.c
@@ -24,6 +24,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
+#include "helper-tcg.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{
diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c
index fd966174b4..22423eedcd 100644
--- a/target/i386/tcg/mpx_helper.c
+++ b/target/i386/tcg/mpx_helper.c
@@ -22,6 +22,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
+#include "helper-tcg.h"
void helper_bndck(CPUX86State *env, uint32_t fail)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 09b6554660..ed3e04a187 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -25,6 +25,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
+#include "helper-tcg.h"
//#define DEBUG_PCALL
diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c
index d20e8edfdf..62d027abd3 100644
--- a/target/i386/tcg/smm_helper.c
+++ b/target/i386/tcg/smm_helper.c
@@ -22,6 +22,8 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/log.h"
+#include "helper-tcg.h"
+
/* SMM support */
diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c
index 38931586e5..097bb9b83d 100644
--- a/target/i386/tcg/svm_helper.c
+++ b/target/i386/tcg/svm_helper.c
@@ -22,6 +22,7 @@
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "helper-tcg.h"
/* Secure Virtual Machine helpers */
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 4c57307e42..5988ea0289 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -28,6 +28,7 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "helper-tcg.h"
#include "trace-tcg.h"
#include "exec/log.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (6 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2021-01-11 18:43 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 09/11] accel: replace struct CpusAccel with AccelOpsClass Claudio Fontana
` (2 subsequent siblings)
10 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 2 +-
accel/accel-common.c | 50 ++++++++++++++++++++++++++++++
accel/{accel.c => accel-softmmu.c} | 27 ++--------------
accel/accel-user.c | 24 ++++++++++++++
accel/meson.build | 4 ++-
accel/qtest/qtest.c | 2 +-
accel/tcg/meson.build | 2 +-
accel/tcg/tcg-all.c | 7 ++++-
accel/xen/xen-all.c | 2 +-
bsd-user/main.c | 7 +++--
include/hw/boards.h | 2 +-
include/{sysemu => qemu}/accel.h | 14 +++++----
include/sysemu/hvf.h | 2 +-
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 2 +-
linux-user/main.c | 7 +++--
softmmu/memory.c | 2 +-
softmmu/qtest.c | 2 +-
softmmu/vl.c | 2 +-
target/i386/hax/hax-all.c | 2 +-
target/i386/hvf/hvf-i386.h | 2 +-
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86_task.c | 2 +-
target/i386/whpx/whpx-all.c | 2 +-
24 files changed, 119 insertions(+), 53 deletions(-)
create mode 100644 accel/accel-common.c
rename accel/{accel.c => accel-softmmu.c} (75%)
create mode 100644 accel/accel-user.c
rename include/{sysemu => qemu}/accel.h (95%)
diff --git a/MAINTAINERS b/MAINTAINERS
index e892dd2220..d7c212843c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -433,7 +433,7 @@ Overall
M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
-F: include/sysemu/accel.h
+F: include/qemu/accel.h
F: accel/accel.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/accel-common.c b/accel/accel-common.c
new file mode 100644
index 0000000000..ddec8cb5ae
--- /dev/null
+++ b/accel/accel-common.c
@@ -0,0 +1,50 @@
+/*
+ * QEMU accel class, components common to system emulation and user mode
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/accel.h"
+
+static const TypeInfo accel_type = {
+ .name = TYPE_ACCEL,
+ .parent = TYPE_OBJECT,
+ .class_size = sizeof(AccelClass),
+ .instance_size = sizeof(AccelState),
+};
+
+/* Lookup AccelClass from opt_name. Returns NULL if not found */
+AccelClass *accel_find(const char *opt_name)
+{
+ char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
+ AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
+ g_free(class_name);
+ return ac;
+}
+
+static void register_accel_types(void)
+{
+ type_register_static(&accel_type);
+}
+
+type_init(register_accel_types);
diff --git a/accel/accel.c b/accel/accel-softmmu.c
similarity index 75%
rename from accel/accel.c
rename to accel/accel-softmmu.c
index cb555e3b06..f89da8f9d1 100644
--- a/accel/accel.c
+++ b/accel/accel-softmmu.c
@@ -1,5 +1,5 @@
/*
- * QEMU System Emulator, accelerator interfaces
+ * QEMU accel class, system emulation components
*
* Copyright (c) 2003-2008 Fabrice Bellard
* Copyright (c) 2014 Red Hat Inc.
@@ -24,28 +24,12 @@
*/
#include "qemu/osdep.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/boards.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
#include "qom/object.h"
-static const TypeInfo accel_type = {
- .name = TYPE_ACCEL,
- .parent = TYPE_OBJECT,
- .class_size = sizeof(AccelClass),
- .instance_size = sizeof(AccelState),
-};
-
-/* Lookup AccelClass from opt_name. Returns NULL if not found */
-AccelClass *accel_find(const char *opt_name)
-{
- char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
- AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
- g_free(class_name);
- return ac;
-}
-
int accel_init_machine(AccelState *accel, MachineState *ms)
{
AccelClass *acc = ACCEL_GET_CLASS(accel);
@@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms)
acc->setup_post(ms, accel);
}
}
-
-static void register_accel_types(void)
-{
- type_register_static(&accel_type);
-}
-
-type_init(register_accel_types);
diff --git a/accel/accel-user.c b/accel/accel-user.c
new file mode 100644
index 0000000000..26bdda6236
--- /dev/null
+++ b/accel/accel-user.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU accel class, user-mode components
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/accel.h"
+
+AccelState *current_accel(void)
+{
+ static AccelState *accel;
+
+ if (!accel) {
+ AccelClass *ac = accel_find("tcg");
+
+ g_assert(ac != NULL);
+ accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac)));
+ }
+ return accel;
+}
diff --git a/accel/meson.build b/accel/meson.build
index b26cca227a..b44ba30c86 100644
--- a/accel/meson.build
+++ b/accel/meson.build
@@ -1,4 +1,6 @@
-softmmu_ss.add(files('accel.c'))
+specific_ss.add(files('accel-common.c'))
+softmmu_ss.add(files('accel-softmmu.c'))
+user_ss.add(files('accel-user.c'))
subdir('qtest')
subdir('kvm')
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index b282cea5cf..b4e731cb2b 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -17,7 +17,7 @@
#include "qemu/module.h"
#include "qemu/option.h"
#include "qemu/config-file.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/qtest.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index f39aab0a0c..424d9bb1fc 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,5 +1,6 @@
tcg_ss = ss.source_set()
tcg_ss.add(files(
+ 'tcg-all.c',
'cpu-exec-common.c',
'cpu-exec.c',
'tcg-runtime-gvec.c',
@@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
- 'tcg-all.c',
'cputlb.c',
'tcg-cpus.c',
'tcg-cpus-mttcg.c',
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 1ac0b76515..dcbc6970da 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -30,9 +30,12 @@
#include "tcg/tcg.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
-#include "hw/boards.h"
+#include "qemu/accel.h"
#include "qapi/qapi-builtin-visit.h"
+
+#ifndef CONFIG_USER_ONLY
#include "tcg-cpus.h"
+#endif /* CONFIG_USER_ONLY */
struct TCGState {
AccelState parent_obj;
@@ -110,6 +113,7 @@ static int tcg_init(MachineState *ms)
*/
tcg_region_init();
+#ifndef CONFIG_USER_ONLY
if (mttcg_enabled) {
cpus_register_accel(&tcg_cpus_mttcg);
} else if (icount_enabled()) {
@@ -117,6 +121,7 @@ static int tcg_init(MachineState *ms)
} else {
cpus_register_accel(&tcg_cpus_rr);
}
+#endif /* CONFIG_USER_ONLY */
return 0;
}
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 878a4089d9..594aaf6b49 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -15,7 +15,7 @@
#include "hw/xen/xen-legacy-backend.h"
#include "hw/xen/xen_pt.h"
#include "chardev/char.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/cpus.h"
#include "sysemu/xen.h"
#include "sysemu/runstate.h"
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 0a918e8f74..ec1f9d80a4 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/units.h"
+#include "qemu/accel.h"
#include "sysemu/tcg.h"
#include "qemu-version.h"
#include <machine/trap.h>
@@ -908,8 +909,11 @@ int main(int argc, char **argv)
}
/* init tcg before creating CPUs and to get qemu_host_page_size */
- tcg_exec_init(0);
+ {
+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());
+ ac->init_machine(NULL);
+ }
cpu_type = parse_cpu_option(cpu_model);
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
@@ -988,7 +992,6 @@ int main(int argc, char **argv)
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
tcg_prologue_init(tcg_ctx);
- tcg_region_init();
/* build Task State */
memset(ts, 0, sizeof(TaskState));
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a49e3a6b44..b754504afe 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -6,7 +6,7 @@
#include "exec/memory.h"
#include "sysemu/hostmem.h"
#include "sysemu/blockdev.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qapi/qapi-types-machine.h"
#include "qemu/module.h"
#include "qom/object.h"
diff --git a/include/sysemu/accel.h b/include/qemu/accel.h
similarity index 95%
rename from include/sysemu/accel.h
rename to include/qemu/accel.h
index e08b8ab8fa..fac4a18703 100644
--- a/include/sysemu/accel.h
+++ b/include/qemu/accel.h
@@ -20,8 +20,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#ifndef HW_ACCEL_H
-#define HW_ACCEL_H
+#ifndef QEMU_ACCEL_H
+#define QEMU_ACCEL_H
#include "qom/object.h"
#include "exec/hwaddr.h"
@@ -37,8 +37,8 @@ typedef struct AccelClass {
/*< public >*/
const char *name;
-#ifndef CONFIG_USER_ONLY
int (*init_machine)(MachineState *ms);
+#ifndef CONFIG_USER_ONLY
void (*setup_post)(MachineState *ms, AccelState *accel);
bool (*has_memory)(MachineState *ms, AddressSpace *as,
hwaddr start_addr, hwaddr size);
@@ -67,11 +67,13 @@ typedef struct AccelClass {
OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL)
AccelClass *accel_find(const char *opt_name);
+AccelState *current_accel(void);
+
+#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
/* Called just before os_setup_post (ie just before drop OS privs) */
void accel_setup_post(MachineState *ms);
+#endif /* !CONFIG_USER_ONLY */
-AccelState *current_accel(void);
-
-#endif
+#endif /* QEMU_ACCEL_H */
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index f893768df9..c98636bc81 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -13,7 +13,7 @@
#ifndef HVF_H
#define HVF_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef CONFIG_HVF
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index bb5d5cf497..739682f3c3 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -17,7 +17,7 @@
#include "qemu/queue.h"
#include "hw/core/cpu.h"
#include "exec/memattrs.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef NEED_CPU_H
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 65740806da..ccb8869f01 100644
--- a/include/sysemu/kvm_int.h
+++ b/include/sysemu/kvm_int.h
@@ -10,7 +10,7 @@
#define QEMU_KVM_INT_H
#include "exec/memory.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/kvm.h"
typedef struct KVMSlot
diff --git a/linux-user/main.c b/linux-user/main.c
index 24d1eb73ad..1825d2b835 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/units.h"
+#include "qemu/accel.h"
#include "sysemu/tcg.h"
#include "qemu-version.h"
#include <sys/syscall.h>
@@ -703,8 +704,11 @@ int main(int argc, char **argv, char **envp)
cpu_type = parse_cpu_option(cpu_model);
/* init tcg before creating CPUs and to get qemu_host_page_size */
- tcg_exec_init(0);
+ {
+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());
+ ac->init_machine(NULL);
+ }
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
cpu_reset(cpu);
@@ -846,7 +850,6 @@ int main(int argc, char **argv, char **envp)
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
tcg_prologue_init(tcg_ctx);
- tcg_region_init();
target_cpu_copy_regs(env, regs);
diff --git a/softmmu/memory.c b/softmmu/memory.c
index aa393f1bb0..92c8b4fc1f 100644
--- a/softmmu/memory.c
+++ b/softmmu/memory.c
@@ -32,7 +32,7 @@
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "sysemu/tcg.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/boards.h"
#include "migration/vmstate.h"
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 7965dc9a16..130c366615 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -20,7 +20,7 @@
#include "exec/ioport.h"
#include "exec/memory.h"
#include "hw/irq.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/cpu-timers.h"
#include "qemu/config-file.h"
#include "qemu/option.h"
diff --git a/softmmu/vl.c b/softmmu/vl.c
index e6e0ad5a92..bc20c526d2 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -40,7 +40,7 @@
#include "qemu/error-report.h"
#include "qemu/sockets.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/usb.h"
#include "hw/isa/isa.h"
#include "hw/scsi/scsi.h"
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index fecfe8cd6e..d7f4bb44a7 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -28,7 +28,7 @@
#include "exec/address-spaces.h"
#include "qemu-common.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "hw/boards.h"
diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
index e0edffd077..50b914fd67 100644
--- a/target/i386/hvf/hvf-i386.h
+++ b/target/i386/hvf/hvf-i386.h
@@ -16,7 +16,7 @@
#ifndef HVF_I386_H
#define HVF_I386_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/hvf.h"
#include "cpu.h"
#include "x86.h"
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ed9356565c..ffc9efa40f 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -69,7 +69,7 @@
#include "exec/address-spaces.h"
#include "hw/i386/apic_internal.h"
#include "qemu/main-loop.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "target/i386/cpu.h"
#include "hvf-cpus.h"
diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
index 6f04478b3a..d66dfd7669 100644
--- a/target/i386/hvf/x86_task.c
+++ b/target/i386/hvf/x86_task.c
@@ -28,7 +28,7 @@
#include "hw/i386/apic_internal.h"
#include "qemu/main-loop.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "target/i386/cpu.h"
// TODO: taskswitch handling
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index f4f3e33eac..ee6b606194 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -13,7 +13,7 @@
#include "exec/address-spaces.h"
#include "exec/ioport.h"
#include "qemu-common.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/whpx.h"
#include "sysemu/cpus.h"
#include "sysemu/runstate.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 09/11] accel: replace struct CpusAccel with AccelOpsClass
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (7 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
2020-11-26 22:32 ` [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
10 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
centralize the registration of the cpus.c module
accelerator operations in accel/accel-softmmu.c
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 3 ++-
accel/accel-common.c | 11 +++++++++
accel/accel-softmmu.c | 43 +++++++++++++++++++++++++++++++---
accel/accel-softmmu.h | 15 ++++++++++++
accel/kvm/kvm-all.c | 2 --
accel/kvm/kvm-cpus.c | 26 ++++++++++++++++-----
accel/kvm/kvm-cpus.h | 2 --
accel/qtest/qtest.c | 23 +++++++++++++-----
accel/tcg/tcg-all.c | 14 -----------
accel/tcg/tcg-cpus-icount.c | 11 +--------
accel/tcg/tcg-cpus-icount.h | 2 ++
accel/tcg/tcg-cpus-mttcg.c | 12 +++-------
accel/tcg/tcg-cpus-mttcg.h | 19 +++++++++++++++
accel/tcg/tcg-cpus-rr.c | 7 ------
accel/tcg/tcg-cpus.c | 43 ++++++++++++++++++++++++++++++++++
accel/tcg/tcg-cpus.h | 4 ----
accel/xen/xen-all.c | 22 ++++++++++++------
bsd-user/main.c | 3 ++-
include/qemu/accel.h | 2 ++
include/sysemu/accel-ops.h | 45 ++++++++++++++++++++++++++++++++++++
include/sysemu/cpus.h | 26 ++++-----------------
linux-user/main.c | 1 +
softmmu/cpus.c | 12 +++++-----
softmmu/vl.c | 8 +++++--
target/i386/hax/hax-all.c | 3 ---
target/i386/hax/hax-cpus.c | 29 +++++++++++++++++------
target/i386/hax/hax-cpus.h | 2 --
target/i386/hvf/hvf-cpus.c | 27 +++++++++++++++++-----
target/i386/hvf/hvf-cpus.h | 2 --
target/i386/hvf/hvf.c | 1 -
target/i386/whpx/whpx-all.c | 2 --
target/i386/whpx/whpx-cpus.c | 29 +++++++++++++++++------
target/i386/whpx/whpx-cpus.h | 2 --
33 files changed, 320 insertions(+), 133 deletions(-)
create mode 100644 accel/accel-softmmu.h
create mode 100644 accel/tcg/tcg-cpus-mttcg.h
create mode 100644 include/sysemu/accel-ops.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d7c212843c..df64a0d190 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -434,7 +434,8 @@ M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
-F: accel/accel.c
+F: include/sysemu/accel-ops.h
+F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/accel-common.c b/accel/accel-common.c
index ddec8cb5ae..3910b7dbe0 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,10 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#ifndef CONFIG_USER_ONLY
+#include "accel-softmmu.h"
+#endif /* !CONFIG_USER_ONLY */
+
static const TypeInfo accel_type = {
.name = TYPE_ACCEL,
.parent = TYPE_OBJECT,
@@ -42,6 +46,13 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+void accel_init_interfaces(AccelClass *ac, const char *cpu_type)
+{
+#ifndef CONFIG_USER_ONLY
+ accel_init_ops_interfaces(ac);
+#endif /* !CONFIG_USER_ONLY */
+}
+
static void register_accel_types(void)
{
type_register_static(&accel_type);
diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c
index f89da8f9d1..2d15d3f2f4 100644
--- a/accel/accel-softmmu.c
+++ b/accel/accel-softmmu.c
@@ -26,9 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
#include "hw/boards.h"
-#include "sysemu/arch_init.h"
-#include "sysemu/sysemu.h"
-#include "qom/object.h"
+#include "sysemu/cpus.h"
+
+#include "accel-softmmu.h"
int accel_init_machine(AccelState *accel, MachineState *ms)
{
@@ -60,3 +60,40 @@ void accel_setup_post(MachineState *ms)
acc->setup_post(ms, accel);
}
}
+
+/* initialize the arch-independent accel operation interfaces */
+void accel_init_ops_interfaces(AccelClass *ac)
+{
+ const char *ac_name;
+ char *ops_name;
+ AccelOpsClass *ops;
+
+ ac_name = object_class_get_name(OBJECT_CLASS(ac));
+ g_assert(ac_name != NULL);
+
+ ops_name = g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name);
+ ops = ACCEL_OPS_CLASS(object_class_by_name(ops_name));
+ g_free(ops_name);
+
+ /*
+ * all accelerators need to define ops, providing at least a mandatory
+ * non-NULL create_vcpu_thread operation.
+ */
+ g_assert(ops != NULL);
+ if (ops->ops_init) {
+ ops->ops_init(ops);
+ }
+ cpus_register_accel(ops);
+}
+
+static const TypeInfo accel_ops_type_info = {
+ .name = TYPE_ACCEL_OPS,
+ .parent = TYPE_OBJECT,
+ .abstract = true,
+ .class_size = sizeof(AccelOpsClass),
+};
+static void accel_softmmu_register_types(void)
+{
+ type_register_static(&accel_ops_type_info);
+}
+type_init(accel_softmmu_register_types);
diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h
new file mode 100644
index 0000000000..2877b5c234
--- /dev/null
+++ b/accel/accel-softmmu.h
@@ -0,0 +1,15 @@
+/*
+ * QEMU System Emulation accel internal functions
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_SOFTMMU_H
+#define ACCEL_SOFTMMU_H
+
+void accel_init_ops_interfaces(AccelClass *ac);
+
+#endif /* ACCEL_SOFTMMU_H */
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 9ef5daf4c5..33156cc4c7 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -2251,8 +2251,6 @@ static int kvm_init(MachineState *ms)
ret = ram_block_discard_disable(true);
assert(!ret);
}
-
- cpus_register_accel(&kvm_cpus);
return 0;
err:
diff --git a/accel/kvm/kvm-cpus.c b/accel/kvm/kvm-cpus.c
index d809b1e74c..fc9dda46ae 100644
--- a/accel/kvm/kvm-cpus.c
+++ b/accel/kvm/kvm-cpus.c
@@ -74,11 +74,25 @@ static void kvm_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
-const CpusAccel kvm_cpus = {
- .create_vcpu_thread = kvm_start_vcpu_thread,
+static void kvm_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = kvm_cpu_synchronize_post_reset,
- .synchronize_post_init = kvm_cpu_synchronize_post_init,
- .synchronize_state = kvm_cpu_synchronize_state,
- .synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = kvm_start_vcpu_thread;
+ ops->synchronize_post_reset = kvm_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = kvm_cpu_synchronize_post_init;
+ ops->synchronize_state = kvm_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm;
};
+static const TypeInfo kvm_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = kvm_cpus_class_init,
+ .abstract = true,
+};
+static void kvm_cpus_register_types(void)
+{
+ type_register_static(&kvm_cpus_type_info);
+}
+type_init(kvm_cpus_register_types);
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h
index 3df732b816..bf0bd1bee4 100644
--- a/accel/kvm/kvm-cpus.h
+++ b/accel/kvm/kvm-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel kvm_cpus;
-
int kvm_init_vcpu(CPUState *cpu, Error **errp);
int kvm_cpu_exec(CPUState *cpu);
void kvm_destroy_vcpu(CPUState *cpu);
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index b4e731cb2b..68d86de30f 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -25,14 +25,8 @@
#include "qemu/main-loop.h"
#include "hw/core/cpu.h"
-const CpusAccel qtest_cpus = {
- .create_vcpu_thread = dummy_start_vcpu_thread,
- .get_virtual_clock = qtest_get_virtual_clock,
-};
-
static int qtest_init_accel(MachineState *ms)
{
- cpus_register_accel(&qtest_cpus);
return 0;
}
@@ -52,9 +46,26 @@ static const TypeInfo qtest_accel_type = {
.class_init = qtest_accel_class_init,
};
+static void qtest_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->create_vcpu_thread = dummy_start_vcpu_thread;
+ ops->get_virtual_clock = qtest_get_virtual_clock;
+};
+
+static const TypeInfo qtest_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("qtest"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = qtest_cpus_class_init,
+ .abstract = true,
+};
+
static void qtest_type_init(void)
{
type_register_static(&qtest_accel_type);
+ type_register_static(&qtest_cpus_type_info);
}
type_init(qtest_type_init);
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index dcbc6970da..2b86df9ba0 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -33,10 +33,6 @@
#include "qemu/accel.h"
#include "qapi/qapi-builtin-visit.h"
-#ifndef CONFIG_USER_ONLY
-#include "tcg-cpus.h"
-#endif /* CONFIG_USER_ONLY */
-
struct TCGState {
AccelState parent_obj;
@@ -112,16 +108,6 @@ static int tcg_init(MachineState *ms)
* Initialize TCG regions
*/
tcg_region_init();
-
-#ifndef CONFIG_USER_ONLY
- if (mttcg_enabled) {
- cpus_register_accel(&tcg_cpus_mttcg);
- } else if (icount_enabled()) {
- cpus_register_accel(&tcg_cpus_icount);
- } else {
- cpus_register_accel(&tcg_cpus_rr);
- }
-#endif /* CONFIG_USER_ONLY */
return 0;
}
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
index 9f45432275..5445b4d545 100644
--- a/accel/tcg/tcg-cpus-icount.c
+++ b/accel/tcg/tcg-cpus-icount.c
@@ -125,7 +125,7 @@ void icount_process_data(CPUState *cpu)
replay_mutex_unlock();
}
-static void icount_handle_interrupt(CPUState *cpu, int mask)
+void icount_handle_interrupt(CPUState *cpu, int mask)
{
int old_mask = cpu->interrupt_request;
@@ -136,12 +136,3 @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
cpu_abort(cpu, "Raised interrupt while not in I/O function");
}
}
-
-const CpusAccel tcg_cpus_icount = {
- .create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = rr_kick_vcpu_thread,
-
- .handle_interrupt = icount_handle_interrupt,
- .get_virtual_clock = icount_get,
- .get_elapsed_ticks = icount_get,
-};
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
index b695939dfa..d884aa2aaa 100644
--- a/accel/tcg/tcg-cpus-icount.h
+++ b/accel/tcg/tcg-cpus-icount.h
@@ -14,4 +14,6 @@ void icount_handle_deadline(void);
void icount_prepare_for_run(CPUState *cpu);
void icount_process_data(CPUState *cpu);
+void icount_handle_interrupt(CPUState *cpu, int mask);
+
#endif /* TCG_CPUS_ICOUNT_H */
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
index 9c3767d260..dabf5ed42e 100644
--- a/accel/tcg/tcg-cpus-mttcg.c
+++ b/accel/tcg/tcg-cpus-mttcg.c
@@ -33,6 +33,7 @@
#include "hw/boards.h"
#include "tcg-cpus.h"
+#include "tcg-cpus-mttcg.h"
/*
* In the multi-threaded case each vCPU has its own thread. The TLS
@@ -103,12 +104,12 @@ static void *mttcg_cpu_thread_fn(void *arg)
return NULL;
}
-static void mttcg_kick_vcpu_thread(CPUState *cpu)
+void mttcg_kick_vcpu_thread(CPUState *cpu)
{
cpu_exit(cpu);
}
-static void mttcg_start_vcpu_thread(CPUState *cpu)
+void mttcg_start_vcpu_thread(CPUState *cpu)
{
char thread_name[VCPU_THREAD_NAME_SIZE];
@@ -131,10 +132,3 @@ static void mttcg_start_vcpu_thread(CPUState *cpu)
cpu->hThread = qemu_thread_get_handle(cpu->thread);
#endif
}
-
-const CpusAccel tcg_cpus_mttcg = {
- .create_vcpu_thread = mttcg_start_vcpu_thread,
- .kick_vcpu_thread = mttcg_kick_vcpu_thread,
-
- .handle_interrupt = tcg_cpus_handle_interrupt,
-};
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
new file mode 100644
index 0000000000..0af91dd3b3
--- /dev/null
+++ b/accel/tcg/tcg-cpus-mttcg.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU TCG Multi Threaded vCPUs implementation
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPUS_MTTCG_H
+#define TCG_CPUS_MTTCG_H
+
+/* kick MTTCG vCPU thread */
+void mttcg_kick_vcpu_thread(CPUState *cpu);
+
+/* start an mttcg vCPU thread */
+void mttcg_start_vcpu_thread(CPUState *cpu);
+
+#endif /* TCG_CPUS_MTTCG_H */
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
index 0181d2e4eb..802c57bb60 100644
--- a/accel/tcg/tcg-cpus-rr.c
+++ b/accel/tcg/tcg-cpus-rr.c
@@ -296,10 +296,3 @@ void rr_start_vcpu_thread(CPUState *cpu)
cpu->created = true;
}
}
-
-const CpusAccel tcg_cpus_rr = {
- .create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = rr_kick_vcpu_thread,
-
- .handle_interrupt = tcg_cpus_handle_interrupt,
-};
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
index e335f9f155..38a58ab271 100644
--- a/accel/tcg/tcg-cpus.c
+++ b/accel/tcg/tcg-cpus.c
@@ -35,6 +35,9 @@
#include "hw/boards.h"
#include "tcg-cpus.h"
+#include "tcg-cpus-mttcg.h"
+#include "tcg-cpus-rr.h"
+#include "tcg-cpus-icount.h"
/* common functionality among all TCG variants */
@@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
}
}
+
+static void tcg_cpus_ops_init(AccelOpsClass *ops)
+{
+ if (qemu_tcg_mttcg_enabled()) {
+ ops->create_vcpu_thread = mttcg_start_vcpu_thread;
+ ops->kick_vcpu_thread = mttcg_kick_vcpu_thread;
+ ops->handle_interrupt = tcg_cpus_handle_interrupt;
+
+ } else if (icount_enabled()) {
+ ops->create_vcpu_thread = rr_start_vcpu_thread;
+ ops->kick_vcpu_thread = rr_kick_vcpu_thread;
+ ops->handle_interrupt = icount_handle_interrupt;
+ ops->get_virtual_clock = icount_get;
+ ops->get_elapsed_ticks = icount_get;
+
+ } else {
+ ops->create_vcpu_thread = rr_start_vcpu_thread;
+ ops->kick_vcpu_thread = rr_kick_vcpu_thread;
+ ops->handle_interrupt = tcg_cpus_handle_interrupt;
+ }
+}
+
+static void tcg_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->ops_init = tcg_cpus_ops_init;
+};
+static const TypeInfo tcg_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = tcg_cpus_class_init,
+ .abstract = true,
+};
+static void tcg_cpus_register_types(void)
+{
+ type_register_static(&tcg_cpus_type_info);
+}
+type_init(tcg_cpus_register_types);
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
index d6893a32f8..923cbace12 100644
--- a/accel/tcg/tcg-cpus.h
+++ b/accel/tcg/tcg-cpus.h
@@ -14,10 +14,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel tcg_cpus_mttcg;
-extern const CpusAccel tcg_cpus_icount;
-extern const CpusAccel tcg_cpus_rr;
-
void tcg_cpus_destroy(CPUState *cpu);
int tcg_cpus_exec(CPUState *cpu);
void tcg_cpus_handle_interrupt(CPUState *cpu, int mask);
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 594aaf6b49..cd5aa2b96e 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -154,10 +154,6 @@ static void xen_setup_post(MachineState *ms, AccelState *accel)
}
}
-const CpusAccel xen_cpus = {
- .create_vcpu_thread = dummy_start_vcpu_thread,
-};
-
static int xen_init(MachineState *ms)
{
MachineClass *mc = MACHINE_GET_CLASS(ms);
@@ -185,9 +181,6 @@ static int xen_init(MachineState *ms)
* opt out of system RAM being allocated by generic code
*/
mc->default_ram_id = NULL;
-
- cpus_register_accel(&xen_cpus);
-
return 0;
}
@@ -222,9 +215,24 @@ static const TypeInfo xen_accel_type = {
.class_init = xen_accel_class_init,
};
+static void xen_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->create_vcpu_thread = dummy_start_vcpu_thread;
+};
+static const TypeInfo xen_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("xen"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = xen_cpus_class_init,
+ .abstract = true,
+};
+
static void xen_type_init(void)
{
type_register_static(&xen_accel_type);
+ type_register_static(&xen_cpus_type_info);
}
type_init(xen_type_init);
diff --git a/bsd-user/main.c b/bsd-user/main.c
index ec1f9d80a4..25a757c746 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -908,13 +908,14 @@ int main(int argc, char **argv)
#endif
}
+ cpu_type = parse_cpu_option(cpu_model);
/* init tcg before creating CPUs and to get qemu_host_page_size */
{
AccelClass *ac = ACCEL_GET_CLASS(current_accel());
ac->init_machine(NULL);
+ accel_init_interfaces(ac, cpu_type);
}
- cpu_type = parse_cpu_option(cpu_model);
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index fac4a18703..68a57e040f 100644
--- a/include/qemu/accel.h
+++ b/include/qemu/accel.h
@@ -69,6 +69,8 @@ typedef struct AccelClass {
AccelClass *accel_find(const char *opt_name);
AccelState *current_accel(void);
+void accel_init_interfaces(AccelClass *ac, const char *cpu_type);
+
#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h
new file mode 100644
index 0000000000..6102d2f80d
--- /dev/null
+++ b/include/sysemu/accel-ops.h
@@ -0,0 +1,45 @@
+/*
+ * Accelerator OPS, used for cpus.c module
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_OPS_H
+#define ACCEL_OPS_H
+
+#include "qom/object.h"
+
+#define ACCEL_OPS_SUFFIX "-ops"
+#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX
+#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS)
+
+typedef struct AccelOpsClass AccelOpsClass;
+DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS)
+
+/* cpus.c operations interface */
+struct AccelOpsClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ /* initialization function called when accel is chosen */
+ void (*ops_init)(AccelOpsClass *ops);
+
+ void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */
+ void (*kick_vcpu_thread)(CPUState *cpu);
+
+ void (*synchronize_post_reset)(CPUState *cpu);
+ void (*synchronize_post_init)(CPUState *cpu);
+ void (*synchronize_state)(CPUState *cpu);
+ void (*synchronize_pre_loadvm)(CPUState *cpu);
+
+ void (*handle_interrupt)(CPUState *cpu, int mask);
+
+ int64_t (*get_virtual_clock)(void);
+ int64_t (*get_elapsed_ticks)(void);
+};
+
+#endif /* ACCEL_OPS_H */
diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h
index e8156728c6..2cd74392e0 100644
--- a/include/sysemu/cpus.h
+++ b/include/sysemu/cpus.h
@@ -2,30 +2,14 @@
#define QEMU_CPUS_H
#include "qemu/timer.h"
+#include "sysemu/accel-ops.h"
-/* cpus.c */
+/* register accel-specific operations */
+void cpus_register_accel(const AccelOpsClass *i);
-/* CPU execution threads */
+/* accel/dummy-cpus.c */
-typedef struct CpusAccel {
- void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY */
- void (*kick_vcpu_thread)(CPUState *cpu);
-
- void (*synchronize_post_reset)(CPUState *cpu);
- void (*synchronize_post_init)(CPUState *cpu);
- void (*synchronize_state)(CPUState *cpu);
- void (*synchronize_pre_loadvm)(CPUState *cpu);
-
- void (*handle_interrupt)(CPUState *cpu, int mask);
-
- int64_t (*get_virtual_clock)(void);
- int64_t (*get_elapsed_ticks)(void);
-} CpusAccel;
-
-/* register accel-specific cpus interface implementation */
-void cpus_register_accel(const CpusAccel *i);
-
-/* Create a dummy vcpu for CpusAccel->create_vcpu_thread */
+/* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */
void dummy_start_vcpu_thread(CPUState *);
/* interface available for cpus accelerator threads */
diff --git a/linux-user/main.c b/linux-user/main.c
index 1825d2b835..54e59fce3a 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -708,6 +708,7 @@ int main(int argc, char **argv, char **envp)
AccelClass *ac = ACCEL_GET_CLASS(current_accel());
ac->init_machine(NULL);
+ accel_init_interfaces(ac, cpu_type);
}
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
diff --git a/softmmu/cpus.c b/softmmu/cpus.c
index e46ac68ad0..659617e7ef 100644
--- a/softmmu/cpus.c
+++ b/softmmu/cpus.c
@@ -127,7 +127,7 @@ void hw_error(const char *fmt, ...)
/*
* The chosen accelerator is supposed to register this.
*/
-static const CpusAccel *cpus_accel;
+static const AccelOpsClass *cpus_accel;
void cpu_synchronize_all_states(void)
{
@@ -593,11 +593,11 @@ void cpu_remove_sync(CPUState *cpu)
qemu_mutex_lock_iothread();
}
-void cpus_register_accel(const CpusAccel *ca)
+void cpus_register_accel(const AccelOpsClass *ops)
{
- assert(ca != NULL);
- assert(ca->create_vcpu_thread != NULL); /* mandatory */
- cpus_accel = ca;
+ assert(ops != NULL);
+ assert(ops->create_vcpu_thread != NULL); /* mandatory */
+ cpus_accel = ops;
}
void qemu_init_vcpu(CPUState *cpu)
@@ -617,7 +617,7 @@ void qemu_init_vcpu(CPUState *cpu)
cpu_address_space_init(cpu, 0, "cpu-memory", cpu->memory);
}
- /* accelerators all implement the CpusAccel interface */
+ /* accelerators all implement the AccelOpsClass */
g_assert(cpus_accel != NULL && cpus_accel->create_vcpu_thread != NULL);
cpus_accel->create_vcpu_thread(cpu);
diff --git a/softmmu/vl.c b/softmmu/vl.c
index bc20c526d2..8d65058ef1 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -2558,7 +2558,7 @@ static bool object_create_initial(const char *type, QemuOpts *opts)
}
/* Memory allocation by backends needs to be done
- * after configure_accelerator() (due to the tcg_enabled()
+ * after do_configure_accelerator() (due to the tcg_enabled()
* checks at memory_region_init_*()).
*
* Also, allocation of large amounts of memory may delay
@@ -4186,7 +4186,7 @@ void qemu_init(int argc, char **argv, char **envp)
*
* Machine compat properties: object_set_machine_compat_props().
* Accelerator compat props: object_set_accelerator_compat_props(),
- * called from configure_accelerator().
+ * called from do_configure_accelerator().
*/
if (!qtest_enabled() && machine_class->deprecation_reason) {
@@ -4322,6 +4322,10 @@ void qemu_init(int argc, char **argv, char **envp)
current_machine->cpu_type = parse_cpu_option(cpu_option);
}
+ /* cpu has been chosen, initialize the accel interfaces */
+ accel_init_interfaces(ACCEL_GET_CLASS(current_machine->accelerator),
+ current_machine->cpu_type);
+
if (current_machine->ram_memdev_id) {
Object *backend;
ram_addr_t backend_size;
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index d7f4bb44a7..ec3c426223 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms)
!ret ? "working" : "not working",
!ret ? "fast virt" : "emulation");
}
- if (ret == 0) {
- cpus_register_accel(&hax_cpus);
- }
return ret;
}
diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-cpus.c
index f72c85bd49..2f8424388d 100644
--- a/target/i386/hax/hax-cpus.c
+++ b/target/i386/hax/hax-cpus.c
@@ -74,12 +74,27 @@ static void hax_start_vcpu_thread(CPUState *cpu)
#endif
}
-const CpusAccel hax_cpus = {
- .create_vcpu_thread = hax_start_vcpu_thread,
- .kick_vcpu_thread = hax_kick_vcpu_thread,
+static void hax_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = hax_cpu_synchronize_post_reset,
- .synchronize_post_init = hax_cpu_synchronize_post_init,
- .synchronize_state = hax_cpu_synchronize_state,
- .synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = hax_start_vcpu_thread;
+ ops->kick_vcpu_thread = hax_kick_vcpu_thread;
+
+ ops->synchronize_post_reset = hax_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = hax_cpu_synchronize_post_init;
+ ops->synchronize_state = hax_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm;
+};
+static const TypeInfo hax_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("hax"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = hax_cpus_class_init,
+ .abstract = true,
};
+static void hax_cpus_register_types(void)
+{
+ type_register_static(&hax_cpus_type_info);
+}
+type_init(hax_cpus_register_types);
diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-cpus.h
index ee8ab7a631..c7698519cd 100644
--- a/target/i386/hax/hax-cpus.h
+++ b/target/i386/hax/hax-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel hax_cpus;
-
#include "hax-interface.h"
#include "hax-i386.h"
diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-cpus.c
index 817b3d7452..dd022a84c4 100644
--- a/target/i386/hvf/hvf-cpus.c
+++ b/target/i386/hvf/hvf-cpus.c
@@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
-const CpusAccel hvf_cpus = {
- .create_vcpu_thread = hvf_start_vcpu_thread,
+static void hvf_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = hvf_cpu_synchronize_post_reset,
- .synchronize_post_init = hvf_cpu_synchronize_post_init,
- .synchronize_state = hvf_cpu_synchronize_state,
- .synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = hvf_start_vcpu_thread;
+
+ ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = hvf_cpu_synchronize_post_init;
+ ops->synchronize_state = hvf_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm;
+};
+static const TypeInfo hvf_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("hvf"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = hvf_cpus_class_init,
+ .abstract = true,
};
+static void hvf_cpus_register_types(void)
+{
+ type_register_static(&hvf_cpus_type_info);
+}
+type_init(hvf_cpus_register_types);
diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-cpus.h
index ced31b82c0..8f992da168 100644
--- a/target/i386/hvf/hvf-cpus.h
+++ b/target/i386/hvf/hvf-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel hvf_cpus;
-
int hvf_init_vcpu(CPUState *);
int hvf_vcpu_exec(CPUState *);
void hvf_cpu_synchronize_state(CPUState *);
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ffc9efa40f..bd94bb5243 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms)
hvf_state = s;
memory_listener_register(&hvf_memory_listener, &address_space_memory);
- cpus_register_accel(&hvf_cpus);
return 0;
}
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index ee6b606194..90adae9af7 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -1642,8 +1642,6 @@ static int whpx_accel_init(MachineState *ms)
whpx_memory_init();
- cpus_register_accel(&whpx_cpus);
-
printf("Windows Hypervisor Platform accelerator is operational\n");
return 0;
diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c
index d9bd5a2d36..8e82974de7 100644
--- a/target/i386/whpx/whpx-cpus.c
+++ b/target/i386/whpx/whpx-cpus.c
@@ -85,12 +85,27 @@ static void whpx_kick_vcpu_thread(CPUState *cpu)
}
}
-const CpusAccel whpx_cpus = {
- .create_vcpu_thread = whpx_start_vcpu_thread,
- .kick_vcpu_thread = whpx_kick_vcpu_thread,
+static void whpx_cpus_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = whpx_cpu_synchronize_post_reset,
- .synchronize_post_init = whpx_cpu_synchronize_post_init,
- .synchronize_state = whpx_cpu_synchronize_state,
- .synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = whpx_start_vcpu_thread;
+ ops->kick_vcpu_thread = whpx_kick_vcpu_thread;
+
+ ops->synchronize_post_reset = whpx_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = whpx_cpu_synchronize_post_init;
+ ops->synchronize_state = whpx_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm;
+};
+static const TypeInfo whpx_cpus_type_info = {
+ .name = ACCEL_OPS_NAME("whpx"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = whpx_cpus_class_init,
+ .abstract = true,
};
+static void whpx_cpus_register_types(void)
+{
+ type_register_static(&whpx_cpus_type_info);
+}
+type_init(whpx_cpus_register_types);
diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h
index bdb367d1d0..2dee6d61ea 100644
--- a/target/i386/whpx/whpx-cpus.h
+++ b/target/i386/whpx/whpx-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel whpx_cpus;
-
int whpx_init_vcpu(CPUState *cpu);
int whpx_vcpu_exec(CPUState *cpu);
void whpx_destroy_vcpu(CPUState *cpu);
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (8 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 09/11] accel: replace struct CpusAccel with AccelOpsClass Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-27 6:21 ` Paolo Bonzini
2020-11-27 17:06 ` Eduardo Habkost
2020-11-26 22:32 ` [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
10 siblings, 2 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
add a new optional interface to CPUClass,
which allows accelerators to extend the CPUClass
with additional accelerator-specific initializations.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 1 +
accel/accel-common.c | 43 +++++++++++++++++++++++++++++++++++++
include/hw/core/accel-cpu.h | 28 ++++++++++++++++++++++++
include/hw/core/cpu.h | 4 ++++
4 files changed, 76 insertions(+)
create mode 100644 include/hw/core/accel-cpu.h
diff --git a/MAINTAINERS b/MAINTAINERS
index df64a0d190..b99526e491 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -435,6 +435,7 @@ R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
F: include/sysemu/accel-ops.h
+F: include/hw/core/accel-cpu.h
F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/accel-common.c b/accel/accel-common.c
index 3910b7dbe0..06afee982e 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#include "cpu.h"
+#include "hw/core/accel-cpu.h"
+
#ifndef CONFIG_USER_ONLY
#include "accel-softmmu.h"
#endif /* !CONFIG_USER_ONLY */
@@ -46,16 +49,56 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
+{
+ CPUClass *cc = CPU_CLASS(klass);
+ AccelCPUClass *accel_cpu_interface = opaque;
+
+ cc->accel_cpu_interface = accel_cpu_interface;
+ if (accel_cpu_interface->cpu_class_init) {
+ accel_cpu_interface->cpu_class_init(cc);
+ }
+}
+
+/* initialize the arch-specific accel CpuClass interfaces */
+static void accel_init_cpu_interfaces(AccelClass *ac, const char *cpu_type)
+{
+ const char *ac_name; /* AccelClass name */
+ char *acc_name; /* AccelCPUClass name */
+ ObjectClass *acc; /* AccelCPUClass */
+
+ ac_name = object_class_get_name(OBJECT_CLASS(ac));
+ g_assert(ac_name != NULL);
+
+ acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
+ acc = object_class_by_name(acc_name);
+ g_free(acc_name);
+
+ if (acc) {
+ object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
+ }
+}
+
void accel_init_interfaces(AccelClass *ac, const char *cpu_type)
{
#ifndef CONFIG_USER_ONLY
accel_init_ops_interfaces(ac);
#endif /* !CONFIG_USER_ONLY */
+
+ accel_init_cpu_interfaces(ac, cpu_type);
}
+static const TypeInfo accel_cpu_type = {
+ .name = TYPE_ACCEL_CPU,
+ .parent = TYPE_OBJECT,
+ .abstract = true,
+ .class_size = sizeof(AccelCPUClass),
+};
+
static void register_accel_types(void)
{
type_register_static(&accel_type);
+ type_register_static(&accel_cpu_type);
}
type_init(register_accel_types);
diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
new file mode 100644
index 0000000000..380e1c7436
--- /dev/null
+++ b/include/hw/core/accel-cpu.h
@@ -0,0 +1,28 @@
+/*
+ * Accelerator interface, specializes CPUClass
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_CPU_H
+#define ACCEL_CPU_H
+
+struct AccelCPUClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ void (*cpu_class_init)(CPUClass *cc);
+ void (*cpu_instance_init)(CPUState *cpu);
+ void (*cpu_realizefn)(CPUState *cpu, Error **errp);
+};
+
+#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
+#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
+typedef struct AccelCPUClass AccelCPUClass;
+DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
+
+#endif /* ACCEL_CPU_H */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3d92c967ff..75eb1d8199 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,6 +76,8 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
+struct AccelCPUClass;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -227,6 +229,8 @@ struct CPUClass {
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+
+ struct AccelCPUClass *accel_cpu_interface;
};
/*
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
` (9 preceding siblings ...)
2020-11-26 22:32 ` [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
@ 2020-11-26 22:32 ` Claudio Fontana
2020-11-27 17:41 ` Eduardo Habkost
10 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-26 22:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Claudio Fontana, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota, Colin Xu
i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.c cpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/cpu.c KVM x86 AccelCPUClass
hvf/cpu.c HVF x86 AccelCPUClass
tcg/cpu.c TCG x86 AccelCPUClass
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
MAINTAINERS | 2 +-
hw/i386/pc_piix.c | 1 +
target/i386/cpu.c | 386 ++++--------------------------------
target/i386/cpu.h | 20 +-
target/i386/host-cpu.c | 198 ++++++++++++++++++
target/i386/host-cpu.h | 19 ++
target/i386/hvf/cpu.c | 65 ++++++
target/i386/hvf/meson.build | 1 +
target/i386/kvm/cpu.c | 148 ++++++++++++++
target/i386/kvm/kvm-cpu.h | 41 ++++
target/i386/kvm/kvm.c | 3 +-
target/i386/kvm/meson.build | 7 +-
target/i386/meson.build | 8 +-
target/i386/tcg-cpu.c | 71 -------
target/i386/tcg-cpu.h | 15 --
target/i386/tcg/cpu.c | 173 ++++++++++++++++
target/i386/tcg/meson.build | 3 +-
17 files changed, 711 insertions(+), 450 deletions(-)
create mode 100644 target/i386/host-cpu.c
create mode 100644 target/i386/host-cpu.h
create mode 100644 target/i386/hvf/cpu.c
create mode 100644 target/i386/kvm/cpu.c
create mode 100644 target/i386/kvm/kvm-cpu.h
delete mode 100644 target/i386/tcg-cpu.c
delete mode 100644 target/i386/tcg-cpu.h
create mode 100644 target/i386/tcg/cpu.c
diff --git a/MAINTAINERS b/MAINTAINERS
index b99526e491..c7fff31888 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -336,7 +336,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Richard Henderson <richard.henderson@linaro.org>
M: Eduardo Habkost <ehabkost@redhat.com>
S: Maintained
-F: target/i386/
+F: target/i386/tcg/
F: tests/tcg/i386/
F: tests/tcg/x86_64/
F: hw/i386/
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 13d1628f13..d3f013f3a1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -64,6 +64,7 @@
#include "hw/hyperv/vmbus-bridge.h"
#include "hw/mem/nvdimm.h"
#include "hw/i386/acpi-build.h"
+#include "kvm/kvm-cpu.h"
#define MAX_IDE_BUS 2
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3462d0143f..27fba3b003 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -22,37 +22,24 @@
#include "qemu/cutils.h"
#include "qemu/bitops.h"
#include "qemu/qemu-print.h"
-
#include "cpu.h"
-#include "tcg-cpu.h"
#include "helper-tcg.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
#include "sysemu/hvf.h"
-#include "sysemu/cpus.h"
+#include "hw/core/accel-cpu.h"
#include "sysemu/xen.h"
#include "kvm/kvm_i386.h"
#include "sev_i386.h"
-
-#include "qemu/error-report.h"
#include "qemu/module.h"
-#include "qemu/option.h"
-#include "qemu/config-file.h"
-#include "qapi/error.h"
#include "qapi/qapi-visit-machine.h"
#include "qapi/qapi-visit-run-state.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qerror.h"
-#include "qapi/visitor.h"
#include "qom/qom-qobject.h"
-#include "sysemu/arch_init.h"
#include "qapi/qapi-commands-machine-target.h"
-
#include "standard-headers/asm-x86/kvm_para.h"
-
-#include "sysemu/sysemu.h"
-#include "sysemu/tcg.h"
#include "hw/qdev-properties.h"
#include "hw/i386/topology.h"
#ifndef CONFIG_USER_ONLY
@@ -594,8 +581,8 @@ static CPUCacheInfo legacy_l3_cache = {
#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
-static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
- uint32_t vendor2, uint32_t vendor3)
+void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
+ uint32_t vendor2, uint32_t vendor3)
{
int i;
for (i = 0; i < 4; i++) {
@@ -1563,25 +1550,6 @@ void host_cpuid(uint32_t function, uint32_t count,
*edx = vec[3];
}
-void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
-{
- uint32_t eax, ebx, ecx, edx;
-
- host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
-
- host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
- if (family) {
- *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
- }
- if (model) {
- *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
- }
- if (stepping) {
- *stepping = eax & 0x0F;
- }
-}
-
/* CPU class name definitions: */
/* Return type name for a given CPU model name
@@ -1606,10 +1574,6 @@ static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
}
-typedef struct PropValue {
- const char *prop, *value;
-} PropValue;
-
typedef struct X86CPUVersionDefinition {
X86CPUVersion version;
const char *alias;
@@ -4106,31 +4070,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
};
-/* KVM-specific features that are automatically added/removed
- * from all CPU models when KVM is enabled.
- */
-static PropValue kvm_default_props[] = {
- { "kvmclock", "on" },
- { "kvm-nopiodelay", "on" },
- { "kvm-asyncpf", "on" },
- { "kvm-steal-time", "on" },
- { "kvm-pv-eoi", "on" },
- { "kvmclock-stable-bit", "on" },
- { "x2apic", "on" },
- { "acpi", "off" },
- { "monitor", "off" },
- { "svm", "off" },
- { NULL, NULL },
-};
-
-/* TCG-specific defaults that override all CPU models when using TCG
- */
-static PropValue tcg_default_props[] = {
- { "vme", "off" },
- { NULL, NULL },
-};
-
-
/*
* We resolve CPU model aliases using -v1 when using "-machine
* none", but this is just for compatibility while libvirt isn't
@@ -4172,61 +4111,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
return v;
}
-void x86_cpu_change_kvm_default(const char *prop, const char *value)
-{
- PropValue *pv;
- for (pv = kvm_default_props; pv->prop; pv++) {
- if (!strcmp(pv->prop, prop)) {
- pv->value = value;
- break;
- }
- }
-
- /* It is valid to call this function only for properties that
- * are already present in the kvm_default_props table.
- */
- assert(pv->prop);
-}
-
-static bool lmce_supported(void)
-{
- uint64_t mce_cap = 0;
-
-#ifdef CONFIG_KVM
- if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
- return false;
- }
-#endif
-
- return !!(mce_cap & MCG_LMCE_P);
-}
-
-#define CPUID_MODEL_ID_SZ 48
-
-/**
- * cpu_x86_fill_model_id:
- * Get CPUID model ID string from host CPU.
- *
- * @str should have at least CPUID_MODEL_ID_SZ bytes
- *
- * The function does NOT add a null terminator to the string
- * automatically.
- */
-static int cpu_x86_fill_model_id(char *str)
-{
- uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
- int i;
-
- for (i = 0; i < 3; i++) {
- host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
- memcpy(str + i * 16 + 0, &eax, 4);
- memcpy(str + i * 16 + 4, &ebx, 4);
- memcpy(str + i * 16 + 8, &ecx, 4);
- memcpy(str + i * 16 + 12, &edx, 4);
- }
- return 0;
-}
-
static Property max_x86_cpu_properties[] = {
DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
@@ -4249,61 +4133,25 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
static void max_x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
- CPUX86State *env = &cpu->env;
- KVMState *s = kvm_state;
/* We can't fill the features array here because we don't know yet if
* "migratable" is true or false.
*/
cpu->max_features = true;
-
- if (accel_uses_host_cpuid()) {
- char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
- char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
- int family, model, stepping;
-
- host_vendor_fms(vendor, &family, &model, &stepping);
- cpu_x86_fill_model_id(model_id);
-
- object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
- object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
- object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
- object_property_set_int(OBJECT(cpu), "stepping", stepping,
- &error_abort);
- object_property_set_str(OBJECT(cpu), "model-id", model_id,
- &error_abort);
-
- if (kvm_enabled()) {
- env->cpuid_min_level =
- kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
- env->cpuid_min_xlevel =
- kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
- env->cpuid_min_xlevel2 =
- kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
- } else {
- env->cpuid_min_level =
- hvf_get_supported_cpuid(0x0, 0, R_EAX);
- env->cpuid_min_xlevel =
- hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
- env->cpuid_min_xlevel2 =
- hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
- }
-
- if (lmce_supported()) {
- object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
- }
- } else {
- object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
- &error_abort);
- object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
- object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
- object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
- object_property_set_str(OBJECT(cpu), "model-id",
- "QEMU TCG CPU version " QEMU_HW_VERSION,
- &error_abort);
- }
-
object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
+
+ /*
+ * these defaults are used for TCG and all other accelerators
+ * besides KVM and HVF, which overwrite these values
+ */
+ object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
+ &error_abort);
+ object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
+ object_property_set_str(OBJECT(cpu), "model-id",
+ "QEMU TCG CPU version " QEMU_HW_VERSION,
+ &error_abort);
}
static const TypeInfo max_x86_cpu_type_info = {
@@ -4313,31 +4161,6 @@ static const TypeInfo max_x86_cpu_type_info = {
.class_init = max_x86_cpu_class_init,
};
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
-{
- X86CPUClass *xcc = X86_CPU_CLASS(oc);
-
- xcc->host_cpuid_required = true;
- xcc->ordering = 8;
-
-#if defined(CONFIG_KVM)
- xcc->model_description =
- "KVM processor with all supported host features ";
-#elif defined(CONFIG_HVF)
- xcc->model_description =
- "HVF processor with all supported host features ";
-#endif
-}
-
-static const TypeInfo host_x86_cpu_type_info = {
- .name = X86_CPU_TYPE_NAME("host"),
- .parent = X86_CPU_TYPE_NAME("max"),
- .class_init = host_x86_cpu_class_init,
-};
-
-#endif
-
static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
{
assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
@@ -5063,7 +4886,7 @@ static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
return r;
}
-static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
+void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
{
PropValue *pv;
for (pv = props; pv->prop; pv++) {
@@ -5110,8 +4933,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
{
X86CPUDefinition *def = model->cpudef;
CPUX86State *env = &cpu->env;
- const char *vendor;
- char host_vendor[CPUID_VENDOR_SZ + 1];
FeatureWord w;
/*NOTE: any property set by this function should be returned by
@@ -5138,18 +4959,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
/* legacy-cache defaults to 'off' if CPU model provides cache info */
cpu->legacy_cache = !def->cache_info;
- /* Special cases not set in the X86CPUDefinition structs: */
- /* TODO: in-kernel irqchip for hvf */
- if (kvm_enabled()) {
- if (!kvm_irqchip_in_kernel()) {
- x86_cpu_change_kvm_default("x2apic", "off");
- }
-
- x86_cpu_apply_props(cpu, kvm_default_props);
- } else if (tcg_enabled()) {
- x86_cpu_apply_props(cpu, tcg_default_props);
- }
-
env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
/* sysenter isn't supported in compatibility mode on AMD,
@@ -5159,15 +4968,12 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
* KVM's sysenter/syscall emulation in compatibility mode and
* when doing cross vendor migration
*/
- vendor = def->vendor;
- if (accel_uses_host_cpuid()) {
- uint32_t ebx = 0, ecx = 0, edx = 0;
- host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
- x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
- vendor = host_vendor;
- }
- object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+ /*
+ * vendor property is set here but then overloaded with the
+ * host cpu vendor for KVM and HVF.
+ */
+ object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
x86_cpu_apply_version_props(cpu, model);
@@ -6192,53 +5998,12 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
apic_mmio_map_once = true;
}
}
-
-static void x86_cpu_machine_done(Notifier *n, void *unused)
-{
- X86CPU *cpu = container_of(n, X86CPU, machine_done);
- MemoryRegion *smram =
- (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
-
- if (smram) {
- cpu->smram = g_new(MemoryRegion, 1);
- memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
- smram, 0, 4 * GiB);
- memory_region_set_enabled(cpu->smram, true);
- memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
- }
-}
#else
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
}
#endif
-/* Note: Only safe for use on x86(-64) hosts */
-static uint32_t x86_host_phys_bits(void)
-{
- uint32_t eax;
- uint32_t host_phys_bits;
-
- host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
- if (eax >= 0x80000008) {
- host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
- /* Note: According to AMD doc 25481 rev 2.34 they have a field
- * at 23:16 that can specify a maximum physical address bits for
- * the guest that can override this value; but I've not seen
- * anything with that set.
- */
- host_phys_bits = eax & 0xff;
- } else {
- /* It's an odd 64 bit machine that doesn't have the leaf for
- * physical address bits; fall back to 36 that's most older
- * Intel.
- */
- host_phys_bits = 36;
- }
-
- return host_phys_bits;
-}
-
static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
{
if (*min < value) {
@@ -6515,33 +6280,22 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ CPUClass *cc = CPU_GET_CLASS(cs);
X86CPU *cpu = X86_CPU(dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = &cpu->env;
Error *local_err = NULL;
static bool ht_warned;
- if (xcc->host_cpuid_required) {
- if (!accel_uses_host_cpuid()) {
- g_autofree char *name = x86_cpu_class_get_model_name(xcc);
- error_setg(&local_err, "CPU model '%s' requires KVM", name);
- goto out;
- }
+ /* The accelerator realizefn needs to be called first. */
+ if (cc->accel_cpu_interface) {
+ cc->accel_cpu_interface->cpu_realizefn(cs, errp);
}
- if (cpu->max_features && accel_uses_host_cpuid()) {
- if (enable_cpu_pm) {
- host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
- &cpu->mwait.ecx, &cpu->mwait.edx);
- env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
- if (kvm_enabled() && kvm_has_waitpkg()) {
- env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
- }
- }
- if (kvm_enabled() && cpu->ucode_rev == 0) {
- cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
- MSR_IA32_UCODE_REV);
- }
+ if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
+ g_autofree char *name = x86_cpu_class_get_model_name(xcc);
+ error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
+ goto out;
}
if (cpu->ucode_rev == 0) {
@@ -6593,39 +6347,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
* consumer AMD devices but nothing else.
*/
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
- if (accel_uses_host_cpuid()) {
- uint32_t host_phys_bits = x86_host_phys_bits();
- static bool warned;
-
- /* Print a warning if the user set it to a value that's not the
- * host value.
- */
- if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
- !warned) {
- warn_report("Host physical bits (%u)"
- " does not match phys-bits property (%u)",
- host_phys_bits, cpu->phys_bits);
- warned = true;
- }
-
- if (cpu->host_phys_bits) {
- /* The user asked for us to use the host physical bits */
- cpu->phys_bits = host_phys_bits;
- if (cpu->host_phys_bits_limit &&
- cpu->phys_bits > cpu->host_phys_bits_limit) {
- cpu->phys_bits = cpu->host_phys_bits_limit;
- }
- }
-
- if (cpu->phys_bits &&
- (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
- cpu->phys_bits < 32)) {
- error_setg(errp, "phys-bits should be between 32 and %u "
- " (but is %u)",
- TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
- return;
- }
- } else {
+ if (!accel_uses_host_cpuid()) {
if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
error_setg(errp, "TCG only supports phys-bits=%u",
TCG_PHYS_ADDR_BITS);
@@ -6633,8 +6355,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
}
/* 0 means it was not explicitly set by the user (or by machine
- * compat_props or by the host code above). In this case, the default
- * is the value used by TCG (40).
+ * compat_props or by the host code in host-cpu.c).
+ * In this case, the default is the value used by TCG (40).
*/
if (cpu->phys_bits == 0) {
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
@@ -6704,33 +6426,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
mce_init(cpu);
-#ifndef CONFIG_USER_ONLY
- if (tcg_enabled()) {
- cpu->cpu_as_mem = g_new(MemoryRegion, 1);
- cpu->cpu_as_root = g_new(MemoryRegion, 1);
-
- /* Outer container... */
- memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
- memory_region_set_enabled(cpu->cpu_as_root, true);
-
- /* ... with two regions inside: normal system memory with low
- * priority, and...
- */
- memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
- get_system_memory(), 0, ~0ull);
- memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
- memory_region_set_enabled(cpu->cpu_as_mem, true);
-
- cs->num_ases = 2;
- cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
- cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
-
- /* ... SMRAM with higher priority, linked from /machine/smram. */
- cpu->machine_done.notify = x86_cpu_machine_done;
- qemu_add_machine_init_done_notifier(&cpu->machine_done);
- }
-#endif
-
qemu_init_vcpu(cs);
/*
@@ -6936,6 +6631,8 @@ static void x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
+ CPUClass *cc = CPU_CLASS(xcc);
+
CPUX86State *env = &cpu->env;
FeatureWord w;
@@ -6992,6 +6689,11 @@ static void x86_cpu_initfn(Object *obj)
if (xcc->model) {
x86_cpu_load_model(cpu, xcc->model);
}
+
+ /* if required, do the accelerator-specific cpu initialization */
+ if (cc->accel_cpu_interface) {
+ cc->accel_cpu_interface->cpu_instance_init(CPU(obj));
+ }
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
@@ -7248,11 +6950,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
-
-#ifdef CONFIG_TCG
- tcg_cpu_common_class_init(cc);
-#endif /* CONFIG_TCG */
-
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
cc->gdb_read_register = x86_cpu_gdb_read_register;
@@ -7357,9 +7054,6 @@ static void x86_cpu_register_types(void)
}
type_register_static(&max_x86_cpu_type_info);
type_register_static(&x86_base_cpu_type_info);
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
- type_register_static(&host_x86_cpu_type_info);
-#endif
}
type_init(x86_cpu_register_types)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a0d64613dc..b3e39fc631 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1905,13 +1905,20 @@ int cpu_x86_signal_handler(int host_signum, void *pinfo,
void *puc);
/* cpu.c */
+void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
+ uint32_t vendor2, uint32_t vendor3);
+typedef struct PropValue {
+ const char *prop, *value;
+} PropValue;
+void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
+
+/* cpu.c other functions (cpuid) */
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx);
void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
-void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
/* helper.c */
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
@@ -2111,17 +2118,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
TPRAccess access);
-
-/* Change the value of a KVM-specific default
- *
- * If value is NULL, no default will be set and the original
- * value from the CPU model table will be kept.
- *
- * It is valid to call this function only for properties that
- * are already present in the kvm_default_props table.
- */
-void x86_cpu_change_kvm_default(const char *prop, const char *value);
-
/* Special values for X86CPUVersion: */
/* Resolve to latest CPU version */
diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c
new file mode 100644
index 0000000000..3ce2bc9a84
--- /dev/null
+++ b/target/i386/host-cpu.c
@@ -0,0 +1,198 @@
+/*
+ * x86 host CPU functions, and "host" cpu type initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "host-cpu.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+
+/* Note: Only safe for use on x86(-64) hosts */
+static uint32_t host_cpu_phys_bits(void)
+{
+ uint32_t eax;
+ uint32_t host_phys_bits;
+
+ host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
+ if (eax >= 0x80000008) {
+ host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
+ /*
+ * Note: According to AMD doc 25481 rev 2.34 they have a field
+ * at 23:16 that can specify a maximum physical address bits for
+ * the guest that can override this value; but I've not seen
+ * anything with that set.
+ */
+ host_phys_bits = eax & 0xff;
+ } else {
+ /*
+ * It's an odd 64 bit machine that doesn't have the leaf for
+ * physical address bits; fall back to 36 that's most older
+ * Intel.
+ */
+ host_phys_bits = 36;
+ }
+
+ return host_phys_bits;
+}
+
+static void host_cpu_enable_cpu_pm(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
+ &cpu->mwait.ecx, &cpu->mwait.edx);
+ env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
+}
+
+static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp)
+{
+ uint32_t host_phys_bits = host_cpu_phys_bits();
+ uint32_t phys_bits = cpu->phys_bits;
+ static bool warned;
+
+ /*
+ * Print a warning if the user set it to a value that's not the
+ * host value.
+ */
+ if (phys_bits != host_phys_bits && phys_bits != 0 &&
+ !warned) {
+ warn_report("Host physical bits (%u)"
+ " does not match phys-bits property (%u)",
+ host_phys_bits, phys_bits);
+ warned = true;
+ }
+
+ if (cpu->host_phys_bits) {
+ /* The user asked for us to use the host physical bits */
+ phys_bits = host_phys_bits;
+ if (cpu->host_phys_bits_limit &&
+ phys_bits > cpu->host_phys_bits_limit) {
+ phys_bits = cpu->host_phys_bits_limit;
+ }
+ }
+
+ if (phys_bits &&
+ (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
+ phys_bits < 32)) {
+ error_setg(errp, "phys-bits should be between 32 and %u "
+ " (but is %u)",
+ TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
+ }
+
+ return phys_bits;
+}
+
+void host_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ if (cpu->max_features && enable_cpu_pm) {
+ host_cpu_enable_cpu_pm(cpu);
+ }
+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
+ cpu->phys_bits = host_cpu_adjust_phys_bits(cpu, errp);
+ }
+}
+
+#define CPUID_MODEL_ID_SZ 48
+/**
+ * cpu_x86_fill_model_id:
+ * Get CPUID model ID string from host CPU.
+ *
+ * @str should have at least CPUID_MODEL_ID_SZ bytes
+ *
+ * The function does NOT add a null terminator to the string
+ * automatically.
+ */
+static int host_cpu_fill_model_id(char *str)
+{
+ uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
+ memcpy(str + i * 16 + 0, &eax, 4);
+ memcpy(str + i * 16 + 4, &ebx, 4);
+ memcpy(str + i * 16 + 8, &ecx, 4);
+ memcpy(str + i * 16 + 12, &edx, 4);
+ }
+ return 0;
+}
+
+void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping)
+{
+ uint32_t eax, ebx, ecx, edx;
+
+ host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
+
+ host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
+ if (family) {
+ *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
+ }
+ if (model) {
+ *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
+ }
+ if (stepping) {
+ *stepping = eax & 0x0F;
+ }
+}
+
+void host_cpu_instance_init(X86CPU *cpu)
+{
+ uint32_t ebx = 0, ecx = 0, edx = 0;
+ char vendor[CPUID_VENDOR_SZ + 1];
+
+ host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
+ x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
+
+ object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+}
+
+void host_cpu_max_instance_init(X86CPU *cpu)
+{
+ char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
+ char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
+ int family, model, stepping;
+
+ host_cpu_vendor_fms(vendor, &family, &model, &stepping);
+ host_cpu_fill_model_id(model_id);
+
+ object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+ object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", stepping,
+ &error_abort);
+ object_property_set_str(OBJECT(cpu), "model-id", model_id,
+ &error_abort);
+}
+
+static void host_cpu_class_init(ObjectClass *oc, void *data)
+{
+ X86CPUClass *xcc = X86_CPU_CLASS(oc);
+
+ xcc->host_cpuid_required = true;
+ xcc->ordering = 8;
+ xcc->model_description =
+ g_strdup_printf("processor with all supported host features ");
+}
+
+static const TypeInfo host_cpu_type_info = {
+ .name = X86_CPU_TYPE_NAME("host"),
+ .parent = X86_CPU_TYPE_NAME("max"),
+ .class_init = host_cpu_class_init,
+};
+
+static void host_cpu_type_init(void)
+{
+ type_register_static(&host_cpu_type_info);
+}
+
+type_init(host_cpu_type_init);
diff --git a/target/i386/host-cpu.h b/target/i386/host-cpu.h
new file mode 100644
index 0000000000..d1f2644422
--- /dev/null
+++ b/target/i386/host-cpu.h
@@ -0,0 +1,19 @@
+/*
+ * x86 host CPU type initialization and host CPU functions
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef HOST_CPU_H
+#define HOST_CPU_H
+
+void host_cpu_instance_init(X86CPU *cpu);
+void host_cpu_max_instance_init(X86CPU *cpu);
+void host_cpu_realizefn(CPUState *cs, Error **errp);
+
+void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping);
+
+#endif /* HOST_CPU_H */
diff --git a/target/i386/hvf/cpu.c b/target/i386/hvf/cpu.c
new file mode 100644
index 0000000000..d6579571f1
--- /dev/null
+++ b/target/i386/hvf/cpu.c
@@ -0,0 +1,65 @@
+/*
+ * x86 HVF CPU type initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "host-cpu.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "sysemu/hvf.h"
+#include "hw/core/accel-cpu.h"
+
+static void hvf_cpu_max_instance_init(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ host_cpu_max_instance_init(cpu);
+
+ env->cpuid_min_level =
+ hvf_get_supported_cpuid(0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
+}
+
+static void hvf_cpu_instance_init(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ host_cpu_instance_init(cpu);
+
+ /* Special cases not set in the X86CPUDefinition structs: */
+ /* TODO: in-kernel irqchip for hvf */
+
+ if (cpu->max_features) {
+ hvf_cpu_max_instance_init(cpu);
+ }
+}
+
+static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_realizefn = host_cpu_realizefn;
+ acc->cpu_instance_init = hvf_cpu_instance_init;
+};
+static const TypeInfo hvf_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("hvf"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = hvf_cpu_accel_class_init,
+ .abstract = true,
+};
+static void hvf_cpu_accel_register_types(void)
+{
+ type_register_static(&hvf_cpu_accel_type_info);
+}
+type_init(hvf_cpu_accel_register_types);
diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build
index 409c9a3f14..a7fba5724c 100644
--- a/target/i386/hvf/meson.build
+++ b/target/i386/hvf/meson.build
@@ -10,4 +10,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files(
'x86_mmu.c',
'x86_task.c',
'x86hvf.c',
+ 'cpu.c',
))
diff --git a/target/i386/kvm/cpu.c b/target/i386/kvm/cpu.c
new file mode 100644
index 0000000000..adc5120cf6
--- /dev/null
+++ b/target/i386/kvm/cpu.c
@@ -0,0 +1,148 @@
+/*
+ * x86 KVM CPU type initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "host-cpu.h"
+#include "kvm-cpu.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+
+#include "kvm_i386.h"
+#include "hw/core/accel-cpu.h"
+
+static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ /*
+ * The realize order is important, since x86_cpu_realize() checks if
+ * nothing else has been set by the user (or by accelerators) in
+ * cpu->ucode_rev and cpu->phys_bits.
+ *
+ * realize order:
+ * kvm_cpu -> host_cpu -> x86_cpu
+ */
+ if (cpu->max_features) {
+ if (enable_cpu_pm && kvm_has_waitpkg()) {
+ env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
+ }
+ if (cpu->ucode_rev == 0) {
+ cpu->ucode_rev =
+ kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_UCODE_REV);
+ }
+ }
+ host_cpu_realizefn(cs, errp);
+}
+
+/*
+ * KVM-specific features that are automatically added/removed
+ * from all CPU models when KVM is enabled.
+ */
+static PropValue kvm_default_props[] = {
+ { "kvmclock", "on" },
+ { "kvm-nopiodelay", "on" },
+ { "kvm-asyncpf", "on" },
+ { "kvm-steal-time", "on" },
+ { "kvm-pv-eoi", "on" },
+ { "kvmclock-stable-bit", "on" },
+ { "x2apic", "on" },
+ { "acpi", "off" },
+ { "monitor", "off" },
+ { "svm", "off" },
+ { NULL, NULL },
+};
+
+void x86_cpu_change_kvm_default(const char *prop, const char *value)
+{
+ PropValue *pv;
+ for (pv = kvm_default_props; pv->prop; pv++) {
+ if (!strcmp(pv->prop, prop)) {
+ pv->value = value;
+ break;
+ }
+ }
+
+ /*
+ * It is valid to call this function only for properties that
+ * are already present in the kvm_default_props table.
+ */
+ assert(pv->prop);
+}
+
+static bool lmce_supported(void)
+{
+ uint64_t mce_cap = 0;
+
+ if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
+ return false;
+ }
+ return !!(mce_cap & MCG_LMCE_P);
+}
+
+static void kvm_cpu_max_instance_init(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+ KVMState *s = kvm_state;
+
+ host_cpu_max_instance_init(cpu);
+
+ if (lmce_supported()) {
+ object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
+ }
+
+ env->cpuid_min_level =
+ kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
+}
+
+static void kvm_cpu_instance_init(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ host_cpu_instance_init(cpu);
+
+ if (!kvm_irqchip_in_kernel()) {
+ x86_cpu_change_kvm_default("x2apic", "off");
+ }
+
+ /* Special cases not set in the X86CPUDefinition structs: */
+
+ x86_cpu_apply_props(cpu, kvm_default_props);
+
+ if (cpu->max_features) {
+ kvm_cpu_max_instance_init(cpu);
+ }
+}
+
+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_realizefn = kvm_cpu_realizefn;
+ acc->cpu_instance_init = kvm_cpu_instance_init;
+}
+static const TypeInfo kvm_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = kvm_cpu_accel_class_init,
+ .abstract = true,
+};
+static void kvm_cpu_accel_register_types(void)
+{
+ type_register_static(&kvm_cpu_accel_type_info);
+}
+type_init(kvm_cpu_accel_register_types);
diff --git a/target/i386/kvm/kvm-cpu.h b/target/i386/kvm/kvm-cpu.h
new file mode 100644
index 0000000000..e858ca21e5
--- /dev/null
+++ b/target/i386/kvm/kvm-cpu.h
@@ -0,0 +1,41 @@
+/*
+ * i386 KVM CPU type and functions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef KVM_CPU_H
+#define KVM_CPU_H
+
+#ifdef CONFIG_KVM
+/*
+ * Change the value of a KVM-specific default
+ *
+ * If value is NULL, no default will be set and the original
+ * value from the CPU model table will be kept.
+ *
+ * It is valid to call this function only for properties that
+ * are already present in the kvm_default_props table.
+ */
+void x86_cpu_change_kvm_default(const char *prop, const char *value);
+
+#else /* !CONFIG_KVM */
+
+#define x86_cpu_change_kvm_default(a, b)
+
+#endif /* CONFIG_KVM */
+
+#endif /* KVM_CPU_H */
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index a2934dda02..35c86fdba6 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -22,6 +22,7 @@
#include "standard-headers/asm-x86/kvm_para.h"
#include "cpu.h"
+#include "host-cpu.h"
#include "sysemu/sysemu.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm_int.h"
@@ -285,7 +286,7 @@ static bool host_tsx_broken(void)
int family, model, stepping;\
char vendor[CPUID_VENDOR_SZ + 1];
- host_vendor_fms(vendor, &family, &model, &stepping);
+ host_cpu_vendor_fms(vendor, &family, &model, &stepping);
/* Check if we are running on a Haswell host known to have broken TSX */
return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build
index 1d66559187..0bc3724eb3 100644
--- a/target/i386/kvm/meson.build
+++ b/target/i386/kvm/meson.build
@@ -1,3 +1,8 @@
i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
-i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+
+i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files(
+ 'kvm.c',
+ 'cpu.c',
+))
+
i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 9c20208e5a..4e6e915e7f 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -6,8 +6,12 @@ i386_ss.add(files(
'xsave_helper.c',
'cpu-dump.c',
))
-i386_ss.add(when: 'CONFIG_TCG', if_true: files('tcg-cpu.c'))
-i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
+
+i386_ss.add(when: 'CONFIG_SEV', if_true: files('host-cpu.c', 'sev.c'), if_false: files('sev-stub.c'))
+
+# x86 cpu type
+i386_ss.add(when: 'CONFIG_KVM', if_true: files('host-cpu.c'))
+i386_ss.add(when: 'CONFIG_HVF', if_true: files('host-cpu.c'))
i386_softmmu_ss = ss.source_set()
i386_softmmu_ss.add(files(
diff --git a/target/i386/tcg-cpu.c b/target/i386/tcg-cpu.c
deleted file mode 100644
index 628dd29fe7..0000000000
--- a/target/i386/tcg-cpu.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * i386 TCG cpu class initialization
- *
- * Copyright (c) 2003 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "tcg-cpu.h"
-#include "exec/exec-all.h"
-#include "sysemu/runstate.h"
-#include "helper-tcg.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/i386/apic.h"
-#endif
-
-/* Frob eflags into and out of the CPU temporary format. */
-
-static void x86_cpu_exec_enter(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- env->df = 1 - (2 * ((env->eflags >> 10) & 1));
- CC_OP = CC_OP_EFLAGS;
- env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
-}
-
-static void x86_cpu_exec_exit(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- env->eflags = cpu_compute_eflags(env);
-}
-
-static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
-{
- X86CPU *cpu = X86_CPU(cs);
-
- cpu->env.eip = tb->pc - tb->cs_base;
-}
-
-void tcg_cpu_common_class_init(CPUClass *cc)
-{
- cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
- cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
- cc->cpu_exec_enter = x86_cpu_exec_enter;
- cc->cpu_exec_exit = x86_cpu_exec_exit;
- cc->tcg_initialize = tcg_x86_init;
- cc->tlb_fill = x86_cpu_tlb_fill;
-#ifndef CONFIG_USER_ONLY
- cc->debug_excp_handler = breakpoint_handler;
-#endif
-}
diff --git a/target/i386/tcg-cpu.h b/target/i386/tcg-cpu.h
deleted file mode 100644
index 81f02e562e..0000000000
--- a/target/i386/tcg-cpu.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * i386 TCG CPU class initialization
- *
- * Copyright 2020 SUSE LLC
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef TCG_CPU_H
-#define TCG_CPU_H
-
-void tcg_cpu_common_class_init(CPUClass *cc);
-
-#endif /* TCG_CPU_H */
diff --git a/target/i386/tcg/cpu.c b/target/i386/tcg/cpu.c
new file mode 100644
index 0000000000..bdb4971ba9
--- /dev/null
+++ b/target/i386/tcg/cpu.c
@@ -0,0 +1,173 @@
+/*
+ * i386 TCG cpu class initialization
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "helper-tcg.h"
+#include "qemu/accel.h"
+#include "hw/core/accel-cpu.h"
+
+#ifndef CONFIG_USER_ONLY
+#include "sysemu/sysemu.h"
+#include "qemu/units.h"
+#include "exec/address-spaces.h"
+#endif
+
+/* Frob eflags into and out of the CPU temporary format. */
+
+static void x86_cpu_exec_enter(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+ env->df = 1 - (2 * ((env->eflags >> 10) & 1));
+ CC_OP = CC_OP_EFLAGS;
+ env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+}
+
+static void x86_cpu_exec_exit(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ env->eflags = cpu_compute_eflags(env);
+}
+
+static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ cpu->env.eip = tb->pc - tb->cs_base;
+}
+
+#ifndef CONFIG_USER_ONLY
+
+static void x86_cpu_machine_done(Notifier *n, void *unused)
+{
+ X86CPU *cpu = container_of(n, X86CPU, machine_done);
+ MemoryRegion *smram =
+ (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
+
+ if (smram) {
+ cpu->smram = g_new(MemoryRegion, 1);
+ memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
+ smram, 0, 4 * GiB);
+ memory_region_set_enabled(cpu->smram, true);
+ memory_region_add_subregion_overlap(cpu->cpu_as_root, 0,
+ cpu->smram, 1);
+ }
+}
+
+static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ /*
+ * The realize order is important, since x86_cpu_realize() checks if
+ * nothing else has been set by the user (or by accelerators) in
+ * cpu->ucode_rev and cpu->phys_bits, and the memory regions
+ * initialized here are needed for the vcpu initialization.
+ *
+ * realize order:
+ * tcg_cpu -> host_cpu -> x86_cpu
+ */
+ cpu->cpu_as_mem = g_new(MemoryRegion, 1);
+ cpu->cpu_as_root = g_new(MemoryRegion, 1);
+
+ /* Outer container... */
+ memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
+ memory_region_set_enabled(cpu->cpu_as_root, true);
+
+ /*
+ * ... with two regions inside: normal system memory with low
+ * priority, and...
+ */
+ memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
+ get_system_memory(), 0, ~0ull);
+ memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
+ memory_region_set_enabled(cpu->cpu_as_mem, true);
+
+ cs->num_ases = 2;
+ cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
+ cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
+
+ /* ... SMRAM with higher priority, linked from /machine/smram. */
+ cpu->machine_done.notify = x86_cpu_machine_done;
+ qemu_add_machine_init_done_notifier(&cpu->machine_done);
+}
+
+#else /* CONFIG_USER_ONLY */
+
+static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+{
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+
+static void tcg_cpu_class_init(CPUClass *cc)
+{
+ cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->cpu_exec_enter = x86_cpu_exec_enter;
+ cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_initialize = tcg_x86_init;
+ cc->tlb_fill = x86_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->debug_excp_handler = breakpoint_handler;
+#endif /* !CONFIG_USER_ONLY */
+}
+
+/*
+ * TCG-specific defaults that override all CPU models when using TCG
+ */
+static PropValue tcg_default_props[] = {
+ { "vme", "off" },
+ { NULL, NULL },
+};
+
+static void tcg_cpu_instance_init(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ /* Special cases not set in the X86CPUDefinition structs: */
+ x86_cpu_apply_props(cpu, tcg_default_props);
+}
+
+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_realizefn = tcg_cpu_realizefn;
+ acc->cpu_class_init = tcg_cpu_class_init;
+ acc->cpu_instance_init = tcg_cpu_instance_init;
+}
+static const TypeInfo tcg_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = tcg_cpu_accel_class_init,
+ .abstract = true,
+};
+static void tcg_cpu_accel_register_types(void)
+{
+ type_register_static(&tcg_cpu_accel_type_info);
+}
+type_init(tcg_cpu_accel_register_types);
diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
index 02794226c2..9e439df9c7 100644
--- a/target/i386/tcg/meson.build
+++ b/target/i386/tcg/meson.build
@@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
'seg_helper.c',
'smm_helper.c',
'svm_helper.c',
- 'translate.c'), if_false: files('tcg-stub.c'))
+ 'translate.c',
+ 'cpu.c'), if_false: files('tcg-stub.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-26 22:32 ` [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
@ 2020-11-27 6:21 ` Paolo Bonzini
2020-11-27 8:59 ` Claudio Fontana
2020-12-18 17:51 ` Claudio Fontana
2020-11-27 17:06 ` Eduardo Habkost
1 sibling, 2 replies; 43+ messages in thread
From: Paolo Bonzini @ 2020-11-27 6:21 UTC (permalink / raw)
To: Claudio Fontana, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 26/11/20 23:32, Claudio Fontana wrote:
> + if (acc) {
> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
> + }
Any reason to do it for cpu_type only, rather than for all subclasses of
CPU_RESOLVING_TYPE? This would remove the cpu_type argument to
accel_init_cpu_interfaces and accel_init_interfaces.
Otherwise I haven't done a careful review yet but it looks very nice,
thanks!
Paolo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 6:21 ` Paolo Bonzini
@ 2020-11-27 8:59 ` Claudio Fontana
2020-11-27 11:22 ` Claudio Fontana
2020-12-18 17:51 ` Claudio Fontana
1 sibling, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 8:59 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 11/27/20 7:21 AM, Paolo Bonzini wrote:
> On 26/11/20 23:32, Claudio Fontana wrote:
>> + if (acc) {
>> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
>> + }
>
> Any reason to do it for cpu_type only, rather than for all subclasses of
> CPU_RESOLVING_TYPE? This would remove the cpu_type argument to
> accel_init_cpu_interfaces and accel_init_interfaces.
>
> Otherwise I haven't done a careful review yet but it looks very nice,
> thanks!
>
> Paolo
>
Hi Paolo,
yes, I thought to pass cpu_type in order to set the interface only for the cpu that is actually used,
instead of looping over all cpu models, just to be a bit quicker, but both things should work.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 8:59 ` Claudio Fontana
@ 2020-11-27 11:22 ` Claudio Fontana
2020-11-27 11:41 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 11:22 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Emilio G . Cota, haxm-team, Cameron Esfahani, Anthony Perard,
Bruce Rogers, Olaf Hering, Colin Xu
On 11/27/20 9:59 AM, Claudio Fontana wrote:
> On 11/27/20 7:21 AM, Paolo Bonzini wrote:
>> On 26/11/20 23:32, Claudio Fontana wrote:
>>> + if (acc) {
>>> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
>>> + }
>>
>> Any reason to do it for cpu_type only, rather than for all subclasses of
>> CPU_RESOLVING_TYPE? This would remove the cpu_type argument to
>> accel_init_cpu_interfaces and accel_init_interfaces.
>>
>> Otherwise I haven't done a careful review yet but it looks very nice,
>> thanks!
>>
>> Paolo
>>
>
> Hi Paolo,
>
> yes, I thought to pass cpu_type in order to set the interface only for the cpu that is actually used,
> instead of looping over all cpu models, just to be a bit quicker, but both things should work.
>
> Ciao,
>
> Claudio
>
Note that this actually creates a bug that is caught _ONLY_ by
acceptance-system-centos.
The gist of it is that cpu_type (or current_machine->default_cpu_type) is _not_ guaranteed to be set,
the code there is a bit misleading I think.
I'll look into it, but just wanted to warn early about it.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 11:22 ` Claudio Fontana
@ 2020-11-27 11:41 ` Claudio Fontana
2020-11-27 13:31 ` Paolo Bonzini
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 11:41 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Emilio G . Cota, haxm-team, Cameron Esfahani, Anthony Perard,
Bruce Rogers, Olaf Hering, Colin Xu
On 11/27/20 12:22 PM, Claudio Fontana wrote:
> On 11/27/20 9:59 AM, Claudio Fontana wrote:
>> On 11/27/20 7:21 AM, Paolo Bonzini wrote:
>>> On 26/11/20 23:32, Claudio Fontana wrote:
>>>> + if (acc) {
>>>> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
>>>> + }
>>>
>>> Any reason to do it for cpu_type only, rather than for all subclasses of
>>> CPU_RESOLVING_TYPE? This would remove the cpu_type argument to
>>> accel_init_cpu_interfaces and accel_init_interfaces.
>>>
>>> Otherwise I haven't done a careful review yet but it looks very nice,
>>> thanks!
>>>
>>> Paolo
>>>
>>
>> Hi Paolo,
>>
>> yes, I thought to pass cpu_type in order to set the interface only for the cpu that is actually used,
>> instead of looping over all cpu models, just to be a bit quicker, but both things should work.
>>
>> Ciao,
>>
>> Claudio
>>
>
> Note that this actually creates a bug that is caught _ONLY_ by
>
> acceptance-system-centos.
>
> The gist of it is that cpu_type (or current_machine->default_cpu_type) is _not_ guaranteed to be set,
> the code there is a bit misleading I think.
>
> I'll look into it, but just wanted to warn early about it.
>
> Ciao,
>
> Claudio
>
This seems to be due to "-machine none", is machine none supposed to have no default cpu_type?
Is it expected that for machine none current_machine->cpu_type is NULL, or is it a bug?
Thanks,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 11:41 ` Claudio Fontana
@ 2020-11-27 13:31 ` Paolo Bonzini
2020-11-27 13:32 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Paolo Bonzini @ 2020-11-27 13:31 UTC (permalink / raw)
To: Claudio Fontana, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Emilio G . Cota, haxm-team, Cameron Esfahani, Anthony Perard,
Bruce Rogers, Olaf Hering, Colin Xu
On 27/11/20 12:41, Claudio Fontana wrote:
> This seems to be due to "-machine none", is machine none supposed to
> have no default cpu_type? Is it expected that for machine none
> current_machine->cpu_type is NULL, or is it a bug?
"-machine none" has no CPU at all, so I think anything is acceptable.
There's also the possibility of emulating big.LITTLE machines in the
future with >1 cpu_type, so the cop out of doing it on the whole
hierarchy is easiest.
Paolo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 13:31 ` Paolo Bonzini
@ 2020-11-27 13:32 ` Claudio Fontana
0 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 13:32 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Emilio G . Cota, haxm-team, Cameron Esfahani, Anthony Perard,
Bruce Rogers, Olaf Hering, Colin Xu
On 11/27/20 2:31 PM, Paolo Bonzini wrote:
> On 27/11/20 12:41, Claudio Fontana wrote:
>> This seems to be due to "-machine none", is machine none supposed to
>> have no default cpu_type? Is it expected that for machine none
>> current_machine->cpu_type is NULL, or is it a bug?
>
> "-machine none" has no CPU at all, so I think anything is acceptable.
> There's also the possibility of emulating big.LITTLE machines in the
> future with >1 cpu_type, so the cop out of doing it on the whole
> hierarchy is easiest.
>
> Paolo
>
Ok will take that route then.
Thanks!
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-26 22:32 ` [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
2020-11-27 6:21 ` Paolo Bonzini
@ 2020-11-27 17:06 ` Eduardo Habkost
2020-11-27 17:58 ` Claudio Fontana
1 sibling, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 17:06 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Thu, Nov 26, 2020 at 11:32:17PM +0100, Claudio Fontana wrote:
> add a new optional interface to CPUClass,
> which allows accelerators to extend the CPUClass
> with additional accelerator-specific initializations.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> ---
[...]
> +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
> +{
> + CPUClass *cc = CPU_CLASS(klass);
> + AccelCPUClass *accel_cpu_interface = opaque;
> +
> + cc->accel_cpu_interface = accel_cpu_interface;
> + if (accel_cpu_interface->cpu_class_init) {
> + accel_cpu_interface->cpu_class_init(cc);
> + }
> +}
So, now that the approach we're following to trigger the
accel_init_cpu*() call is less controversial (thanks for your
patience!), we can try to address the monkey patching issue:
Monkey patching classes like this is acceptable as an initial
solution, but I'd like us to have a plan to eventually get rid of
it. Monkey patching CPU classes makes querying of CPU model
information less predictable and subtly dependent on QEMU
initialization state.
Removing CPUClass.accel_cpu_interface may be easy, because it
should be possible to just call current_accel() when realizing
CPUs. Getting rid of CPUClass.cpu_class_init might be more
difficult, depending on what the ->cpu_class_init() function is
doing.
> +
> +/* initialize the arch-specific accel CpuClass interfaces */
> +static void accel_init_cpu_interfaces(AccelClass *ac, const char *cpu_type)
> +{
> + const char *ac_name; /* AccelClass name */
> + char *acc_name; /* AccelCPUClass name */
> + ObjectClass *acc; /* AccelCPUClass */
> +
> + ac_name = object_class_get_name(OBJECT_CLASS(ac));
> + g_assert(ac_name != NULL);
> +
> + acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
> + acc = object_class_by_name(acc_name);
> + g_free(acc_name);
> +
> + if (acc) {
> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
> + }
> +}
> +
> void accel_init_interfaces(AccelClass *ac, const char *cpu_type)
> {
> #ifndef CONFIG_USER_ONLY
> accel_init_ops_interfaces(ac);
> #endif /* !CONFIG_USER_ONLY */
> +
> + accel_init_cpu_interfaces(ac, cpu_type);
> }
[...]
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2020-11-26 22:32 ` [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
@ 2020-11-27 17:41 ` Eduardo Habkost
2020-11-27 17:53 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 17:41 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Thu, Nov 26, 2020 at 11:32:18PM +0100, Claudio Fontana wrote:
> i386 is the first user of AccelCPUClass, allowing to split
> cpu.c into:
>
> cpu.c cpuid and common x86 cpu functionality
> host-cpu.c host x86 cpu functions and "host" cpu type
> kvm/cpu.c KVM x86 AccelCPUClass
> hvf/cpu.c HVF x86 AccelCPUClass
> tcg/cpu.c TCG x86 AccelCPUClass
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> ---
[...]
> +static void tcg_cpu_class_init(CPUClass *cc)
Is this the only case where we need to provide an
AccelCPUClass.cpu_class_init method?
> +{
> + cc->do_interrupt = x86_cpu_do_interrupt;
> + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
> + cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> + cc->cpu_exec_enter = x86_cpu_exec_enter;
> + cc->cpu_exec_exit = x86_cpu_exec_exit;
> + cc->tcg_initialize = tcg_x86_init;
> + cc->tlb_fill = x86_cpu_tlb_fill;
> +#ifndef CONFIG_USER_ONLY
> + cc->debug_excp_handler = breakpoint_handler;
> +#endif /* !CONFIG_USER_ONLY */
I find the need for these method overrides suspicious.
Comparing this with the code on qemu.git master:
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
[...]
#ifdef CONFIG_TCG
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
#endif
[...]
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
[...]
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
cc->debug_excp_handler = breakpoint_handler;
#endif
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
#ifdef CONFIG_TCG
cc->tcg_initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#endif
[...]
}
So, we have two kinds of CPUClass fields above:
* Code that was never conditional on CONFIG_TCG, and now is
conditional (synchronize_from_tb, cpu_exec_enter,
cpu_exec_exit).
* Code that was conditional on CONFIG_TCG at compile time, and is
now conditional on TCG being enabled at runtime.
On both cases, we are replacing static initialization of CPUClass
fields with dynamically initialization of CPUClass depending on
the chosen accelerator. What makes this necessary?
> +}
> +
> +/*
> + * TCG-specific defaults that override all CPU models when using TCG
> + */
> +static PropValue tcg_default_props[] = {
> + { "vme", "off" },
> + { NULL, NULL },
> +};
> +
> +static void tcg_cpu_instance_init(CPUState *cs)
> +{
> + X86CPU *cpu = X86_CPU(cs);
> + /* Special cases not set in the X86CPUDefinition structs: */
> + x86_cpu_apply_props(cpu, tcg_default_props);
> +}
> +
> +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
> +{
> + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
> +
> + acc->cpu_realizefn = tcg_cpu_realizefn;
> + acc->cpu_class_init = tcg_cpu_class_init;
> + acc->cpu_instance_init = tcg_cpu_instance_init;
> +}
> +static const TypeInfo tcg_cpu_accel_type_info = {
> + .name = ACCEL_CPU_NAME("tcg"),
> +
> + .parent = TYPE_ACCEL_CPU,
> + .class_init = tcg_cpu_accel_class_init,
> + .abstract = true,
> +};
> +static void tcg_cpu_accel_register_types(void)
> +{
> + type_register_static(&tcg_cpu_accel_type_info);
> +}
> +type_init(tcg_cpu_accel_register_types);
> diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
> index 02794226c2..9e439df9c7 100644
> --- a/target/i386/tcg/meson.build
> +++ b/target/i386/tcg/meson.build
> @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
> 'seg_helper.c',
> 'smm_helper.c',
> 'svm_helper.c',
> - 'translate.c'), if_false: files('tcg-stub.c'))
> + 'translate.c',
> + 'cpu.c'), if_false: files('tcg-stub.c'))
> --
> 2.26.2
>
>
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2020-11-27 17:41 ` Eduardo Habkost
@ 2020-11-27 17:53 ` Claudio Fontana
2020-11-27 18:09 ` Eduardo Habkost
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 17:53 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 11/27/20 6:41 PM, Eduardo Habkost wrote:
> On Thu, Nov 26, 2020 at 11:32:18PM +0100, Claudio Fontana wrote:
>> i386 is the first user of AccelCPUClass, allowing to split
>> cpu.c into:
>>
>> cpu.c cpuid and common x86 cpu functionality
>> host-cpu.c host x86 cpu functions and "host" cpu type
>> kvm/cpu.c KVM x86 AccelCPUClass
>> hvf/cpu.c HVF x86 AccelCPUClass
>> tcg/cpu.c TCG x86 AccelCPUClass
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> ---
> [...]
>> +static void tcg_cpu_class_init(CPUClass *cc)
>
> Is this the only case where we need to provide an
> AccelCPUClass.cpu_class_init method?
>
>
>> +{
>> + cc->do_interrupt = x86_cpu_do_interrupt;
>> + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
>> + cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
>> + cc->cpu_exec_enter = x86_cpu_exec_enter;
>> + cc->cpu_exec_exit = x86_cpu_exec_exit;
>> + cc->tcg_initialize = tcg_x86_init;
>> + cc->tlb_fill = x86_cpu_tlb_fill;
>> +#ifndef CONFIG_USER_ONLY
>> + cc->debug_excp_handler = breakpoint_handler;
>> +#endif /* !CONFIG_USER_ONLY */
>
> I find the need for these method overrides suspicious.
These mechanisms are preexistent. My refactoring only makes them more visible.
>
> Comparing this with the code on qemu.git master:
>
> static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> {
> [...]
> #ifdef CONFIG_TCG
> cc->do_interrupt = x86_cpu_do_interrupt;
> cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
> #endif
> [...]
> cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> [...]
> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> cc->debug_excp_handler = breakpoint_handler;
> #endif
> cc->cpu_exec_enter = x86_cpu_exec_enter;
> cc->cpu_exec_exit = x86_cpu_exec_exit;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = tcg_x86_init;
> cc->tlb_fill = x86_cpu_tlb_fill;
> #endif
> [...]
> }
>
> So, we have two kinds of CPUClass fields above:
> * Code that was never conditional on CONFIG_TCG, and now is
> conditional (synchronize_from_tb, cpu_exec_enter,
> cpu_exec_exit).
synchronize_from_tb, cpu_exec_enter and cpu_exec_exit only makes sense for TCG,
and their code should not be compiled in for non-TCG.
This is part of the effort to separate away non-pertinent code into accelerator-specific builds (and in the future modules).
The fact that they were unconditionally compiled in before was a mistake, or at least this is the assumption I am making when changing this.
> * Code that was conditional on CONFIG_TCG at compile time, and is
> now conditional on TCG being enabled at runtime.
>
> On both cases, we are replacing static initialization of CPUClass
> fields with dynamically initialization of CPUClass depending on
> the chosen accelerator. What makes this necessary?
I am not sure about the definitions of "static" and "dynamic" you are using here, as all the above looks "dynamic" to me, before and after.
The overrides and additional fields in the CPUClass are only necessary for TCG, and all that code should not be compiled in if TCG is not built-in.
Ciao,
Claudio
>
>
>> +}
>> +
>> +/*
>> + * TCG-specific defaults that override all CPU models when using TCG
>> + */
>> +static PropValue tcg_default_props[] = {
>> + { "vme", "off" },
>> + { NULL, NULL },
>> +};
>> +
>> +static void tcg_cpu_instance_init(CPUState *cs)
>> +{
>> + X86CPU *cpu = X86_CPU(cs);
>> + /* Special cases not set in the X86CPUDefinition structs: */
>> + x86_cpu_apply_props(cpu, tcg_default_props);
>> +}
>> +
>> +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
>> +{
>> + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
>> +
>> + acc->cpu_realizefn = tcg_cpu_realizefn;
>> + acc->cpu_class_init = tcg_cpu_class_init;
>> + acc->cpu_instance_init = tcg_cpu_instance_init;
>> +}
>> +static const TypeInfo tcg_cpu_accel_type_info = {
>> + .name = ACCEL_CPU_NAME("tcg"),
>> +
>> + .parent = TYPE_ACCEL_CPU,
>> + .class_init = tcg_cpu_accel_class_init,
>> + .abstract = true,
>> +};
>> +static void tcg_cpu_accel_register_types(void)
>> +{
>> + type_register_static(&tcg_cpu_accel_type_info);
>> +}
>> +type_init(tcg_cpu_accel_register_types);
>> diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
>> index 02794226c2..9e439df9c7 100644
>> --- a/target/i386/tcg/meson.build
>> +++ b/target/i386/tcg/meson.build
>> @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
>> 'seg_helper.c',
>> 'smm_helper.c',
>> 'svm_helper.c',
>> - 'translate.c'), if_false: files('tcg-stub.c'))
>> + 'translate.c',
>> + 'cpu.c'), if_false: files('tcg-stub.c'))
>> --
>> 2.26.2
>>
>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 17:06 ` Eduardo Habkost
@ 2020-11-27 17:58 ` Claudio Fontana
2020-11-27 18:13 ` Eduardo Habkost
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 17:58 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 11/27/20 6:06 PM, Eduardo Habkost wrote:
> On Thu, Nov 26, 2020 at 11:32:17PM +0100, Claudio Fontana wrote:
>> add a new optional interface to CPUClass,
>> which allows accelerators to extend the CPUClass
>> with additional accelerator-specific initializations.
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> ---
> [...]
>> +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
>> +{
>> + CPUClass *cc = CPU_CLASS(klass);
>> + AccelCPUClass *accel_cpu_interface = opaque;
>> +
>> + cc->accel_cpu_interface = accel_cpu_interface;
>> + if (accel_cpu_interface->cpu_class_init) {
>> + accel_cpu_interface->cpu_class_init(cc);
>> + }
>> +}
>
> So, now that the approach we're following to trigger the
> accel_init_cpu*() call is less controversial (thanks for your
> patience!), we can try to address the monkey patching issue:
>
> Monkey patching classes like this is acceptable as an initial
> solution, but I'd like us to have a plan to eventually get rid of
> it. Monkey patching CPU classes makes querying of CPU model
> information less predictable and subtly dependent on QEMU
> initialization state.
The question of QEMU initialization state and the querying of supported functionality, also in relationship with the loadable modules, is I think a larger discussion.
Regardless of the amount of glue code and lipstick, this is hiding the fact that the fundamentals of the object hierarchy for cpus are wrong,
and are (unfortunately) codified as part of the external interface.
>
> Removing CPUClass.accel_cpu_interface may be easy, because it
> should be possible to just call current_accel() when realizing
> CPUs. Getting rid of CPUClass.cpu_class_init might be more
> difficult, depending on what the ->cpu_class_init() function is
> doing.
This seems to be for a next step to me.
Ciao,
Claudio
>
>> +
>> +/* initialize the arch-specific accel CpuClass interfaces */
>> +static void accel_init_cpu_interfaces(AccelClass *ac, const char *cpu_type)
>> +{
>> + const char *ac_name; /* AccelClass name */
>> + char *acc_name; /* AccelCPUClass name */
>> + ObjectClass *acc; /* AccelCPUClass */
>> +
>> + ac_name = object_class_get_name(OBJECT_CLASS(ac));
>> + g_assert(ac_name != NULL);
>> +
>> + acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
>> + acc = object_class_by_name(acc_name);
>> + g_free(acc_name);
>> +
>> + if (acc) {
>> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
>> + }
>> +}
>> +
>> void accel_init_interfaces(AccelClass *ac, const char *cpu_type)
>> {
>> #ifndef CONFIG_USER_ONLY
>> accel_init_ops_interfaces(ac);
>> #endif /* !CONFIG_USER_ONLY */
>> +
>> + accel_init_cpu_interfaces(ac, cpu_type);
>> }
> [...]
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2020-11-27 17:53 ` Claudio Fontana
@ 2020-11-27 18:09 ` Eduardo Habkost
2020-11-27 18:16 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 18:09 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Fri, Nov 27, 2020 at 06:53:23PM +0100, Claudio Fontana wrote:
> On 11/27/20 6:41 PM, Eduardo Habkost wrote:
> > On Thu, Nov 26, 2020 at 11:32:18PM +0100, Claudio Fontana wrote:
> >> i386 is the first user of AccelCPUClass, allowing to split
> >> cpu.c into:
> >>
> >> cpu.c cpuid and common x86 cpu functionality
> >> host-cpu.c host x86 cpu functions and "host" cpu type
> >> kvm/cpu.c KVM x86 AccelCPUClass
> >> hvf/cpu.c HVF x86 AccelCPUClass
> >> tcg/cpu.c TCG x86 AccelCPUClass
> >>
> >> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> >> ---
> > [...]
> >> +static void tcg_cpu_class_init(CPUClass *cc)
> >
> > Is this the only case where we need to provide an
> > AccelCPUClass.cpu_class_init method?
> >
> >
> >> +{
> >> + cc->do_interrupt = x86_cpu_do_interrupt;
> >> + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
> >> + cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> >> + cc->cpu_exec_enter = x86_cpu_exec_enter;
> >> + cc->cpu_exec_exit = x86_cpu_exec_exit;
> >> + cc->tcg_initialize = tcg_x86_init;
> >> + cc->tlb_fill = x86_cpu_tlb_fill;
> >> +#ifndef CONFIG_USER_ONLY
> >> + cc->debug_excp_handler = breakpoint_handler;
> >> +#endif /* !CONFIG_USER_ONLY */
> >
> > I find the need for these method overrides suspicious.
>
> These mechanisms are preexistent. My refactoring only makes them more visible.
>
> >
> > Comparing this with the code on qemu.git master:
> >
> > static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> > {
> > [...]
> > #ifdef CONFIG_TCG
> > cc->do_interrupt = x86_cpu_do_interrupt;
> > cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
> > #endif
> > [...]
> > cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> > [...]
> > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> > cc->debug_excp_handler = breakpoint_handler;
> > #endif
> > cc->cpu_exec_enter = x86_cpu_exec_enter;
> > cc->cpu_exec_exit = x86_cpu_exec_exit;
> > #ifdef CONFIG_TCG
> > cc->tcg_initialize = tcg_x86_init;
> > cc->tlb_fill = x86_cpu_tlb_fill;
> > #endif
> > [...]
> > }
> >
> > So, we have two kinds of CPUClass fields above:
> > * Code that was never conditional on CONFIG_TCG, and now is
> > conditional (synchronize_from_tb, cpu_exec_enter,
> > cpu_exec_exit).
>
>
>
> synchronize_from_tb, cpu_exec_enter and cpu_exec_exit only makes sense for TCG,
> and their code should not be compiled in for non-TCG.
>
> This is part of the effort to separate away non-pertinent code into accelerator-specific builds (and in the future modules).
>
> The fact that they were unconditionally compiled in before was a mistake, or at least this is the assumption I am making when changing this.
Can you clarify why that was a mistake? Patch 07/11 makes
existing functions TCG-specific, but doesn't explain why.
>
>
> > * Code that was conditional on CONFIG_TCG at compile time, and is
> > now conditional on TCG being enabled at runtime.
> >
> > On both cases, we are replacing static initialization of CPUClass
> > fields with dynamically initialization of CPUClass depending on
> > the chosen accelerator. What makes this necessary?
>
>
> I am not sure about the definitions of "static" and "dynamic"
> you are using here, as all the above looks "dynamic" to me,
> before and after.
The existing code initializes all CPUClass fields as soon as
possible (at class_init), and we can be 100% sure the CPUClass
methods above are always pointing to the right function and will
never change.
This patch makes those CPUClass fields change at runtime, after
accelerator initialization.
This might be a reasonable approach if we have a good reason for
it, but what can we do to simplify this? If those methods really
depend on the accelerator (and not the CPU class), why aren't
they part of the CpusAccel struct instead of CPUClass?
>
> The overrides and additional fields in the CPUClass are only
> necessary for TCG, and all that code should not be compiled in
> if TCG is not built-in.
>
> Ciao,
>
> Claudio
>
> >
> >
> >> +}
> >> +
> >> +/*
> >> + * TCG-specific defaults that override all CPU models when using TCG
> >> + */
> >> +static PropValue tcg_default_props[] = {
> >> + { "vme", "off" },
> >> + { NULL, NULL },
> >> +};
> >> +
> >> +static void tcg_cpu_instance_init(CPUState *cs)
> >> +{
> >> + X86CPU *cpu = X86_CPU(cs);
> >> + /* Special cases not set in the X86CPUDefinition structs: */
> >> + x86_cpu_apply_props(cpu, tcg_default_props);
> >> +}
> >> +
> >> +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
> >> +{
> >> + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
> >> +
> >> + acc->cpu_realizefn = tcg_cpu_realizefn;
> >> + acc->cpu_class_init = tcg_cpu_class_init;
> >> + acc->cpu_instance_init = tcg_cpu_instance_init;
> >> +}
> >> +static const TypeInfo tcg_cpu_accel_type_info = {
> >> + .name = ACCEL_CPU_NAME("tcg"),
> >> +
> >> + .parent = TYPE_ACCEL_CPU,
> >> + .class_init = tcg_cpu_accel_class_init,
> >> + .abstract = true,
> >> +};
> >> +static void tcg_cpu_accel_register_types(void)
> >> +{
> >> + type_register_static(&tcg_cpu_accel_type_info);
> >> +}
> >> +type_init(tcg_cpu_accel_register_types);
> >> diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
> >> index 02794226c2..9e439df9c7 100644
> >> --- a/target/i386/tcg/meson.build
> >> +++ b/target/i386/tcg/meson.build
> >> @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
> >> 'seg_helper.c',
> >> 'smm_helper.c',
> >> 'svm_helper.c',
> >> - 'translate.c'), if_false: files('tcg-stub.c'))
> >> + 'translate.c',
> >> + 'cpu.c'), if_false: files('tcg-stub.c'))
> >> --
> >> 2.26.2
> >>
> >>
> >
>
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 17:58 ` Claudio Fontana
@ 2020-11-27 18:13 ` Eduardo Habkost
2020-11-27 18:20 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 18:13 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Fri, Nov 27, 2020 at 06:58:22PM +0100, Claudio Fontana wrote:
> On 11/27/20 6:06 PM, Eduardo Habkost wrote:
> > On Thu, Nov 26, 2020 at 11:32:17PM +0100, Claudio Fontana wrote:
> >> add a new optional interface to CPUClass,
> >> which allows accelerators to extend the CPUClass
> >> with additional accelerator-specific initializations.
> >>
> >> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> >> ---
> > [...]
> >> +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
> >> +{
> >> + CPUClass *cc = CPU_CLASS(klass);
> >> + AccelCPUClass *accel_cpu_interface = opaque;
> >> +
> >> + cc->accel_cpu_interface = accel_cpu_interface;
> >> + if (accel_cpu_interface->cpu_class_init) {
> >> + accel_cpu_interface->cpu_class_init(cc);
> >> + }
> >> +}
> >
> > So, now that the approach we're following to trigger the
> > accel_init_cpu*() call is less controversial (thanks for your
> > patience!), we can try to address the monkey patching issue:
> >
> > Monkey patching classes like this is acceptable as an initial
> > solution, but I'd like us to have a plan to eventually get rid of
> > it. Monkey patching CPU classes makes querying of CPU model
> > information less predictable and subtly dependent on QEMU
> > initialization state.
>
>
> The question of QEMU initialization state and the querying of supported functionality, also in relationship with the loadable modules, is I think a larger discussion.
>
> Regardless of the amount of glue code and lipstick, this is hiding the fact that the fundamentals of the object hierarchy for cpus are wrong,
> and are (unfortunately) codified as part of the external interface.
That's probably right, and removal of monkey patching might force
us to change our external interfaces.
>
>
> >
> > Removing CPUClass.accel_cpu_interface may be easy, because it
> > should be possible to just call current_accel() when realizing
> > CPUs. Getting rid of CPUClass.cpu_class_init might be more
> > difficult, depending on what the ->cpu_class_init() function is
> > doing.
>
>
> This seems to be for a next step to me.
Agreed, although I'd like to understand what makes
AccelCPUClass.cpu_class_init() so important in the first version
(considering that existing x86_cpu_class_init() has zero
tcg_enabled() calls today).
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2020-11-27 18:09 ` Eduardo Habkost
@ 2020-11-27 18:16 ` Claudio Fontana
2020-11-27 18:33 ` Eduardo Habkost
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 18:16 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 11/27/20 7:09 PM, Eduardo Habkost wrote:
> On Fri, Nov 27, 2020 at 06:53:23PM +0100, Claudio Fontana wrote:
>> On 11/27/20 6:41 PM, Eduardo Habkost wrote:
>>> On Thu, Nov 26, 2020 at 11:32:18PM +0100, Claudio Fontana wrote:
>>>> i386 is the first user of AccelCPUClass, allowing to split
>>>> cpu.c into:
>>>>
>>>> cpu.c cpuid and common x86 cpu functionality
>>>> host-cpu.c host x86 cpu functions and "host" cpu type
>>>> kvm/cpu.c KVM x86 AccelCPUClass
>>>> hvf/cpu.c HVF x86 AccelCPUClass
>>>> tcg/cpu.c TCG x86 AccelCPUClass
>>>>
>>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>>> ---
>>> [...]
>>>> +static void tcg_cpu_class_init(CPUClass *cc)
>>>
>>> Is this the only case where we need to provide an
>>> AccelCPUClass.cpu_class_init method?
>>>
>>>
>>>> +{
>>>> + cc->do_interrupt = x86_cpu_do_interrupt;
>>>> + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
>>>> + cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
>>>> + cc->cpu_exec_enter = x86_cpu_exec_enter;
>>>> + cc->cpu_exec_exit = x86_cpu_exec_exit;
>>>> + cc->tcg_initialize = tcg_x86_init;
>>>> + cc->tlb_fill = x86_cpu_tlb_fill;
>>>> +#ifndef CONFIG_USER_ONLY
>>>> + cc->debug_excp_handler = breakpoint_handler;
>>>> +#endif /* !CONFIG_USER_ONLY */
>>>
>>> I find the need for these method overrides suspicious.
>>
>> These mechanisms are preexistent. My refactoring only makes them more visible.
>>
>>>
>>> Comparing this with the code on qemu.git master:
>>>
>>> static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>>> {
>>> [...]
>>> #ifdef CONFIG_TCG
>>> cc->do_interrupt = x86_cpu_do_interrupt;
>>> cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
>>> #endif
>>> [...]
>>> cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
>>> [...]
>>> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>>> cc->debug_excp_handler = breakpoint_handler;
>>> #endif
>>> cc->cpu_exec_enter = x86_cpu_exec_enter;
>>> cc->cpu_exec_exit = x86_cpu_exec_exit;
>>> #ifdef CONFIG_TCG
>>> cc->tcg_initialize = tcg_x86_init;
>>> cc->tlb_fill = x86_cpu_tlb_fill;
>>> #endif
>>> [...]
>>> }
>>>
>>> So, we have two kinds of CPUClass fields above:
>>> * Code that was never conditional on CONFIG_TCG, and now is
>>> conditional (synchronize_from_tb, cpu_exec_enter,
>>> cpu_exec_exit).
>>
>>
>>
>> synchronize_from_tb, cpu_exec_enter and cpu_exec_exit only makes sense for TCG,
>> and their code should not be compiled in for non-TCG.
>>
>> This is part of the effort to separate away non-pertinent code into accelerator-specific builds (and in the future modules).
>>
>> The fact that they were unconditionally compiled in before was a mistake, or at least this is the assumption I am making when changing this.
>
> Can you clarify why that was a mistake? Patch 07/11 makes
> existing functions TCG-specific, but doesn't explain why.
They are functions called only for TCG. You don't need translation blocks and cpu_exec() for other accelerators.
I can add this information in the commit message.
>
>>
>>
>>> * Code that was conditional on CONFIG_TCG at compile time, and is
>>> now conditional on TCG being enabled at runtime.
>>>
>>> On both cases, we are replacing static initialization of CPUClass
>>> fields with dynamically initialization of CPUClass depending on
>>> the chosen accelerator. What makes this necessary?
>>
>>
>> I am not sure about the definitions of "static" and "dynamic"
>> you are using here, as all the above looks "dynamic" to me,
>> before and after.
>
> The existing code initializes all CPUClass fields as soon as
> possible (at class_init), and we can be 100% sure the CPUClass
> methods above are always pointing to the right function and will
> never change.
>
> This patch makes those CPUClass fields change at runtime, after
> accelerator initialization.
>
> This might be a reasonable approach if we have a good reason for
> it, but what can we do to simplify this? If those methods really
> depend on the accelerator (and not the CPU class), why aren't
> they part of the CpusAccel struct instead of CPUClass?
>
>
>>
>> The overrides and additional fields in the CPUClass are only
>> necessary for TCG, and all that code should not be compiled in
>> if TCG is not built-in.
>>
>> Ciao,
>>
>> Claudio
>>
>>>
>>>
>>>> +}
>>>> +
>>>> +/*
>>>> + * TCG-specific defaults that override all CPU models when using TCG
>>>> + */
>>>> +static PropValue tcg_default_props[] = {
>>>> + { "vme", "off" },
>>>> + { NULL, NULL },
>>>> +};
>>>> +
>>>> +static void tcg_cpu_instance_init(CPUState *cs)
>>>> +{
>>>> + X86CPU *cpu = X86_CPU(cs);
>>>> + /* Special cases not set in the X86CPUDefinition structs: */
>>>> + x86_cpu_apply_props(cpu, tcg_default_props);
>>>> +}
>>>> +
>>>> +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
>>>> +{
>>>> + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
>>>> +
>>>> + acc->cpu_realizefn = tcg_cpu_realizefn;
>>>> + acc->cpu_class_init = tcg_cpu_class_init;
>>>> + acc->cpu_instance_init = tcg_cpu_instance_init;
>>>> +}
>>>> +static const TypeInfo tcg_cpu_accel_type_info = {
>>>> + .name = ACCEL_CPU_NAME("tcg"),
>>>> +
>>>> + .parent = TYPE_ACCEL_CPU,
>>>> + .class_init = tcg_cpu_accel_class_init,
>>>> + .abstract = true,
>>>> +};
>>>> +static void tcg_cpu_accel_register_types(void)
>>>> +{
>>>> + type_register_static(&tcg_cpu_accel_type_info);
>>>> +}
>>>> +type_init(tcg_cpu_accel_register_types);
>>>> diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
>>>> index 02794226c2..9e439df9c7 100644
>>>> --- a/target/i386/tcg/meson.build
>>>> +++ b/target/i386/tcg/meson.build
>>>> @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
>>>> 'seg_helper.c',
>>>> 'smm_helper.c',
>>>> 'svm_helper.c',
>>>> - 'translate.c'), if_false: files('tcg-stub.c'))
>>>> + 'translate.c',
>>>> + 'cpu.c'), if_false: files('tcg-stub.c'))
>>>> --
>>>> 2.26.2
>>>>
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 18:13 ` Eduardo Habkost
@ 2020-11-27 18:20 ` Claudio Fontana
0 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 18:20 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 11/27/20 7:13 PM, Eduardo Habkost wrote:
> On Fri, Nov 27, 2020 at 06:58:22PM +0100, Claudio Fontana wrote:
>> On 11/27/20 6:06 PM, Eduardo Habkost wrote:
>>> On Thu, Nov 26, 2020 at 11:32:17PM +0100, Claudio Fontana wrote:
>>>> add a new optional interface to CPUClass,
>>>> which allows accelerators to extend the CPUClass
>>>> with additional accelerator-specific initializations.
>>>>
>>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>>> ---
>>> [...]
>>>> +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
>>>> +{
>>>> + CPUClass *cc = CPU_CLASS(klass);
>>>> + AccelCPUClass *accel_cpu_interface = opaque;
>>>> +
>>>> + cc->accel_cpu_interface = accel_cpu_interface;
>>>> + if (accel_cpu_interface->cpu_class_init) {
>>>> + accel_cpu_interface->cpu_class_init(cc);
>>>> + }
>>>> +}
>>>
>>> So, now that the approach we're following to trigger the
>>> accel_init_cpu*() call is less controversial (thanks for your
>>> patience!), we can try to address the monkey patching issue:
>>>
>>> Monkey patching classes like this is acceptable as an initial
>>> solution, but I'd like us to have a plan to eventually get rid of
>>> it. Monkey patching CPU classes makes querying of CPU model
>>> information less predictable and subtly dependent on QEMU
>>> initialization state.
>>
>>
>> The question of QEMU initialization state and the querying of supported functionality, also in relationship with the loadable modules, is I think a larger discussion.
>>
>> Regardless of the amount of glue code and lipstick, this is hiding the fact that the fundamentals of the object hierarchy for cpus are wrong,
>> and are (unfortunately) codified as part of the external interface.
>
> That's probably right, and removal of monkey patching might force
> us to change our external interfaces.
>
>>
>>
>>>
>>> Removing CPUClass.accel_cpu_interface may be easy, because it
>>> should be possible to just call current_accel() when realizing
>>> CPUs. Getting rid of CPUClass.cpu_class_init might be more
>>> difficult, depending on what the ->cpu_class_init() function is
>>> doing.
>>
>>
>> This seems to be for a next step to me.
>
> Agreed, although I'd like to understand what makes
> AccelCPUClass.cpu_class_init() so important in the first version
> (considering that existing x86_cpu_class_init() has zero
> tcg_enabled() calls today).
>
currently x86_cpu_common_class_init() has
#ifdef CONFIG_TCG
and
#ifdef CONFIG_USER_ONLY
I move this code to a tcg specific module,
and I also move the parts that should have been CONFIG_TCG before but were probably just missed.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2020-11-27 18:16 ` Claudio Fontana
@ 2020-11-27 18:33 ` Eduardo Habkost
0 siblings, 0 replies; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 18:33 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Fri, Nov 27, 2020 at 07:16:25PM +0100, Claudio Fontana wrote:
> On 11/27/20 7:09 PM, Eduardo Habkost wrote:
> > On Fri, Nov 27, 2020 at 06:53:23PM +0100, Claudio Fontana wrote:
> >> On 11/27/20 6:41 PM, Eduardo Habkost wrote:
> >>> On Thu, Nov 26, 2020 at 11:32:18PM +0100, Claudio Fontana wrote:
> >>>> i386 is the first user of AccelCPUClass, allowing to split
> >>>> cpu.c into:
> >>>>
> >>>> cpu.c cpuid and common x86 cpu functionality
> >>>> host-cpu.c host x86 cpu functions and "host" cpu type
> >>>> kvm/cpu.c KVM x86 AccelCPUClass
> >>>> hvf/cpu.c HVF x86 AccelCPUClass
> >>>> tcg/cpu.c TCG x86 AccelCPUClass
> >>>>
> >>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> >>>> ---
> >>> [...]
> >>>> +static void tcg_cpu_class_init(CPUClass *cc)
> >>>
> >>> Is this the only case where we need to provide an
> >>> AccelCPUClass.cpu_class_init method?
> >>>
> >>>
> >>>> +{
> >>>> + cc->do_interrupt = x86_cpu_do_interrupt;
> >>>> + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
> >>>> + cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> >>>> + cc->cpu_exec_enter = x86_cpu_exec_enter;
> >>>> + cc->cpu_exec_exit = x86_cpu_exec_exit;
> >>>> + cc->tcg_initialize = tcg_x86_init;
> >>>> + cc->tlb_fill = x86_cpu_tlb_fill;
> >>>> +#ifndef CONFIG_USER_ONLY
> >>>> + cc->debug_excp_handler = breakpoint_handler;
> >>>> +#endif /* !CONFIG_USER_ONLY */
> >>>
> >>> I find the need for these method overrides suspicious.
> >>
> >> These mechanisms are preexistent. My refactoring only makes them more visible.
> >>
> >>>
> >>> Comparing this with the code on qemu.git master:
> >>>
> >>> static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> >>> {
> >>> [...]
> >>> #ifdef CONFIG_TCG
> >>> cc->do_interrupt = x86_cpu_do_interrupt;
> >>> cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
> >>> #endif
> >>> [...]
> >>> cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> >>> [...]
> >>> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> >>> cc->debug_excp_handler = breakpoint_handler;
> >>> #endif
> >>> cc->cpu_exec_enter = x86_cpu_exec_enter;
> >>> cc->cpu_exec_exit = x86_cpu_exec_exit;
> >>> #ifdef CONFIG_TCG
> >>> cc->tcg_initialize = tcg_x86_init;
> >>> cc->tlb_fill = x86_cpu_tlb_fill;
> >>> #endif
> >>> [...]
> >>> }
> >>>
> >>> So, we have two kinds of CPUClass fields above:
> >>> * Code that was never conditional on CONFIG_TCG, and now is
> >>> conditional (synchronize_from_tb, cpu_exec_enter,
> >>> cpu_exec_exit).
> >>
> >>
> >>
> >> synchronize_from_tb, cpu_exec_enter and cpu_exec_exit only makes sense for TCG,
> >> and their code should not be compiled in for non-TCG.
> >>
> >> This is part of the effort to separate away non-pertinent code into accelerator-specific builds (and in the future modules).
> >>
> >> The fact that they were unconditionally compiled in before was a mistake, or at least this is the assumption I am making when changing this.
> >
> > Can you clarify why that was a mistake? Patch 07/11 makes
> > existing functions TCG-specific, but doesn't explain why.
>
>
>
> They are functions called only for TCG. You don't need translation blocks and cpu_exec() for other accelerators.
> I can add this information in the commit message.
Thanks! I believe we can clarify in patch 07/11 why some methods
that were not conditional on CONFIG_TCG were moved to
tcg_cpu_common_class_init().
Do you think it would be too complicated to move those methods
from CPUClass to CpusAccel? If they are really accel-specific,
CPUClass looks like the wrong place for them.
> [...]
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c
2020-11-26 22:32 ` [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
@ 2020-11-27 19:04 ` Eduardo Habkost
2020-11-27 19:47 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 19:04 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
Now that I understand what you are doing here, I have specific
questions about the functions you are moving, below:
On Thu, Nov 26, 2020 at 11:32:14PM +0100, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
[...]
> @@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
> cpu->env.features[FEAT_XSAVE_COMP_LO];
> }
>
> -const char *get_register_name_32(unsigned int reg)
> +/* Return name of 32-bit register, from a R_* constant */
> +static const char *get_register_name_32(unsigned int reg)
> {
> if (reg >= CPU_NB_REGS32) {
> return NULL;
> @@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.eip = value;
> }
>
> -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> -{
> - X86CPU *cpu = X86_CPU(cs);
> -
> - cpu->env.eip = tb->pc - tb->cs_base;
> -}
Question to be answered in the commit message: how can somebody
be sure this code is not necessary for any other accelerators?
The TranslationBlock* argument is a hint, but not a guarantee.
Maybe we should rename CPUClass.synchronize_from_tb to
CPUClass.tcg_synchronize_from_tb? Maybe we should have a
separate TCGCpuOperations struct to carry TCG-specific methods?
(The same questions above apply to the other methods below)
> -
> int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
> {
> X86CPU *cpu = X86_CPU(cs);
> @@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> cc->class_by_name = x86_cpu_class_by_name;
> cc->parse_features = x86_cpu_parse_featurestr;
> cc->has_work = x86_cpu_has_work;
> +
> #ifdef CONFIG_TCG
> - cc->do_interrupt = x86_cpu_do_interrupt;
> - cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
These two are in seg_helper.c, so I agree it makes sense to keep
it in tcg_cpu_common_class_init().
I'd like to understand why they are TCG-specific, though. Are
CPUClass.do_interrupt and CPUClass.cpu_exec_enter TCG-specific on
all architectures, or only in x86?
> -#endif
> + tcg_cpu_common_class_init(cc);
> +#endif /* CONFIG_TCG */
> +
> cc->dump_state = x86_cpu_dump_state;
> cc->set_pc = x86_cpu_set_pc;
> - cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> cc->gdb_read_register = x86_cpu_gdb_read_register;
> cc->gdb_write_register = x86_cpu_gdb_write_register;
> cc->get_arch_id = x86_cpu_get_arch_id;
> cc->get_paging_enabled = x86_cpu_get_paging_enabled;
> +
> #ifndef CONFIG_USER_ONLY
> cc->asidx_from_attrs = x86_asidx_from_attrs;
> cc->get_memory_mapping = x86_cpu_get_memory_mapping;
> @@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> cc->write_elf32_note = x86_cpu_write_elf32_note;
> cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
> cc->vmsd = &vmstate_x86_cpu;
> -#endif
> +#endif /* !CONFIG_USER_ONLY */
> +
> cc->gdb_arch_name = x86_gdb_arch_name;
> #ifdef TARGET_X86_64
> cc->gdb_core_xml_file = "i386-64bit.xml";
> @@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> #else
> cc->gdb_core_xml_file = "i386-32bit.xml";
> cc->gdb_num_core_regs = 50;
> -#endif
> -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> - cc->debug_excp_handler = breakpoint_handler;
That's in bpt_helper.c, also TCG-specific. Makes sense to move
it to tcg_cpu_common_class_init().
Is CPUClass.debug_excp_handler() TCG-specific in all
architectures, or only in x86?
> -#endif
> - cc->cpu_exec_enter = x86_cpu_exec_enter;
> - cc->cpu_exec_exit = x86_cpu_exec_exit;
I have a question about those two functions below[1].
> -#ifdef CONFIG_TCG
> - cc->tcg_initialize = tcg_x86_init;
The name makes this is obviously TCG-specific, so it makes sense
to move it to tcg_cpu_common_class_init().
> - cc->tlb_fill = x86_cpu_tlb_fill;
This is in excp_helper.c (TCG-specific), so it makes sense to
move it to tcg_cpu_common_class_init().
Is CPUClass.tlb_fill TCG-specific in all architectures, or only
in x86?
> #endif
> cc->disas_set_info = x86_disas_set_info;
>
[...]
> -/* Frob eflags into and out of the CPU temporary format. */
> -
> -void x86_cpu_exec_enter(CPUState *cs)
> -{
> - X86CPU *cpu = X86_CPU(cs);
> - CPUX86State *env = &cpu->env;
> -
> - CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
> - env->df = 1 - (2 * ((env->eflags >> 10) & 1));
> - CC_OP = CC_OP_EFLAGS;
> - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
> -}
> -
> -void x86_cpu_exec_exit(CPUState *cs)
> -{
> - X86CPU *cpu = X86_CPU(cs);
> - CPUX86State *env = &cpu->env;
> -
> - env->eflags = cpu_compute_eflags(env);
> -}
[1]
How exactly can we be 100% sure this is not used by other
accelerators?
> -
> #ifndef CONFIG_USER_ONLY
> uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
> {
[...]
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c
2020-11-27 19:04 ` Eduardo Habkost
@ 2020-11-27 19:47 ` Claudio Fontana
2020-11-27 20:43 ` Eduardo Habkost
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-11-27 19:47 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, gengdongjiu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy, Alex Bennee,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
Hi Eduardo,
On 11/27/20 8:04 PM, Eduardo Habkost wrote:
> Now that I understand what you are doing here, I have specific
> questions about the functions you are moving, below:
>
> On Thu, Nov 26, 2020 at 11:32:14PM +0100, Claudio Fontana wrote:
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> [...]
>> @@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
>> cpu->env.features[FEAT_XSAVE_COMP_LO];
>> }
>>
>> -const char *get_register_name_32(unsigned int reg)
>> +/* Return name of 32-bit register, from a R_* constant */
>> +static const char *get_register_name_32(unsigned int reg)
>> {
>> if (reg >= CPU_NB_REGS32) {
>> return NULL;
>> @@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
>> cpu->env.eip = value;
>> }
>>
>> -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
>> -{
>> - X86CPU *cpu = X86_CPU(cs);
>> -
>> - cpu->env.eip = tb->pc - tb->cs_base;
>> -}
>
> Question to be answered in the commit message: how can somebody
> be sure this code is not necessary for any other accelerators?
> The TranslationBlock* argument is a hint, but not a guarantee.
easiest is to just trace the calls, but there is a also helpful description of all these methods in hw/core/cpu.h.
$ mkid --include="C"
$ gid synchronize_from_tb
include/hw/core/cpu.h:110: * also implement the synchronize_from_tb hook.
include/hw/core/cpu.h:111: * @synchronize_from_tb: Callback for synchronizing state from a TCG
include/hw/core/cpu.h:194: void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
accel/tcg/cpu-exec.c:195: if (cc->synchronize_from_tb) {
accel/tcg/cpu-exec.c:196: cc->synchronize_from_tb(cpu, last_tb);
target/arm/cpu.c:2245: cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
target/avr/cpu.c:210: cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
target/hppa/cpu.c:146: cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
target/microblaze/cpu.c:325: cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
target/mips/cpu.c:241: cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
target/riscv/cpu.c:546: cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
target/rx/cpu.c:192: cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
target/sh4/cpu.c:225: cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
target/sparc/cpu.c:871: cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
target/tricore/cpu.c:165: cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
target/i386/tcg/cpu.c:129: cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> Maybe we should rename CPUClass.synchronize_from_tb to
> CPUClass.tcg_synchronize_from_tb? Maybe we should have a
possibly, yes.
> separate TCGCpuOperations struct to carry TCG-specific methods?
interesting, will think about it.
>
> (The same questions above apply to the other methods below)
>
>
>> -
>> int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
>> {
>> X86CPU *cpu = X86_CPU(cs);
>> @@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>> cc->class_by_name = x86_cpu_class_by_name;
>> cc->parse_features = x86_cpu_parse_featurestr;
>> cc->has_work = x86_cpu_has_work;
>> +
>> #ifdef CONFIG_TCG
>> - cc->do_interrupt = x86_cpu_do_interrupt;
>> - cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
>
> These two are in seg_helper.c, so I agree it makes sense to keep
> it in tcg_cpu_common_class_init().
>
> I'd like to understand why they are TCG-specific, though. Are
> CPUClass.do_interrupt and CPUClass.cpu_exec_enter TCG-specific on
> all architectures, or only in x86?
cpu_exec_enter: yes, tcg only on all archs.
Traces as above, it is only called by
accel/tcg/cpu-exec.c
cc->do_interrupt() is very interesting, it _should_ be the same story,
the use of cc->do_interrupt() is normally relegated to accel/tcg/cpu-exec.c,
or to the various implementations of cpu_exec_interrupt (also tcg-specific).
_BUT_ there is an exception in arm64 where it seems to be (strangely) used for kvm64:
So in this case the arm kvm64 code is the outlier. There are two calls, one introduced in 2015 and one in 2020:
commit e24fd076a59604c4ba3c05fe9d19ea6fc5320a12
Author: Dongjiu Geng <gengdongjiu@huawei.com>
Date: Tue May 12 11:06:08 2020 +0800
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
commit 34c45d53026d9c135415d034a8bc30c1a30acf1c
Author: Alex Bennée <alex.bennee@linaro.org>
Date: Thu Dec 17 13:37:15 2015 +0000
target-arm: kvm - re-inject guest debug exceptions
Maybe Alex and Dongjiu Geng (or maybe Peter?) can shed some light on whether this is intentional, or an oversight?
It is the one and only use of cc->do_interrupt outside of TCG. So strange.
>
>> -#endif
>> + tcg_cpu_common_class_init(cc);
>> +#endif /* CONFIG_TCG */
>> +
>> cc->dump_state = x86_cpu_dump_state;
>> cc->set_pc = x86_cpu_set_pc;
>> - cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
>> cc->gdb_read_register = x86_cpu_gdb_read_register;
>> cc->gdb_write_register = x86_cpu_gdb_write_register;
>> cc->get_arch_id = x86_cpu_get_arch_id;
>> cc->get_paging_enabled = x86_cpu_get_paging_enabled;
>> +
>> #ifndef CONFIG_USER_ONLY
>> cc->asidx_from_attrs = x86_asidx_from_attrs;
>> cc->get_memory_mapping = x86_cpu_get_memory_mapping;
>> @@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>> cc->write_elf32_note = x86_cpu_write_elf32_note;
>> cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
>> cc->vmsd = &vmstate_x86_cpu;
>> -#endif
>> +#endif /* !CONFIG_USER_ONLY */
>> +
>> cc->gdb_arch_name = x86_gdb_arch_name;
>> #ifdef TARGET_X86_64
>> cc->gdb_core_xml_file = "i386-64bit.xml";
>> @@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>> #else
>> cc->gdb_core_xml_file = "i386-32bit.xml";
>> cc->gdb_num_core_regs = 50;
>> -#endif
>> -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>> - cc->debug_excp_handler = breakpoint_handler;
>
> That's in bpt_helper.c, also TCG-specific. Makes sense to move
> it to tcg_cpu_common_class_init().
>
> Is CPUClass.debug_excp_handler() TCG-specific in all
> architectures, or only in x86?
>
>> -#endif
>> - cc->cpu_exec_enter = x86_cpu_exec_enter;
>> - cc->cpu_exec_exit = x86_cpu_exec_exit;
>
> I have a question about those two functions below[1].
>
>> -#ifdef CONFIG_TCG
>> - cc->tcg_initialize = tcg_x86_init;
>
> The name makes this is obviously TCG-specific, so it makes sense
> to move it to tcg_cpu_common_class_init().
>
>> - cc->tlb_fill = x86_cpu_tlb_fill;
>
> This is in excp_helper.c (TCG-specific), so it makes sense to
> move it to tcg_cpu_common_class_init().
>
> Is CPUClass.tlb_fill TCG-specific in all architectures, or only
> in x86?
TCG-specific on all, real CPU has its own real TLB.
Only accel/tcg/ uses the code.
>
>> #endif
>> cc->disas_set_info = x86_disas_set_info;
>>
> [...]
>> -/* Frob eflags into and out of the CPU temporary format. */
>> -
>> -void x86_cpu_exec_enter(CPUState *cs)
>> -{
>> - X86CPU *cpu = X86_CPU(cs);
>> - CPUX86State *env = &cpu->env;
>> -
>> - CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
>> - env->df = 1 - (2 * ((env->eflags >> 10) & 1));
>> - CC_OP = CC_OP_EFLAGS;
>> - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
>> -}
>> -
>> -void x86_cpu_exec_exit(CPUState *cs)
>> -{
>> - X86CPU *cpu = X86_CPU(cs);
>> - CPUX86State *env = &cpu->env;
>> -
>> - env->eflags = cpu_compute_eflags(env);
>> -}
>
> [1]
>
> How exactly can we be 100% sure this is not used by other
> accelerators?
The only calls to these methods are from accel/tcg/cpu-exec.c .
>
>> -
>> #ifndef CONFIG_USER_ONLY
>> uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
>> {
> [...]
>
I think that this exercise has been useful, and btw I am really interested about the possible comments from Alex or Geng DongJiu
on the extraordinary use of cc->do_interrupt for kvm64 on AArch64,
Thanks,
Ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c
2020-11-27 19:47 ` Claudio Fontana
@ 2020-11-27 20:43 ` Eduardo Habkost
2020-11-29 11:53 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2020-11-27 20:43 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, gengdongjiu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy, Alex Bennee,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Fri, Nov 27, 2020 at 08:47:00PM +0100, Claudio Fontana wrote:
> On 11/27/20 8:04 PM, Eduardo Habkost wrote:
[...]
> > Maybe we should rename CPUClass.synchronize_from_tb to
> > CPUClass.tcg_synchronize_from_tb? Maybe we should have a
>
> possibly, yes.
>
> > separate TCGCpuOperations struct to carry TCG-specific methods?
>
>
> interesting, will think about it.
I'm working on it at:
https://gitlab.com/ehabkost/qemu/-/commits/work/tcg-cpu-ops
Feel free to reuse it, if you want to do it before your series.
Otherwise, I can rebase it after your series is merged.
I didn't touch do_interrupt(), because of the aarch64 weirdness.
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c
2020-11-27 20:43 ` Eduardo Habkost
@ 2020-11-29 11:53 ` Claudio Fontana
0 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2020-11-29 11:53 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, gengdongjiu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy, Alex Bennee,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 11/27/20 9:43 PM, Eduardo Habkost wrote:
> On Fri, Nov 27, 2020 at 08:47:00PM +0100, Claudio Fontana wrote:
>> On 11/27/20 8:04 PM, Eduardo Habkost wrote:
> [...]
>>> Maybe we should rename CPUClass.synchronize_from_tb to
>>> CPUClass.tcg_synchronize_from_tb? Maybe we should have a
>>
>> possibly, yes.
>>
>>> separate TCGCpuOperations struct to carry TCG-specific methods?
>>
>>
>> interesting, will think about it.
>
> I'm working on it at:
> https://gitlab.com/ehabkost/qemu/-/commits/work/tcg-cpu-ops
>
> Feel free to reuse it, if you want to do it before your series.
> Otherwise, I can rebase it after your series is merged.
>
> I didn't touch do_interrupt(), because of the aarch64 weirdness.
>
Hi,
yes it makes sense to separate more clearly I think what is tcg only among those operations,
it is a bit tangent to my series in the sense that those methods need to be set one way or another,
either in cc-> or in cc->tcg_ops,
but yes, we could put those changes before or after the series, and I think they make sense.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-11-27 6:21 ` Paolo Bonzini
2020-11-27 8:59 ` Claudio Fontana
@ 2020-12-18 17:51 ` Claudio Fontana
2020-12-18 18:01 ` Paolo Bonzini
1 sibling, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-12-18 17:51 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 11/27/20 7:21 AM, Paolo Bonzini wrote:
> On 26/11/20 23:32, Claudio Fontana wrote:
>> + if (acc) {
>> + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc);
>> + }
>
> Any reason to do it for cpu_type only, rather than for all subclasses of
> CPU_RESOLVING_TYPE? This would remove the cpu_type argument to
> accel_init_cpu_interfaces and accel_init_interfaces.
>
> Otherwise I haven't done a careful review yet but it looks very nice,
> thanks!
>
> Paolo
>
Hi Paolo,
going back to this topic:
while doing some experiments in applying the ACCEL_CPU_TYPE classes for all targets (TCG for now, not KVM or other hw accels),
and merging all tcg cpu ops,
I did encounter some issue.
For the simplest of targets like hppa for example, it works just fine, we can do:
static void hppa_tcg_cpu_class_init(CPUClass *cc)
{
cc->tcg_ops.initialize = hppa_translate_init;
cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
#endif
}
*(later on I will try to change the cc->tcg_ops thing to something that ends up in cc->accel_cpu->tcg_ops->initialize, as I try to merge tcg_ops with accel_cpu, but this is spoiler of the future)*
static void hppa_tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
{
AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
acc->cpu_class_init = hppa_tcg_cpu_class_init;
}
static const TypeInfo hppa_tcg_cpu_accel_type = {
.name = ACCEL_CPU_NAME("tcg"),
.parent = TYPE_ACCEL_CPU,
.class_init = hppa_tcg_cpu_accel_class_init,
};
static void hppa_cpu_register_types(void)
{
type_register_static(&hppa_cpu_type_info);
type_register_static(&hppa_tcg_cpu_accel_type);
}
type_init(hppa_cpu_register_types)
So this is good.
But with things like cris/ for example,
the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
So in order to avoid code in the class initialization like this:
if (version1) { then set the tcg ops for version 1; }
if (version2) { then set the tcg ops for version 2; ...} etc,
we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
where typename needs to be known for sure.
This last option seems kinda attractive, but any ideas?
Thanks, ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-12-18 17:51 ` Claudio Fontana
@ 2020-12-18 18:01 ` Paolo Bonzini
2020-12-18 18:04 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Paolo Bonzini @ 2020-12-18 18:01 UTC (permalink / raw)
To: Claudio Fontana, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 18/12/20 18:51, Claudio Fontana wrote:
> But with things like cris/ for example,
> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>
> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
CRIS is not that bad since it's TCG only. You can just make it a field
in CRISCPUClass and copy it over to tcg_ops.
I think ARM had something similar though, with different do_interrupt
implementations for M and A processors. Somebody from Linaro was
cleaning it up as part of some BQL work, but it was never merged. But
even in that case, do_interrupt is somewhat special for ARM so making it
an xxxCPUClass field makes sense.
Paolo
> So in order to avoid code in the class initialization like this:
>
> if (version1) { then set the tcg ops for version 1; }
> if (version2) { then set the tcg ops for version 2; ...} etc,
>
> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>
> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>
> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
> where typename needs to be known for sure.
>
> This last option seems kinda attractive, but any ideas?
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-12-18 18:01 ` Paolo Bonzini
@ 2020-12-18 18:04 ` Claudio Fontana
2020-12-18 21:55 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-12-18 18:04 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/18/20 7:01 PM, Paolo Bonzini wrote:
> On 18/12/20 18:51, Claudio Fontana wrote:
>> But with things like cris/ for example,
>> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>>
>> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
>
> CRIS is not that bad since it's TCG only. You can just make it a field
> in CRISCPUClass and copy it over to tcg_ops.
>
> I think ARM had something similar though, with different do_interrupt
> implementations for M and A processors. Somebody from Linaro was
> cleaning it up as part of some BQL work, but it was never merged. But
> even in that case, do_interrupt is somewhat special for ARM so making it
> an xxxCPUClass field makes sense.
>
> Paolo
Ok that's a good alternative,
>
>> So in order to avoid code in the class initialization like this:
>>
>> if (version1) { then set the tcg ops for version 1; }
>> if (version2) { then set the tcg ops for version 2; ...} etc,
>>
>> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>>
>> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
>> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>>
>> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
>> where typename needs to be known for sure.
I take you don't like this idea to initialize the accel cpu interface in cpu_create()?
It seems to make sense to me, but any drawbacks?
Ciao thanks!
Claudio
>>
>> This last option seems kinda attractive, but any ideas?
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-12-18 18:04 ` Claudio Fontana
@ 2020-12-18 21:55 ` Claudio Fontana
2020-12-18 22:30 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-12-18 21:55 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/18/20 7:04 PM, Claudio Fontana wrote:
> On 12/18/20 7:01 PM, Paolo Bonzini wrote:
>> On 18/12/20 18:51, Claudio Fontana wrote:
>>> But with things like cris/ for example,
>>> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>>>
>>> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
>>
>> CRIS is not that bad since it's TCG only. You can just make it a field
>> in CRISCPUClass and copy it over to tcg_ops.
>>
>> I think ARM had something similar though, with different do_interrupt
>> implementations for M and A processors. Somebody from Linaro was
>> cleaning it up as part of some BQL work, but it was never merged. But
>> even in that case, do_interrupt is somewhat special for ARM so making it
>> an xxxCPUClass field makes sense.
>>
>> Paolo
>
> Ok that's a good alternative,
>
>>
>>> So in order to avoid code in the class initialization like this:
>>>
>>> if (version1) { then set the tcg ops for version 1; }
>>> if (version2) { then set the tcg ops for version 2; ...} etc,
>>>
>>> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>>>
>>> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
>>> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>>>
>>> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
>>> where typename needs to be known for sure.
>
>
> I take you don't like this idea to initialize the accel cpu interface in cpu_create()?
> It seems to make sense to me, but any drawbacks?
>
> Ciao thanks!
>
> Claudio
>
>
>>>
>>> This last option seems kinda attractive, but any ideas?
>
>
Oh I see, sadly, only user mode code seem to be guaranteed to go through cpu_create(), so there is probably no single code point,
where we are guaranteed to see the creation of a cpu, everything is duplicated with explict calls to object_new in multiple places.
Hmm...
Ciao,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-12-18 21:55 ` Claudio Fontana
@ 2020-12-18 22:30 ` Claudio Fontana
2020-12-18 23:00 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-12-18 22:30 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/18/20 10:55 PM, Claudio Fontana wrote:
> On 12/18/20 7:04 PM, Claudio Fontana wrote:
>> On 12/18/20 7:01 PM, Paolo Bonzini wrote:
>>> On 18/12/20 18:51, Claudio Fontana wrote:
>>>> But with things like cris/ for example,
>>>> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>>>>
>>>> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
>>>
>>> CRIS is not that bad since it's TCG only. You can just make it a field
>>> in CRISCPUClass and copy it over to tcg_ops.
>>>
>>> I think ARM had something similar though, with different do_interrupt
>>> implementations for M and A processors. Somebody from Linaro was
>>> cleaning it up as part of some BQL work, but it was never merged. But
>>> even in that case, do_interrupt is somewhat special for ARM so making it
>>> an xxxCPUClass field makes sense.
>>>
>>> Paolo
>>
>> Ok that's a good alternative,
>>
>>>
>>>> So in order to avoid code in the class initialization like this:
>>>>
>>>> if (version1) { then set the tcg ops for version 1; }
>>>> if (version2) { then set the tcg ops for version 2; ...} etc,
>>>>
>>>> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>>>>
>>>> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
>>>> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>>>>
>>>> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
>>>> where typename needs to be known for sure.
>>
>>
>> I take you don't like this idea to initialize the accel cpu interface in cpu_create()?
>> It seems to make sense to me, but any drawbacks?
>>
>> Ciao thanks!
>>
>> Claudio
>>
>>
>>>>
>>>> This last option seems kinda attractive, but any ideas?
>>
>>
>
> Oh I see, sadly, only user mode code seem to be guaranteed to go through cpu_create(), so there is probably no single code point,
> where we are guaranteed to see the creation of a cpu, everything is duplicated with explict calls to object_new in multiple places.
>
> Hmm...
Well we can actually do it in the right place, that is in cpu_common_intfn,
by calling accel_init_cpu_intefaces there, which kinda makes sense anyway... wdyt?
Ciao,
CLaudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-12-18 22:30 ` Claudio Fontana
@ 2020-12-18 23:00 ` Claudio Fontana
2021-01-11 16:13 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2020-12-18 23:00 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Cameron Esfahani, haxm-team, Colin Xu, Anthony Perard,
Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/18/20 11:30 PM, Claudio Fontana wrote:
> On 12/18/20 10:55 PM, Claudio Fontana wrote:
>> On 12/18/20 7:04 PM, Claudio Fontana wrote:
>>> On 12/18/20 7:01 PM, Paolo Bonzini wrote:
>>>> On 18/12/20 18:51, Claudio Fontana wrote:
>>>>> But with things like cris/ for example,
>>>>> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>>>>>
>>>>> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
>>>>
>>>> CRIS is not that bad since it's TCG only. You can just make it a field
>>>> in CRISCPUClass and copy it over to tcg_ops.
>>>>
>>>> I think ARM had something similar though, with different do_interrupt
>>>> implementations for M and A processors. Somebody from Linaro was
>>>> cleaning it up as part of some BQL work, but it was never merged. But
>>>> even in that case, do_interrupt is somewhat special for ARM so making it
>>>> an xxxCPUClass field makes sense.
>>>>
>>>> Paolo
>>>
>>> Ok that's a good alternative,
>>>
>>>>
>>>>> So in order to avoid code in the class initialization like this:
>>>>>
>>>>> if (version1) { then set the tcg ops for version 1; }
>>>>> if (version2) { then set the tcg ops for version 2; ...} etc,
>>>>>
>>>>> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>>>>>
>>>>> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
>>>>> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>>>>>
>>>>> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
>>>>> where typename needs to be known for sure.
>>>
>>>
>>> I take you don't like this idea to initialize the accel cpu interface in cpu_create()?
>>> It seems to make sense to me, but any drawbacks?
>>>
>>> Ciao thanks!
>>>
>>> Claudio
>>>
>>>
>>>>>
>>>>> This last option seems kinda attractive, but any ideas?
>>>
>>>
>>
>> Oh I see, sadly, only user mode code seem to be guaranteed to go through cpu_create(), so there is probably no single code point,
>> where we are guaranteed to see the creation of a cpu, everything is duplicated with explict calls to object_new in multiple places.
>>
>> Hmm...
>
> Well we can actually do it in the right place, that is in cpu_common_intfn,
> by calling accel_init_cpu_intefaces there, which kinda makes sense anyway... wdyt?
>
But then the mapping becomes difficult.. actually I think we/I need to study carefully all targets to figure out the best way to associate a cpu subclass/model with its accel cpu interface.
it's going to be next year now.
Happy holidays,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2020-12-18 23:00 ` Claudio Fontana
@ 2021-01-11 16:13 ` Claudio Fontana
2021-01-11 18:08 ` Claudio Fontana
2021-01-11 22:35 ` Eduardo Habkost
0 siblings, 2 replies; 43+ messages in thread
From: Claudio Fontana @ 2021-01-11 16:13 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Emilio G . Cota, haxm-team, Cameron Esfahani, Anthony Perard,
Bruce Rogers, Olaf Hering, Colin Xu
On 12/19/20 12:00 AM, Claudio Fontana wrote:
> On 12/18/20 11:30 PM, Claudio Fontana wrote:
>> On 12/18/20 10:55 PM, Claudio Fontana wrote:
>>> On 12/18/20 7:04 PM, Claudio Fontana wrote:
>>>> On 12/18/20 7:01 PM, Paolo Bonzini wrote:
>>>>> On 18/12/20 18:51, Claudio Fontana wrote:
>>>>>> But with things like cris/ for example,
>>>>>> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>>>>>>
>>>>>> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
>>>>>
>>>>> CRIS is not that bad since it's TCG only. You can just make it a field
>>>>> in CRISCPUClass and copy it over to tcg_ops.
>>>>>
>>>>> I think ARM had something similar though, with different do_interrupt
>>>>> implementations for M and A processors. Somebody from Linaro was
>>>>> cleaning it up as part of some BQL work, but it was never merged. But
>>>>> even in that case, do_interrupt is somewhat special for ARM so making it
>>>>> an xxxCPUClass field makes sense.
>>>>>
>>>>> Paolo
>>>>
>>>> Ok that's a good alternative,
>>>>
>>>>>
>>>>>> So in order to avoid code in the class initialization like this:
>>>>>>
>>>>>> if (version1) { then set the tcg ops for version 1; }
>>>>>> if (version2) { then set the tcg ops for version 2; ...} etc,
>>>>>>
>>>>>> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>>>>>>
>>>>>> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
>>>>>> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>>>>>>
>>>>>> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
>>>>>> where typename needs to be known for sure.
>>>>
>>>>
>>>> I take you don't like this idea to initialize the accel cpu interface in cpu_create()?
>>>> It seems to make sense to me, but any drawbacks?
>>>>
>>>> Ciao thanks!
>>>>
>>>> Claudio
>>>>
>>>>
Happy new year,
picking up this topic again, i am looking at at now a different aspect of this problem, of setting the right tcg ops for the right cpu class.
This issue I am highlighting is present because different targets behave differently in this regard.
Ie, we have targets for which we always initialize all cpu classes, as a result of different machine definitions.
This is the case of arm, for example where we end up with backtraces like:
arm_v7m_class_init
type_initialize
object_class_foreach_tramp
g_hash_table_foreach ()
object_class_foreach
object_class_get_list
select_machine ()
qemu_init
main
with the arm_v7m_class_init called even if we are just going to use an aarch64 cpu (so the class initializer for arm_v7m is called even for unused cpus classes),
while in other cases we have the target explicitly relying on the fact that only the right cpu class is initialized, for example in cris we have code like:
target/cris/cpu.c:
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_initialize = cris_initialize_crisv10_tcg;
}
where the class initialization of the cpu is explicitly setting the methods of CPUClass, therefore implicitly relying on the fact that no other class initializer screws things up.
Given this context, which one of these methods is "right"? Should we rework things so that only used cpu classes are actually initialized?
Or should we maybe not do these settings in cpu class_init at all, but rather at cpu initfn time, or at cpu realize time?
any comments/preferences?
Thanks,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2021-01-11 16:13 ` Claudio Fontana
@ 2021-01-11 18:08 ` Claudio Fontana
2021-01-11 22:35 ` Eduardo Habkost
1 sibling, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2021-01-11 18:08 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Eduardo Habkost, Paul Durrant, Jason Wang,
Marcelo Tosatti, qemu-devel, Peter Xu, Dario Faggioli,
Emilio G . Cota, haxm-team, Cameron Esfahani, Anthony Perard,
Bruce Rogers, Olaf Hering, Colin Xu
On 1/11/21 5:13 PM, Claudio Fontana wrote:
> On 12/19/20 12:00 AM, Claudio Fontana wrote:
>> On 12/18/20 11:30 PM, Claudio Fontana wrote:
>>> On 12/18/20 10:55 PM, Claudio Fontana wrote:
>>>> On 12/18/20 7:04 PM, Claudio Fontana wrote:
>>>>> On 12/18/20 7:01 PM, Paolo Bonzini wrote:
>>>>>> On 18/12/20 18:51, Claudio Fontana wrote:
>>>>>>> But with things like cris/ for example,
>>>>>>> the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU.
>>>>>>>
>>>>>>> Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE.
>>>>>>
>>>>>> CRIS is not that bad since it's TCG only. You can just make it a field
>>>>>> in CRISCPUClass and copy it over to tcg_ops.
>>>>>>
>>>>>> I think ARM had something similar though, with different do_interrupt
>>>>>> implementations for M and A processors. Somebody from Linaro was
>>>>>> cleaning it up as part of some BQL work, but it was never merged. But
>>>>>> even in that case, do_interrupt is somewhat special for ARM so making it
>>>>>> an xxxCPUClass field makes sense.
>>>>>>
>>>>>> Paolo
>>>>>
>>>>> Ok that's a good alternative,
>>>>>
>>>>>>
>>>>>>> So in order to avoid code in the class initialization like this:
>>>>>>>
>>>>>>> if (version1) { then set the tcg ops for version 1; }
>>>>>>> if (version2) { then set the tcg ops for version 2; ...} etc,
>>>>>>>
>>>>>>> we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically.
>>>>>>>
>>>>>>> But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work..
>>>>>>> we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use.
>>>>>>>
>>>>>>> Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename),
>>>>>>> where typename needs to be known for sure.
>>>>>
>>>>>
>>>>> I take you don't like this idea to initialize the accel cpu interface in cpu_create()?
>>>>> It seems to make sense to me, but any drawbacks?
>>>>>
>>>>> Ciao thanks!
>>>>>
>>>>> Claudio
>>>>>
>>>>>
>
>
> Happy new year,
>
> picking up this topic again, i am looking at at now a different aspect of this problem, of setting the right tcg ops for the right cpu class.
>
> This issue I am highlighting is present because different targets behave differently in this regard.
>
> Ie, we have targets for which we always initialize all cpu classes, as a result of different machine definitions.
>
> This is the case of arm, for example where we end up with backtraces like:
>
> arm_v7m_class_init
> type_initialize
> object_class_foreach_tramp
> g_hash_table_foreach ()
> object_class_foreach
> object_class_get_list
> select_machine ()
> qemu_init
> main
>
> with the arm_v7m_class_init called even if we are just going to use an aarch64 cpu (so the class initializer for arm_v7m is called even for unused cpus classes),
>
> while in other cases we have the target explicitly relying on the fact that only the right cpu class is initialized, for example in cris we have code like:
>
> target/cris/cpu.c:
>
> static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
> {
> CPUClass *cc = CPU_CLASS(oc);
> CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
>
> ccc->vr = 9;
> cc->do_interrupt = crisv10_cpu_do_interrupt;
> cc->gdb_read_register = crisv10_cpu_gdb_read_register;
> cc->tcg_initialize = cris_initialize_crisv10_tcg;
> }
>
> where the class initialization of the cpu is explicitly setting the methods of CPUClass, therefore implicitly relying on the fact that no other class initializer screws things up.
>
> Given this context, which one of these methods is "right"? Should we rework things so that only used cpu classes are actually initialized?
> Or should we maybe not do these settings in cpu class_init at all, but rather at cpu initfn time, or at cpu realize time?
>
> any comments/preferences?
>
Or is the hierarchy magically fixing this for us (ie, we rely on the class initializers being called again when the cpu we are actually going to be used is going to be created?)
That seems the likely solution right?
Thanks,
Claudio
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode
2020-11-26 22:32 ` [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode Claudio Fontana
@ 2021-01-11 18:43 ` Claudio Fontana
2021-01-12 9:23 ` Claudio Fontana
0 siblings, 1 reply; 43+ messages in thread
From: Claudio Fontana @ 2021-01-11 18:43 UTC (permalink / raw)
To: Richard Henderson
Cc: Thomas Huth, Eduardo Habkost, Philippe Mathieu-Daudé,
qemu-devel, Paolo Bonzini, Alex Bennee
Hi Richard,
happy new year,
this change of mine breaks with --enable-debug, after your changes related to "splitrw" in tcg/,
I am a bit at a loss at what could be going wrong.. any hints?
I am getting assertion failures with --enable-debug in make check-tcg,
in particular in tcg/tcg.c:768
#ifdef CONFIG_DEBUG_TCG
const void *tcg_splitwx_to_rx(void *rw)
{
/* Pass NULL pointers unchanged. */
if (rw) {
g_assert(in_code_gen_buffer(rw)); /* <=== HERE */
rw += tcg_splitwx_diff;
}
return rw;
}
any hints?
Thanks,
Claudio
On 11/26/20 11:32 PM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> ---
> MAINTAINERS | 2 +-
> accel/accel-common.c | 50 ++++++++++++++++++++++++++++++
> accel/{accel.c => accel-softmmu.c} | 27 ++--------------
> accel/accel-user.c | 24 ++++++++++++++
> accel/meson.build | 4 ++-
> accel/qtest/qtest.c | 2 +-
> accel/tcg/meson.build | 2 +-
> accel/tcg/tcg-all.c | 7 ++++-
> accel/xen/xen-all.c | 2 +-
> bsd-user/main.c | 7 +++--
> include/hw/boards.h | 2 +-
> include/{sysemu => qemu}/accel.h | 14 +++++----
> include/sysemu/hvf.h | 2 +-
> include/sysemu/kvm.h | 2 +-
> include/sysemu/kvm_int.h | 2 +-
> linux-user/main.c | 7 +++--
> softmmu/memory.c | 2 +-
> softmmu/qtest.c | 2 +-
> softmmu/vl.c | 2 +-
> target/i386/hax/hax-all.c | 2 +-
> target/i386/hvf/hvf-i386.h | 2 +-
> target/i386/hvf/hvf.c | 2 +-
> target/i386/hvf/x86_task.c | 2 +-
> target/i386/whpx/whpx-all.c | 2 +-
> 24 files changed, 119 insertions(+), 53 deletions(-)
> create mode 100644 accel/accel-common.c
> rename accel/{accel.c => accel-softmmu.c} (75%)
> create mode 100644 accel/accel-user.c
> rename include/{sysemu => qemu}/accel.h (95%)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e892dd2220..d7c212843c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -433,7 +433,7 @@ Overall
> M: Richard Henderson <richard.henderson@linaro.org>
> R: Paolo Bonzini <pbonzini@redhat.com>
> S: Maintained
> -F: include/sysemu/accel.h
> +F: include/qemu/accel.h
> F: accel/accel.c
> F: accel/Makefile.objs
> F: accel/stubs/Makefile.objs
> diff --git a/accel/accel-common.c b/accel/accel-common.c
> new file mode 100644
> index 0000000000..ddec8cb5ae
> --- /dev/null
> +++ b/accel/accel-common.c
> @@ -0,0 +1,50 @@
> +/*
> + * QEMU accel class, components common to system emulation and user mode
> + *
> + * Copyright (c) 2003-2008 Fabrice Bellard
> + * Copyright (c) 2014 Red Hat Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/accel.h"
> +
> +static const TypeInfo accel_type = {
> + .name = TYPE_ACCEL,
> + .parent = TYPE_OBJECT,
> + .class_size = sizeof(AccelClass),
> + .instance_size = sizeof(AccelState),
> +};
> +
> +/* Lookup AccelClass from opt_name. Returns NULL if not found */
> +AccelClass *accel_find(const char *opt_name)
> +{
> + char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
> + AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
> + g_free(class_name);
> + return ac;
> +}
> +
> +static void register_accel_types(void)
> +{
> + type_register_static(&accel_type);
> +}
> +
> +type_init(register_accel_types);
> diff --git a/accel/accel.c b/accel/accel-softmmu.c
> similarity index 75%
> rename from accel/accel.c
> rename to accel/accel-softmmu.c
> index cb555e3b06..f89da8f9d1 100644
> --- a/accel/accel.c
> +++ b/accel/accel-softmmu.c
> @@ -1,5 +1,5 @@
> /*
> - * QEMU System Emulator, accelerator interfaces
> + * QEMU accel class, system emulation components
> *
> * Copyright (c) 2003-2008 Fabrice Bellard
> * Copyright (c) 2014 Red Hat Inc.
> @@ -24,28 +24,12 @@
> */
>
> #include "qemu/osdep.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "hw/boards.h"
> #include "sysemu/arch_init.h"
> #include "sysemu/sysemu.h"
> #include "qom/object.h"
>
> -static const TypeInfo accel_type = {
> - .name = TYPE_ACCEL,
> - .parent = TYPE_OBJECT,
> - .class_size = sizeof(AccelClass),
> - .instance_size = sizeof(AccelState),
> -};
> -
> -/* Lookup AccelClass from opt_name. Returns NULL if not found */
> -AccelClass *accel_find(const char *opt_name)
> -{
> - char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
> - AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
> - g_free(class_name);
> - return ac;
> -}
> -
> int accel_init_machine(AccelState *accel, MachineState *ms)
> {
> AccelClass *acc = ACCEL_GET_CLASS(accel);
> @@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms)
> acc->setup_post(ms, accel);
> }
> }
> -
> -static void register_accel_types(void)
> -{
> - type_register_static(&accel_type);
> -}
> -
> -type_init(register_accel_types);
> diff --git a/accel/accel-user.c b/accel/accel-user.c
> new file mode 100644
> index 0000000000..26bdda6236
> --- /dev/null
> +++ b/accel/accel-user.c
> @@ -0,0 +1,24 @@
> +/*
> + * QEMU accel class, user-mode components
> + *
> + * Copyright 2020 SUSE LLC
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/accel.h"
> +
> +AccelState *current_accel(void)
> +{
> + static AccelState *accel;
> +
> + if (!accel) {
> + AccelClass *ac = accel_find("tcg");
> +
> + g_assert(ac != NULL);
> + accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac)));
> + }
> + return accel;
> +}
> diff --git a/accel/meson.build b/accel/meson.build
> index b26cca227a..b44ba30c86 100644
> --- a/accel/meson.build
> +++ b/accel/meson.build
> @@ -1,4 +1,6 @@
> -softmmu_ss.add(files('accel.c'))
> +specific_ss.add(files('accel-common.c'))
> +softmmu_ss.add(files('accel-softmmu.c'))
> +user_ss.add(files('accel-user.c'))
>
> subdir('qtest')
> subdir('kvm')
> diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
> index b282cea5cf..b4e731cb2b 100644
> --- a/accel/qtest/qtest.c
> +++ b/accel/qtest/qtest.c
> @@ -17,7 +17,7 @@
> #include "qemu/module.h"
> #include "qemu/option.h"
> #include "qemu/config-file.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/qtest.h"
> #include "sysemu/cpus.h"
> #include "sysemu/cpu-timers.h"
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index f39aab0a0c..424d9bb1fc 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -1,5 +1,6 @@
> tcg_ss = ss.source_set()
> tcg_ss.add(files(
> + 'tcg-all.c',
> 'cpu-exec-common.c',
> 'cpu-exec.c',
> 'tcg-runtime-gvec.c',
> @@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
> specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
>
> specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
> - 'tcg-all.c',
> 'cputlb.c',
> 'tcg-cpus.c',
> 'tcg-cpus-mttcg.c',
> diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
> index 1ac0b76515..dcbc6970da 100644
> --- a/accel/tcg/tcg-all.c
> +++ b/accel/tcg/tcg-all.c
> @@ -30,9 +30,12 @@
> #include "tcg/tcg.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> -#include "hw/boards.h"
> +#include "qemu/accel.h"
> #include "qapi/qapi-builtin-visit.h"
> +
> +#ifndef CONFIG_USER_ONLY
> #include "tcg-cpus.h"
> +#endif /* CONFIG_USER_ONLY */
>
> struct TCGState {
> AccelState parent_obj;
> @@ -110,6 +113,7 @@ static int tcg_init(MachineState *ms)
> */
> tcg_region_init();
>
> +#ifndef CONFIG_USER_ONLY
> if (mttcg_enabled) {
> cpus_register_accel(&tcg_cpus_mttcg);
> } else if (icount_enabled()) {
> @@ -117,6 +121,7 @@ static int tcg_init(MachineState *ms)
> } else {
> cpus_register_accel(&tcg_cpus_rr);
> }
> +#endif /* CONFIG_USER_ONLY */
> return 0;
> }
>
> diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
> index 878a4089d9..594aaf6b49 100644
> --- a/accel/xen/xen-all.c
> +++ b/accel/xen/xen-all.c
> @@ -15,7 +15,7 @@
> #include "hw/xen/xen-legacy-backend.h"
> #include "hw/xen/xen_pt.h"
> #include "chardev/char.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/cpus.h"
> #include "sysemu/xen.h"
> #include "sysemu/runstate.h"
> diff --git a/bsd-user/main.c b/bsd-user/main.c
> index 0a918e8f74..ec1f9d80a4 100644
> --- a/bsd-user/main.c
> +++ b/bsd-user/main.c
> @@ -20,6 +20,7 @@
> #include "qemu/osdep.h"
> #include "qemu-common.h"
> #include "qemu/units.h"
> +#include "qemu/accel.h"
> #include "sysemu/tcg.h"
> #include "qemu-version.h"
> #include <machine/trap.h>
> @@ -908,8 +909,11 @@ int main(int argc, char **argv)
> }
>
> /* init tcg before creating CPUs and to get qemu_host_page_size */
> - tcg_exec_init(0);
> + {
> + AccelClass *ac = ACCEL_GET_CLASS(current_accel());
>
> + ac->init_machine(NULL);
> + }
> cpu_type = parse_cpu_option(cpu_model);
> cpu = cpu_create(cpu_type);
> env = cpu->env_ptr;
> @@ -988,7 +992,6 @@ int main(int argc, char **argv)
> generating the prologue until now so that the prologue can take
> the real value of GUEST_BASE into account. */
> tcg_prologue_init(tcg_ctx);
> - tcg_region_init();
>
> /* build Task State */
> memset(ts, 0, sizeof(TaskState));
> diff --git a/include/hw/boards.h b/include/hw/boards.h
> index a49e3a6b44..b754504afe 100644
> --- a/include/hw/boards.h
> +++ b/include/hw/boards.h
> @@ -6,7 +6,7 @@
> #include "exec/memory.h"
> #include "sysemu/hostmem.h"
> #include "sysemu/blockdev.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "qapi/qapi-types-machine.h"
> #include "qemu/module.h"
> #include "qom/object.h"
> diff --git a/include/sysemu/accel.h b/include/qemu/accel.h
> similarity index 95%
> rename from include/sysemu/accel.h
> rename to include/qemu/accel.h
> index e08b8ab8fa..fac4a18703 100644
> --- a/include/sysemu/accel.h
> +++ b/include/qemu/accel.h
> @@ -20,8 +20,8 @@
> * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> * THE SOFTWARE.
> */
> -#ifndef HW_ACCEL_H
> -#define HW_ACCEL_H
> +#ifndef QEMU_ACCEL_H
> +#define QEMU_ACCEL_H
>
> #include "qom/object.h"
> #include "exec/hwaddr.h"
> @@ -37,8 +37,8 @@ typedef struct AccelClass {
> /*< public >*/
>
> const char *name;
> -#ifndef CONFIG_USER_ONLY
> int (*init_machine)(MachineState *ms);
> +#ifndef CONFIG_USER_ONLY
> void (*setup_post)(MachineState *ms, AccelState *accel);
> bool (*has_memory)(MachineState *ms, AddressSpace *as,
> hwaddr start_addr, hwaddr size);
> @@ -67,11 +67,13 @@ typedef struct AccelClass {
> OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL)
>
> AccelClass *accel_find(const char *opt_name);
> +AccelState *current_accel(void);
> +
> +#ifndef CONFIG_USER_ONLY
> int accel_init_machine(AccelState *accel, MachineState *ms);
>
> /* Called just before os_setup_post (ie just before drop OS privs) */
> void accel_setup_post(MachineState *ms);
> +#endif /* !CONFIG_USER_ONLY */
>
> -AccelState *current_accel(void);
> -
> -#endif
> +#endif /* QEMU_ACCEL_H */
> diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
> index f893768df9..c98636bc81 100644
> --- a/include/sysemu/hvf.h
> +++ b/include/sysemu/hvf.h
> @@ -13,7 +13,7 @@
> #ifndef HVF_H
> #define HVF_H
>
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "qom/object.h"
>
> #ifdef CONFIG_HVF
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index bb5d5cf497..739682f3c3 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -17,7 +17,7 @@
> #include "qemu/queue.h"
> #include "hw/core/cpu.h"
> #include "exec/memattrs.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "qom/object.h"
>
> #ifdef NEED_CPU_H
> diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
> index 65740806da..ccb8869f01 100644
> --- a/include/sysemu/kvm_int.h
> +++ b/include/sysemu/kvm_int.h
> @@ -10,7 +10,7 @@
> #define QEMU_KVM_INT_H
>
> #include "exec/memory.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/kvm.h"
>
> typedef struct KVMSlot
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 24d1eb73ad..1825d2b835 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -20,6 +20,7 @@
> #include "qemu/osdep.h"
> #include "qemu-common.h"
> #include "qemu/units.h"
> +#include "qemu/accel.h"
> #include "sysemu/tcg.h"
> #include "qemu-version.h"
> #include <sys/syscall.h>
> @@ -703,8 +704,11 @@ int main(int argc, char **argv, char **envp)
> cpu_type = parse_cpu_option(cpu_model);
>
> /* init tcg before creating CPUs and to get qemu_host_page_size */
> - tcg_exec_init(0);
> + {
> + AccelClass *ac = ACCEL_GET_CLASS(current_accel());
>
> + ac->init_machine(NULL);
> + }
> cpu = cpu_create(cpu_type);
> env = cpu->env_ptr;
> cpu_reset(cpu);
> @@ -846,7 +850,6 @@ int main(int argc, char **argv, char **envp)
> generating the prologue until now so that the prologue can take
> the real value of GUEST_BASE into account. */
> tcg_prologue_init(tcg_ctx);
> - tcg_region_init();
>
> target_cpu_copy_regs(env, regs);
>
> diff --git a/softmmu/memory.c b/softmmu/memory.c
> index aa393f1bb0..92c8b4fc1f 100644
> --- a/softmmu/memory.c
> +++ b/softmmu/memory.c
> @@ -32,7 +32,7 @@
> #include "sysemu/kvm.h"
> #include "sysemu/runstate.h"
> #include "sysemu/tcg.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "hw/boards.h"
> #include "migration/vmstate.h"
>
> diff --git a/softmmu/qtest.c b/softmmu/qtest.c
> index 7965dc9a16..130c366615 100644
> --- a/softmmu/qtest.c
> +++ b/softmmu/qtest.c
> @@ -20,7 +20,7 @@
> #include "exec/ioport.h"
> #include "exec/memory.h"
> #include "hw/irq.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/cpu-timers.h"
> #include "qemu/config-file.h"
> #include "qemu/option.h"
> diff --git a/softmmu/vl.c b/softmmu/vl.c
> index e6e0ad5a92..bc20c526d2 100644
> --- a/softmmu/vl.c
> +++ b/softmmu/vl.c
> @@ -40,7 +40,7 @@
>
> #include "qemu/error-report.h"
> #include "qemu/sockets.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "hw/usb.h"
> #include "hw/isa/isa.h"
> #include "hw/scsi/scsi.h"
> diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
> index fecfe8cd6e..d7f4bb44a7 100644
> --- a/target/i386/hax/hax-all.c
> +++ b/target/i386/hax/hax-all.c
> @@ -28,7 +28,7 @@
> #include "exec/address-spaces.h"
>
> #include "qemu-common.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> #include "hw/boards.h"
> diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
> index e0edffd077..50b914fd67 100644
> --- a/target/i386/hvf/hvf-i386.h
> +++ b/target/i386/hvf/hvf-i386.h
> @@ -16,7 +16,7 @@
> #ifndef HVF_I386_H
> #define HVF_I386_H
>
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/hvf.h"
> #include "cpu.h"
> #include "x86.h"
> diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
> index ed9356565c..ffc9efa40f 100644
> --- a/target/i386/hvf/hvf.c
> +++ b/target/i386/hvf/hvf.c
> @@ -69,7 +69,7 @@
> #include "exec/address-spaces.h"
> #include "hw/i386/apic_internal.h"
> #include "qemu/main-loop.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "target/i386/cpu.h"
>
> #include "hvf-cpus.h"
> diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
> index 6f04478b3a..d66dfd7669 100644
> --- a/target/i386/hvf/x86_task.c
> +++ b/target/i386/hvf/x86_task.c
> @@ -28,7 +28,7 @@
>
> #include "hw/i386/apic_internal.h"
> #include "qemu/main-loop.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "target/i386/cpu.h"
>
> // TODO: taskswitch handling
> diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
> index f4f3e33eac..ee6b606194 100644
> --- a/target/i386/whpx/whpx-all.c
> +++ b/target/i386/whpx/whpx-all.c
> @@ -13,7 +13,7 @@
> #include "exec/address-spaces.h"
> #include "exec/ioport.h"
> #include "qemu-common.h"
> -#include "sysemu/accel.h"
> +#include "qemu/accel.h"
> #include "sysemu/whpx.h"
> #include "sysemu/cpus.h"
> #include "sysemu/runstate.h"
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2021-01-11 16:13 ` Claudio Fontana
2021-01-11 18:08 ` Claudio Fontana
@ 2021-01-11 22:35 ` Eduardo Habkost
2021-01-11 23:35 ` Claudio Fontana
1 sibling, 1 reply; 43+ messages in thread
From: Eduardo Habkost @ 2021-01-11 22:35 UTC (permalink / raw)
To: Claudio Fontana
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Mon, Jan 11, 2021 at 05:13:27PM +0100, Claudio Fontana wrote:
> Happy new year,
Hi!
>
> picking up this topic again, i am looking at at now a different aspect of this problem, of setting the right tcg ops for the right cpu class.
>
> This issue I am highlighting is present because different targets behave differently in this regard.
>
> Ie, we have targets for which we always initialize all cpu classes, as a result of different machine definitions.
>
> This is the case of arm, for example where we end up with backtraces like:
>
> arm_v7m_class_init
> type_initialize
> object_class_foreach_tramp
> g_hash_table_foreach ()
> object_class_foreach
> object_class_get_list
> select_machine ()
> qemu_init
> main
>
> with the arm_v7m_class_init called even if we are just going to use an aarch64 cpu (so the class initializer for arm_v7m is called even for unused cpus classes),
>
> while in other cases we have the target explicitly relying on the fact that only the right cpu class is initialized, for example in cris we have code like:
This shouldn't matter at all, because class_init is not supposed
to have any side effects outside the corresponding ObjectClass
struct.
So, I don't understand what you mean below:
>
> target/cris/cpu.c:
>
> static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
> {
> CPUClass *cc = CPU_CLASS(oc);
> CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
>
> ccc->vr = 9;
> cc->do_interrupt = crisv10_cpu_do_interrupt;
> cc->gdb_read_register = crisv10_cpu_gdb_read_register;
> cc->tcg_initialize = cris_initialize_crisv10_tcg;
> }
>
> where the class initialization of the cpu is explicitly setting the methods of CPUClass, therefore implicitly relying on the fact that no other class initializer screws things up.
I don't see the problem here. Having all other class
initializers being called should be completely OK, because each
class has its own ObjectClass struct.
>
> Given this context, which one of these methods is "right"?
> Should we rework things so that only used cpu classes are actually initialized?
This option wouldn't make sense. class_init is supposed to be
called on demand on class lookup, and can be triggered by
object_class_get_list(), object_class_by_name(), or similar
functions. This is by design.
> Or should we maybe not do these settings in cpu class_init at all, but rather at cpu initfn time, or at cpu realize time?
If you are talking about initializing
ObjectClass/CPUClass/...Class fields, they can always be safely
initialized in class_init.
If you are talking about touching anything outside the class
struct (like in CPUState), class_init is not the right place to
do it.
--
Eduardo
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass
2021-01-11 22:35 ` Eduardo Habkost
@ 2021-01-11 23:35 ` Claudio Fontana
0 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2021-01-11 23:35 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Paul Durrant, Jason Wang, qemu-devel, Peter Xu, haxm-team,
Colin Xu, Olaf Hering, Stefano Stabellini, Bruce Rogers,
Emilio G . Cota, Anthony Perard, Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 1/11/21 11:35 PM, Eduardo Habkost wrote:
> On Mon, Jan 11, 2021 at 05:13:27PM +0100, Claudio Fontana wrote:
>> Happy new year,
>
> Hi!
>
>>
>> picking up this topic again, i am looking at at now a different aspect of this problem, of setting the right tcg ops for the right cpu class.
>>
>> This issue I am highlighting is present because different targets behave differently in this regard.
>>
>> Ie, we have targets for which we always initialize all cpu classes, as a result of different machine definitions.
>>
>> This is the case of arm, for example where we end up with backtraces like:
>>
>> arm_v7m_class_init
>> type_initialize
>> object_class_foreach_tramp
>> g_hash_table_foreach ()
>> object_class_foreach
>> object_class_get_list
>> select_machine ()
>> qemu_init
>> main
>>
>> with the arm_v7m_class_init called even if we are just going to use an aarch64 cpu (so the class initializer for arm_v7m is called even for unused cpus classes),
>>
>> while in other cases we have the target explicitly relying on the fact that only the right cpu class is initialized, for example in cris we have code like:
>
> This shouldn't matter at all, because class_init is not supposed
> to have any side effects outside the corresponding ObjectClass
> struct.
>
> So, I don't understand what you mean below:
>
>>
>> target/cris/cpu.c:
>>
>> static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
>> {
>> CPUClass *cc = CPU_CLASS(oc);
>> CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
>>
>> ccc->vr = 9;
>> cc->do_interrupt = crisv10_cpu_do_interrupt;
>> cc->gdb_read_register = crisv10_cpu_gdb_read_register;
>> cc->tcg_initialize = cris_initialize_crisv10_tcg;
>> }
>>
>> where the class initialization of the cpu is explicitly setting the methods of CPUClass, therefore implicitly relying on the fact that no other class initializer screws things up.
>
> I don't see the problem here. Having all other class
> initializers being called should be completely OK, because each
> class has its own ObjectClass struct.
>
>
>>
>> Given this context, which one of these methods is "right"?
>> Should we rework things so that only used cpu classes are actually initialized?
>
> This option wouldn't make sense. class_init is supposed to be
> called on demand on class lookup, and can be triggered by
> object_class_get_list(), object_class_by_name(), or similar
> functions. This is by design.
>
>
>> Or should we maybe not do these settings in cpu class_init at all, but rather at cpu initfn time, or at cpu realize time?
>
> If you are talking about initializing
> ObjectClass/CPUClass/...Class fields, they can always be safely
> initialized in class_init.
Ok, so I can initialize the CPUClass fields for the tcg ops in the CPUClass subclass class inits safely..
Thanks for clearing this up!
Claudio
>
> If you are talking about touching anything outside the class
> struct (like in CPUState), class_init is not the right place to
> do it.
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode
2021-01-11 18:43 ` Claudio Fontana
@ 2021-01-12 9:23 ` Claudio Fontana
0 siblings, 0 replies; 43+ messages in thread
From: Claudio Fontana @ 2021-01-12 9:23 UTC (permalink / raw)
To: Richard Henderson
Cc: Thomas Huth, Eduardo Habkost, Philippe Mathieu-Daudé,
qemu-devel, Paolo Bonzini, Alex Bennee
On 1/11/21 7:43 PM, Claudio Fontana wrote:
> Hi Richard,
>
> happy new year,
>
> this change of mine breaks with --enable-debug, after your changes related to "splitrw" in tcg/,
> I am a bit at a loss at what could be going wrong.. any hints?
>
> I am getting assertion failures with --enable-debug in make check-tcg,
>
> in particular in tcg/tcg.c:768
>
> #ifdef CONFIG_DEBUG_TCG
> const void *tcg_splitwx_to_rx(void *rw)
> {
> /* Pass NULL pointers unchanged. */
> if (rw) {
> g_assert(in_code_gen_buffer(rw)); /* <=== HERE */
> rw += tcg_splitwx_diff;
> }
> return rw;
> }
>
> any hints?
Nevermind, I now noticed the new parameter, which needs to be false for USER MODE.
Thanks,
Claudio
>
> Thanks,
>
> Claudio
>
>
> On 11/26/20 11:32 PM, Claudio Fontana wrote:
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> ---
>> MAINTAINERS | 2 +-
>> accel/accel-common.c | 50 ++++++++++++++++++++++++++++++
>> accel/{accel.c => accel-softmmu.c} | 27 ++--------------
>> accel/accel-user.c | 24 ++++++++++++++
>> accel/meson.build | 4 ++-
>> accel/qtest/qtest.c | 2 +-
>> accel/tcg/meson.build | 2 +-
>> accel/tcg/tcg-all.c | 7 ++++-
>> accel/xen/xen-all.c | 2 +-
>> bsd-user/main.c | 7 +++--
>> include/hw/boards.h | 2 +-
>> include/{sysemu => qemu}/accel.h | 14 +++++----
>> include/sysemu/hvf.h | 2 +-
>> include/sysemu/kvm.h | 2 +-
>> include/sysemu/kvm_int.h | 2 +-
>> linux-user/main.c | 7 +++--
>> softmmu/memory.c | 2 +-
>> softmmu/qtest.c | 2 +-
>> softmmu/vl.c | 2 +-
>> target/i386/hax/hax-all.c | 2 +-
>> target/i386/hvf/hvf-i386.h | 2 +-
>> target/i386/hvf/hvf.c | 2 +-
>> target/i386/hvf/x86_task.c | 2 +-
>> target/i386/whpx/whpx-all.c | 2 +-
>> 24 files changed, 119 insertions(+), 53 deletions(-)
>> create mode 100644 accel/accel-common.c
>> rename accel/{accel.c => accel-softmmu.c} (75%)
>> create mode 100644 accel/accel-user.c
>> rename include/{sysemu => qemu}/accel.h (95%)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index e892dd2220..d7c212843c 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -433,7 +433,7 @@ Overall
>> M: Richard Henderson <richard.henderson@linaro.org>
>> R: Paolo Bonzini <pbonzini@redhat.com>
>> S: Maintained
>> -F: include/sysemu/accel.h
>> +F: include/qemu/accel.h
>> F: accel/accel.c
>> F: accel/Makefile.objs
>> F: accel/stubs/Makefile.objs
>> diff --git a/accel/accel-common.c b/accel/accel-common.c
>> new file mode 100644
>> index 0000000000..ddec8cb5ae
>> --- /dev/null
>> +++ b/accel/accel-common.c
>> @@ -0,0 +1,50 @@
>> +/*
>> + * QEMU accel class, components common to system emulation and user mode
>> + *
>> + * Copyright (c) 2003-2008 Fabrice Bellard
>> + * Copyright (c) 2014 Red Hat Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/accel.h"
>> +
>> +static const TypeInfo accel_type = {
>> + .name = TYPE_ACCEL,
>> + .parent = TYPE_OBJECT,
>> + .class_size = sizeof(AccelClass),
>> + .instance_size = sizeof(AccelState),
>> +};
>> +
>> +/* Lookup AccelClass from opt_name. Returns NULL if not found */
>> +AccelClass *accel_find(const char *opt_name)
>> +{
>> + char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
>> + AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
>> + g_free(class_name);
>> + return ac;
>> +}
>> +
>> +static void register_accel_types(void)
>> +{
>> + type_register_static(&accel_type);
>> +}
>> +
>> +type_init(register_accel_types);
>> diff --git a/accel/accel.c b/accel/accel-softmmu.c
>> similarity index 75%
>> rename from accel/accel.c
>> rename to accel/accel-softmmu.c
>> index cb555e3b06..f89da8f9d1 100644
>> --- a/accel/accel.c
>> +++ b/accel/accel-softmmu.c
>> @@ -1,5 +1,5 @@
>> /*
>> - * QEMU System Emulator, accelerator interfaces
>> + * QEMU accel class, system emulation components
>> *
>> * Copyright (c) 2003-2008 Fabrice Bellard
>> * Copyright (c) 2014 Red Hat Inc.
>> @@ -24,28 +24,12 @@
>> */
>>
>> #include "qemu/osdep.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "hw/boards.h"
>> #include "sysemu/arch_init.h"
>> #include "sysemu/sysemu.h"
>> #include "qom/object.h"
>>
>> -static const TypeInfo accel_type = {
>> - .name = TYPE_ACCEL,
>> - .parent = TYPE_OBJECT,
>> - .class_size = sizeof(AccelClass),
>> - .instance_size = sizeof(AccelState),
>> -};
>> -
>> -/* Lookup AccelClass from opt_name. Returns NULL if not found */
>> -AccelClass *accel_find(const char *opt_name)
>> -{
>> - char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
>> - AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
>> - g_free(class_name);
>> - return ac;
>> -}
>> -
>> int accel_init_machine(AccelState *accel, MachineState *ms)
>> {
>> AccelClass *acc = ACCEL_GET_CLASS(accel);
>> @@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms)
>> acc->setup_post(ms, accel);
>> }
>> }
>> -
>> -static void register_accel_types(void)
>> -{
>> - type_register_static(&accel_type);
>> -}
>> -
>> -type_init(register_accel_types);
>> diff --git a/accel/accel-user.c b/accel/accel-user.c
>> new file mode 100644
>> index 0000000000..26bdda6236
>> --- /dev/null
>> +++ b/accel/accel-user.c
>> @@ -0,0 +1,24 @@
>> +/*
>> + * QEMU accel class, user-mode components
>> + *
>> + * Copyright 2020 SUSE LLC
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/accel.h"
>> +
>> +AccelState *current_accel(void)
>> +{
>> + static AccelState *accel;
>> +
>> + if (!accel) {
>> + AccelClass *ac = accel_find("tcg");
>> +
>> + g_assert(ac != NULL);
>> + accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac)));
>> + }
>> + return accel;
>> +}
>> diff --git a/accel/meson.build b/accel/meson.build
>> index b26cca227a..b44ba30c86 100644
>> --- a/accel/meson.build
>> +++ b/accel/meson.build
>> @@ -1,4 +1,6 @@
>> -softmmu_ss.add(files('accel.c'))
>> +specific_ss.add(files('accel-common.c'))
>> +softmmu_ss.add(files('accel-softmmu.c'))
>> +user_ss.add(files('accel-user.c'))
>>
>> subdir('qtest')
>> subdir('kvm')
>> diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
>> index b282cea5cf..b4e731cb2b 100644
>> --- a/accel/qtest/qtest.c
>> +++ b/accel/qtest/qtest.c
>> @@ -17,7 +17,7 @@
>> #include "qemu/module.h"
>> #include "qemu/option.h"
>> #include "qemu/config-file.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/qtest.h"
>> #include "sysemu/cpus.h"
>> #include "sysemu/cpu-timers.h"
>> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
>> index f39aab0a0c..424d9bb1fc 100644
>> --- a/accel/tcg/meson.build
>> +++ b/accel/tcg/meson.build
>> @@ -1,5 +1,6 @@
>> tcg_ss = ss.source_set()
>> tcg_ss.add(files(
>> + 'tcg-all.c',
>> 'cpu-exec-common.c',
>> 'cpu-exec.c',
>> 'tcg-runtime-gvec.c',
>> @@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
>> specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
>>
>> specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
>> - 'tcg-all.c',
>> 'cputlb.c',
>> 'tcg-cpus.c',
>> 'tcg-cpus-mttcg.c',
>> diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
>> index 1ac0b76515..dcbc6970da 100644
>> --- a/accel/tcg/tcg-all.c
>> +++ b/accel/tcg/tcg-all.c
>> @@ -30,9 +30,12 @@
>> #include "tcg/tcg.h"
>> #include "qapi/error.h"
>> #include "qemu/error-report.h"
>> -#include "hw/boards.h"
>> +#include "qemu/accel.h"
>> #include "qapi/qapi-builtin-visit.h"
>> +
>> +#ifndef CONFIG_USER_ONLY
>> #include "tcg-cpus.h"
>> +#endif /* CONFIG_USER_ONLY */
>>
>> struct TCGState {
>> AccelState parent_obj;
>> @@ -110,6 +113,7 @@ static int tcg_init(MachineState *ms)
>> */
>> tcg_region_init();
>>
>> +#ifndef CONFIG_USER_ONLY
>> if (mttcg_enabled) {
>> cpus_register_accel(&tcg_cpus_mttcg);
>> } else if (icount_enabled()) {
>> @@ -117,6 +121,7 @@ static int tcg_init(MachineState *ms)
>> } else {
>> cpus_register_accel(&tcg_cpus_rr);
>> }
>> +#endif /* CONFIG_USER_ONLY */
>> return 0;
>> }
>>
>> diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
>> index 878a4089d9..594aaf6b49 100644
>> --- a/accel/xen/xen-all.c
>> +++ b/accel/xen/xen-all.c
>> @@ -15,7 +15,7 @@
>> #include "hw/xen/xen-legacy-backend.h"
>> #include "hw/xen/xen_pt.h"
>> #include "chardev/char.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/cpus.h"
>> #include "sysemu/xen.h"
>> #include "sysemu/runstate.h"
>> diff --git a/bsd-user/main.c b/bsd-user/main.c
>> index 0a918e8f74..ec1f9d80a4 100644
>> --- a/bsd-user/main.c
>> +++ b/bsd-user/main.c
>> @@ -20,6 +20,7 @@
>> #include "qemu/osdep.h"
>> #include "qemu-common.h"
>> #include "qemu/units.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/tcg.h"
>> #include "qemu-version.h"
>> #include <machine/trap.h>
>> @@ -908,8 +909,11 @@ int main(int argc, char **argv)
>> }
>>
>> /* init tcg before creating CPUs and to get qemu_host_page_size */
>> - tcg_exec_init(0);
>> + {
>> + AccelClass *ac = ACCEL_GET_CLASS(current_accel());
>>
>> + ac->init_machine(NULL);
>> + }
>> cpu_type = parse_cpu_option(cpu_model);
>> cpu = cpu_create(cpu_type);
>> env = cpu->env_ptr;
>> @@ -988,7 +992,6 @@ int main(int argc, char **argv)
>> generating the prologue until now so that the prologue can take
>> the real value of GUEST_BASE into account. */
>> tcg_prologue_init(tcg_ctx);
>> - tcg_region_init();
>>
>> /* build Task State */
>> memset(ts, 0, sizeof(TaskState));
>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>> index a49e3a6b44..b754504afe 100644
>> --- a/include/hw/boards.h
>> +++ b/include/hw/boards.h
>> @@ -6,7 +6,7 @@
>> #include "exec/memory.h"
>> #include "sysemu/hostmem.h"
>> #include "sysemu/blockdev.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "qapi/qapi-types-machine.h"
>> #include "qemu/module.h"
>> #include "qom/object.h"
>> diff --git a/include/sysemu/accel.h b/include/qemu/accel.h
>> similarity index 95%
>> rename from include/sysemu/accel.h
>> rename to include/qemu/accel.h
>> index e08b8ab8fa..fac4a18703 100644
>> --- a/include/sysemu/accel.h
>> +++ b/include/qemu/accel.h
>> @@ -20,8 +20,8 @@
>> * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> * THE SOFTWARE.
>> */
>> -#ifndef HW_ACCEL_H
>> -#define HW_ACCEL_H
>> +#ifndef QEMU_ACCEL_H
>> +#define QEMU_ACCEL_H
>>
>> #include "qom/object.h"
>> #include "exec/hwaddr.h"
>> @@ -37,8 +37,8 @@ typedef struct AccelClass {
>> /*< public >*/
>>
>> const char *name;
>> -#ifndef CONFIG_USER_ONLY
>> int (*init_machine)(MachineState *ms);
>> +#ifndef CONFIG_USER_ONLY
>> void (*setup_post)(MachineState *ms, AccelState *accel);
>> bool (*has_memory)(MachineState *ms, AddressSpace *as,
>> hwaddr start_addr, hwaddr size);
>> @@ -67,11 +67,13 @@ typedef struct AccelClass {
>> OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL)
>>
>> AccelClass *accel_find(const char *opt_name);
>> +AccelState *current_accel(void);
>> +
>> +#ifndef CONFIG_USER_ONLY
>> int accel_init_machine(AccelState *accel, MachineState *ms);
>>
>> /* Called just before os_setup_post (ie just before drop OS privs) */
>> void accel_setup_post(MachineState *ms);
>> +#endif /* !CONFIG_USER_ONLY */
>>
>> -AccelState *current_accel(void);
>> -
>> -#endif
>> +#endif /* QEMU_ACCEL_H */
>> diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
>> index f893768df9..c98636bc81 100644
>> --- a/include/sysemu/hvf.h
>> +++ b/include/sysemu/hvf.h
>> @@ -13,7 +13,7 @@
>> #ifndef HVF_H
>> #define HVF_H
>>
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "qom/object.h"
>>
>> #ifdef CONFIG_HVF
>> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>> index bb5d5cf497..739682f3c3 100644
>> --- a/include/sysemu/kvm.h
>> +++ b/include/sysemu/kvm.h
>> @@ -17,7 +17,7 @@
>> #include "qemu/queue.h"
>> #include "hw/core/cpu.h"
>> #include "exec/memattrs.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "qom/object.h"
>>
>> #ifdef NEED_CPU_H
>> diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
>> index 65740806da..ccb8869f01 100644
>> --- a/include/sysemu/kvm_int.h
>> +++ b/include/sysemu/kvm_int.h
>> @@ -10,7 +10,7 @@
>> #define QEMU_KVM_INT_H
>>
>> #include "exec/memory.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/kvm.h"
>>
>> typedef struct KVMSlot
>> diff --git a/linux-user/main.c b/linux-user/main.c
>> index 24d1eb73ad..1825d2b835 100644
>> --- a/linux-user/main.c
>> +++ b/linux-user/main.c
>> @@ -20,6 +20,7 @@
>> #include "qemu/osdep.h"
>> #include "qemu-common.h"
>> #include "qemu/units.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/tcg.h"
>> #include "qemu-version.h"
>> #include <sys/syscall.h>
>> @@ -703,8 +704,11 @@ int main(int argc, char **argv, char **envp)
>> cpu_type = parse_cpu_option(cpu_model);
>>
>> /* init tcg before creating CPUs and to get qemu_host_page_size */
>> - tcg_exec_init(0);
>> + {
>> + AccelClass *ac = ACCEL_GET_CLASS(current_accel());
>>
>> + ac->init_machine(NULL);
>> + }
>> cpu = cpu_create(cpu_type);
>> env = cpu->env_ptr;
>> cpu_reset(cpu);
>> @@ -846,7 +850,6 @@ int main(int argc, char **argv, char **envp)
>> generating the prologue until now so that the prologue can take
>> the real value of GUEST_BASE into account. */
>> tcg_prologue_init(tcg_ctx);
>> - tcg_region_init();
>>
>> target_cpu_copy_regs(env, regs);
>>
>> diff --git a/softmmu/memory.c b/softmmu/memory.c
>> index aa393f1bb0..92c8b4fc1f 100644
>> --- a/softmmu/memory.c
>> +++ b/softmmu/memory.c
>> @@ -32,7 +32,7 @@
>> #include "sysemu/kvm.h"
>> #include "sysemu/runstate.h"
>> #include "sysemu/tcg.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "hw/boards.h"
>> #include "migration/vmstate.h"
>>
>> diff --git a/softmmu/qtest.c b/softmmu/qtest.c
>> index 7965dc9a16..130c366615 100644
>> --- a/softmmu/qtest.c
>> +++ b/softmmu/qtest.c
>> @@ -20,7 +20,7 @@
>> #include "exec/ioport.h"
>> #include "exec/memory.h"
>> #include "hw/irq.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/cpu-timers.h"
>> #include "qemu/config-file.h"
>> #include "qemu/option.h"
>> diff --git a/softmmu/vl.c b/softmmu/vl.c
>> index e6e0ad5a92..bc20c526d2 100644
>> --- a/softmmu/vl.c
>> +++ b/softmmu/vl.c
>> @@ -40,7 +40,7 @@
>>
>> #include "qemu/error-report.h"
>> #include "qemu/sockets.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "hw/usb.h"
>> #include "hw/isa/isa.h"
>> #include "hw/scsi/scsi.h"
>> diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
>> index fecfe8cd6e..d7f4bb44a7 100644
>> --- a/target/i386/hax/hax-all.c
>> +++ b/target/i386/hax/hax-all.c
>> @@ -28,7 +28,7 @@
>> #include "exec/address-spaces.h"
>>
>> #include "qemu-common.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/reset.h"
>> #include "sysemu/runstate.h"
>> #include "hw/boards.h"
>> diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
>> index e0edffd077..50b914fd67 100644
>> --- a/target/i386/hvf/hvf-i386.h
>> +++ b/target/i386/hvf/hvf-i386.h
>> @@ -16,7 +16,7 @@
>> #ifndef HVF_I386_H
>> #define HVF_I386_H
>>
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/hvf.h"
>> #include "cpu.h"
>> #include "x86.h"
>> diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
>> index ed9356565c..ffc9efa40f 100644
>> --- a/target/i386/hvf/hvf.c
>> +++ b/target/i386/hvf/hvf.c
>> @@ -69,7 +69,7 @@
>> #include "exec/address-spaces.h"
>> #include "hw/i386/apic_internal.h"
>> #include "qemu/main-loop.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "target/i386/cpu.h"
>>
>> #include "hvf-cpus.h"
>> diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
>> index 6f04478b3a..d66dfd7669 100644
>> --- a/target/i386/hvf/x86_task.c
>> +++ b/target/i386/hvf/x86_task.c
>> @@ -28,7 +28,7 @@
>>
>> #include "hw/i386/apic_internal.h"
>> #include "qemu/main-loop.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "target/i386/cpu.h"
>>
>> // TODO: taskswitch handling
>> diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
>> index f4f3e33eac..ee6b606194 100644
>> --- a/target/i386/whpx/whpx-all.c
>> +++ b/target/i386/whpx/whpx-all.c
>> @@ -13,7 +13,7 @@
>> #include "exec/address-spaces.h"
>> #include "exec/ioport.h"
>> #include "qemu-common.h"
>> -#include "sysemu/accel.h"
>> +#include "qemu/accel.h"
>> #include "sysemu/whpx.h"
>> #include "sysemu/cpus.h"
>> #include "sysemu/runstate.h"
>>
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2021-01-12 9:26 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-26 22:32 [RFC v6 00/11] i386 cleanup Claudio Fontana
2020-11-26 22:32 ` [RFC v6 01/11] i386: move kvm accel files into kvm/ Claudio Fontana
2020-11-26 22:32 ` [RFC v6 02/11] i386: move whpx accel files into whpx/ Claudio Fontana
2020-11-26 22:32 ` [RFC v6 03/11] i386: move hax accel files into hax/ Claudio Fontana
2020-11-26 22:32 ` [RFC v6 04/11] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Claudio Fontana
2020-11-26 22:32 ` [RFC v6 05/11] i386: move TCG accel files into tcg/ Claudio Fontana
2020-11-26 22:32 ` [RFC v6 06/11] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
2020-11-26 22:32 ` [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
2020-11-27 19:04 ` Eduardo Habkost
2020-11-27 19:47 ` Claudio Fontana
2020-11-27 20:43 ` Eduardo Habkost
2020-11-29 11:53 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode Claudio Fontana
2021-01-11 18:43 ` Claudio Fontana
2021-01-12 9:23 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 09/11] accel: replace struct CpusAccel with AccelOpsClass Claudio Fontana
2020-11-26 22:32 ` [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
2020-11-27 6:21 ` Paolo Bonzini
2020-11-27 8:59 ` Claudio Fontana
2020-11-27 11:22 ` Claudio Fontana
2020-11-27 11:41 ` Claudio Fontana
2020-11-27 13:31 ` Paolo Bonzini
2020-11-27 13:32 ` Claudio Fontana
2020-12-18 17:51 ` Claudio Fontana
2020-12-18 18:01 ` Paolo Bonzini
2020-12-18 18:04 ` Claudio Fontana
2020-12-18 21:55 ` Claudio Fontana
2020-12-18 22:30 ` Claudio Fontana
2020-12-18 23:00 ` Claudio Fontana
2021-01-11 16:13 ` Claudio Fontana
2021-01-11 18:08 ` Claudio Fontana
2021-01-11 22:35 ` Eduardo Habkost
2021-01-11 23:35 ` Claudio Fontana
2020-11-27 17:06 ` Eduardo Habkost
2020-11-27 17:58 ` Claudio Fontana
2020-11-27 18:13 ` Eduardo Habkost
2020-11-27 18:20 ` Claudio Fontana
2020-11-26 22:32 ` [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
2020-11-27 17:41 ` Eduardo Habkost
2020-11-27 17:53 ` Claudio Fontana
2020-11-27 18:09 ` Eduardo Habkost
2020-11-27 18:16 ` Claudio Fontana
2020-11-27 18:33 ` Eduardo Habkost
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.