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Thu, 31 Mar 2022 03:10:28 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id a26-20020a19fc1a000000b0044ab4920887sm805769lfi.57.2022.03.31.03.10.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Mar 2022 03:10:28 -0700 (PDT) Message-ID: Date: Thu, 31 Mar 2022 13:10:27 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v6 4/8] drm/msm/dp: avoid handling masked interrupts Content-Language: en-GB To: "Sankeerth Billakanti (QUIC)" Cc: "dri-devel@lists.freedesktop.org" , "linux-arm-msm@vger.kernel.org" , "freedreno@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "robdclark@gmail.com" , "seanpaul@chromium.org" , "swboyd@chromium.org" , quic_kalyant , "Abhinav Kumar (QUIC)" , "dianders@chromium.org" , "Kuogee Hsieh (QUIC)" , "bjorn.andersson@linaro.org" , "sean@poorly.run" , "airlied@linux.ie" , "daniel@ffwll.ch" , quic_vproddut , "Aravind Venkateswaran (QUIC)" References: <1648656179-10347-1-git-send-email-quic_sbillaka@quicinc.com> <1648656179-10347-5-git-send-email-quic_sbillaka@quicinc.com> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 31/03/2022 08:53, Sankeerth Billakanti (QUIC) wrote: > Hi Dmitry, > >> On Wed, 30 Mar 2022 at 19:03, Sankeerth Billakanti >> wrote: >>> >>> The interrupt register will still reflect the connect and disconnect >>> interrupt status without generating an actual HW interrupt. >>> The controller driver should not handle those masked interrupts. >>> >>> Signed-off-by: Sankeerth Billakanti >>> --- >>> drivers/gpu/drm/msm/dp/dp_catalog.c | 5 +++-- >>> 1 file changed, 3 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c >>> b/drivers/gpu/drm/msm/dp/dp_catalog.c >>> index 3c16f95..1809ce2 100644 >>> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c >>> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c >>> @@ -608,13 +608,14 @@ u32 dp_catalog_hpd_get_intr_status(struct >>> dp_catalog *dp_catalog) { >>> struct dp_catalog_private *catalog = container_of(dp_catalog, >>> struct dp_catalog_private, dp_catalog); >>> - int isr = 0; >>> + int isr, mask; >>> >>> isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); >>> dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, >>> (isr & DP_DP_HPD_INT_MASK)); >>> + mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); >>> >>> - return isr; >>> + return isr & (DP_DP_HPD_STATE_STATUS_MASK | mask); >> >> I suspect that the logic is inverted here. Shouldn't it be: >> >> return isr & DP_DP_HPD_STATE_STATUS_MASK & mask; >> >> ? >> > > The value of DP_DP_HPD_STATE_STATUS_MASK is 0xE0000000 and the value of the read > interrupt mask variable could be is 0xF. > > The mask value is indicated via the register, REG_DP_DP_HPD_INT_MASK, bits 3:0. > The HPD status is indicated via a different read-only register REG_DP_DP_HPD_INT_STATUS, bits 31:29. I see. Maybe the following expression would be better? return isr & (mask & ~DP_DP_HPD_INT_MASK); > > isr & DP_DP_HPD_STATE_STATUS_MASK & mask, will return 0 always. > >>> } >>> >>> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) >>> -- >>> 2.7.4 >>> >> >> >> -- >> With best wishes >> Dmitry > > Thank you, > Sankeerth -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DE6EC433EF for ; Thu, 31 Mar 2022 10:10:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D375710E74F; Thu, 31 Mar 2022 10:10:31 +0000 (UTC) Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA87D10E9F3 for ; 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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v6 4/8] drm/msm/dp: avoid handling masked interrupts Content-Language: en-GB To: "Sankeerth Billakanti (QUIC)" References: <1648656179-10347-1-git-send-email-quic_sbillaka@quicinc.com> <1648656179-10347-5-git-send-email-quic_sbillaka@quicinc.com> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quic_kalyant , "devicetree@vger.kernel.org" , "bjorn.andersson@linaro.org" , "dianders@chromium.org" , "Abhinav Kumar \(QUIC\)" , quic_vproddut , "airlied@linux.ie" , "linux-arm-msm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "swboyd@chromium.org" , "sean@poorly.run" , "seanpaul@chromium.org" , "Aravind Venkateswaran \(QUIC\)" , "Kuogee Hsieh \(QUIC\)" , "freedreno@lists.freedesktop.org" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 31/03/2022 08:53, Sankeerth Billakanti (QUIC) wrote: > Hi Dmitry, > >> On Wed, 30 Mar 2022 at 19:03, Sankeerth Billakanti >> wrote: >>> >>> The interrupt register will still reflect the connect and disconnect >>> interrupt status without generating an actual HW interrupt. >>> The controller driver should not handle those masked interrupts. >>> >>> Signed-off-by: Sankeerth Billakanti >>> --- >>> drivers/gpu/drm/msm/dp/dp_catalog.c | 5 +++-- >>> 1 file changed, 3 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c >>> b/drivers/gpu/drm/msm/dp/dp_catalog.c >>> index 3c16f95..1809ce2 100644 >>> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c >>> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c >>> @@ -608,13 +608,14 @@ u32 dp_catalog_hpd_get_intr_status(struct >>> dp_catalog *dp_catalog) { >>> struct dp_catalog_private *catalog = container_of(dp_catalog, >>> struct dp_catalog_private, dp_catalog); >>> - int isr = 0; >>> + int isr, mask; >>> >>> isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); >>> dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, >>> (isr & DP_DP_HPD_INT_MASK)); >>> + mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); >>> >>> - return isr; >>> + return isr & (DP_DP_HPD_STATE_STATUS_MASK | mask); >> >> I suspect that the logic is inverted here. Shouldn't it be: >> >> return isr & DP_DP_HPD_STATE_STATUS_MASK & mask; >> >> ? >> > > The value of DP_DP_HPD_STATE_STATUS_MASK is 0xE0000000 and the value of the read > interrupt mask variable could be is 0xF. > > The mask value is indicated via the register, REG_DP_DP_HPD_INT_MASK, bits 3:0. > The HPD status is indicated via a different read-only register REG_DP_DP_HPD_INT_STATUS, bits 31:29. I see. Maybe the following expression would be better? return isr & (mask & ~DP_DP_HPD_INT_MASK); > > isr & DP_DP_HPD_STATE_STATUS_MASK & mask, will return 0 always. > >>> } >>> >>> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) >>> -- >>> 2.7.4 >>> >> >> >> -- >> With best wishes >> Dmitry > > Thank you, > Sankeerth -- With best wishes Dmitry