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Fri, 31 Jan 2020 06:51:20 +0000 (UTC) Received: from localhost.localdomain (vpn2-54-25.bne.redhat.com [10.64.54.25]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3270D8D7A; Fri, 31 Jan 2020 06:51:07 +0000 (UTC) Subject: Re: [RFC PATCH] hw/arm/virt: Support NMI injection To: Marc Zyngier References: <20191219040612.28431-1-gshan@redhat.com> <9f82206e-0852-ae17-8c77-01d2a5cea97d@redhat.com> <51a83889-f2ef-5403-6661-710cfa1ffe01@redhat.com> <4a517e53-9a7c-903a-9fbc-e1aab1cccefb@redhat.com> <503f32a53fb1a81e2612bcf3eff965da@kernel.org> From: Gavin Shan Message-ID: Date: Fri, 31 Jan 2020 17:51:05 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <503f32a53fb1a81e2612bcf3eff965da@kernel.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: bVjwnyfxNzyWyobIqSSqdw-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Gavin Shan Cc: peter.maydell@linaro.org, drjones@redhat.com, Julien Thierry , aik@ozlabs.ru, qemu-devel@nongnu.org, eric.auger@redhat.com, qemu-arm@nongnu.org, shan.gavin@gmail.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/30/20 9:58 PM, Marc Zyngier wrote: > On 2020-01-29 21:54, Gavin Shan wrote: >> On 1/29/20 6:57 PM, Julien Thierry wrote: >>> On 1/29/20 3:46 AM, Gavin Shan wrote: >>>> On 1/28/20 7:29 PM, Julien Thierry wrote: >> >> .../... >> >>>> >>>> Julien, thanks for the explanation. The question we're not sure if NMI= should >>>> be injected on receiving HMP/QMP "nmi" command. It means it's not clea= r what >>>> behavior we should have for this command on ARM. However, I have one m= ore >>>> unrelated question: "pseudo" NMI on ARM64 should be PPI? I mean SPI ca= n't >>>> be "pseudo" NMI. >>>> >>> >>> I'm not sure I understand why you say "SPI can't be "pseudo" NMI". Curr= ently both PPI and SPI are supported in the "pseudo" NMI scheme. Do you thi= nk that should not be the case? If so, can you elaborate? >>> >>> Thanks, >>> >> >> Julien, NMI interrupt is connected to the system by request_nmi() where = we have >> a check as below. -EINVAL will be returned from request_nmi() on those >> interrupts >> whose descriptors aren't marked with IRQ_NOAUTOEN. SPI falls into this c= ategory. >=20 > The IRQ_NOAUTOEN is set on PPIs because you can't enable them all at once= , > for obvious reasons. >=20 > This doesn't mean you cannot set it on other interrupt classes, including= SPIs. > It is actually a fairly common thing to do when you want to decouple requ= esting > the interrupt from the enabling, if you do not want the interrupt to be a= ble to > fire right away. >=20 > =A0=A0=A0=A0=A0=A0=A0 M. Marc, Ok, thanks for the details, which make things clear. Thanks, Gavin