All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	ML dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 4/5] drm/i915/ttm: Use TTM for system memory
Date: Thu, 3 Jun 2021 16:27:34 +0200	[thread overview]
Message-ID: <da197ad6-f408-004b-dd7b-9348ca602f0d@linux.intel.com> (raw)
In-Reply-To: <CAM0jSHPfNhw3e9y4eD5X+Bk-i1nkZqb1Tw194mhOFNGbHZD8xw@mail.gmail.com>


On 6/3/21 11:48 AM, Matthew Auld wrote:
> On Wed, 2 Jun 2021 at 18:08, Thomas Hellström
> <thomas.hellstrom@linux.intel.com> wrote:
>> For discrete, use TTM for both cached and WC system memory. That means
>> we currently rely on the TTM memory accounting / shrinker. For cached
>> system memory we should consider remaining shmem-backed, which can be
>> implemented from our ttm_tt_populate calback. We can then also reuse our
>> own very elaborate shrinker for that memory.
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/gem/i915_gem_ttm.c    | 22 ++++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_drv.h            |  3 ---
>>   drivers/gpu/drm/i915/intel_memory_region.c |  7 ++++++-
>>   drivers/gpu/drm/i915/intel_memory_region.h |  8 ++++++++
>>   4 files changed, 36 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> index 8e1c01168c6d..42e89bf43708 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> @@ -755,3 +755,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>>          /* i915 wants -ENXIO when out of memory region space. */
>>          return (ret == -ENOSPC) ? -ENXIO : ret;
>>   }
>> +
>> +static const struct intel_memory_region_ops ttm_system_region_ops = {
>> +       .init_object = __i915_gem_ttm_object_init,
>> +};
>> +
>> +struct intel_memory_region *
>> +i915_gem_ttm_system_setup(struct drm_i915_private *i915,
>> +                         u16 type, u16 instance)
>> +{
>> +       struct intel_memory_region *mr;
>> +
>> +       mr = intel_memory_region_create(i915, 0,
>> +                                       totalram_pages() << PAGE_SHIFT,
>> +                                       PAGE_SIZE, 0,
>> +                                       type, instance,
>> +                                       &ttm_system_region_ops);
>> +       if (IS_ERR_OR_NULL(mr))
> region_create can't return NULL.
OK, will fix.


WARNING: multiple messages have this Message-ID
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	ML dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 4/5] drm/i915/ttm: Use TTM for system memory
Date: Thu, 3 Jun 2021 16:27:34 +0200	[thread overview]
Message-ID: <da197ad6-f408-004b-dd7b-9348ca602f0d@linux.intel.com> (raw)
In-Reply-To: <CAM0jSHPfNhw3e9y4eD5X+Bk-i1nkZqb1Tw194mhOFNGbHZD8xw@mail.gmail.com>


On 6/3/21 11:48 AM, Matthew Auld wrote:
> On Wed, 2 Jun 2021 at 18:08, Thomas Hellström
> <thomas.hellstrom@linux.intel.com> wrote:
>> For discrete, use TTM for both cached and WC system memory. That means
>> we currently rely on the TTM memory accounting / shrinker. For cached
>> system memory we should consider remaining shmem-backed, which can be
>> implemented from our ttm_tt_populate calback. We can then also reuse our
>> own very elaborate shrinker for that memory.
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/gem/i915_gem_ttm.c    | 22 ++++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_drv.h            |  3 ---
>>   drivers/gpu/drm/i915/intel_memory_region.c |  7 ++++++-
>>   drivers/gpu/drm/i915/intel_memory_region.h |  8 ++++++++
>>   4 files changed, 36 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> index 8e1c01168c6d..42e89bf43708 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> @@ -755,3 +755,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>>          /* i915 wants -ENXIO when out of memory region space. */
>>          return (ret == -ENOSPC) ? -ENXIO : ret;
>>   }
>> +
>> +static const struct intel_memory_region_ops ttm_system_region_ops = {
>> +       .init_object = __i915_gem_ttm_object_init,
>> +};
>> +
>> +struct intel_memory_region *
>> +i915_gem_ttm_system_setup(struct drm_i915_private *i915,
>> +                         u16 type, u16 instance)
>> +{
>> +       struct intel_memory_region *mr;
>> +
>> +       mr = intel_memory_region_create(i915, 0,
>> +                                       totalram_pages() << PAGE_SHIFT,
>> +                                       PAGE_SIZE, 0,
>> +                                       type, instance,
>> +                                       &ttm_system_region_ops);
>> +       if (IS_ERR_OR_NULL(mr))
> region_create can't return NULL.
OK, will fix.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-06-03 14:27 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-02 17:07 [PATCH 0/5] drm/i915: Move system memory to TTM for discrete Thomas Hellström
2021-06-02 17:07 ` [Intel-gfx] " Thomas Hellström
2021-06-02 17:07 ` [PATCH 1/5] drm/i915: Update object placement flags to be mutable Thomas Hellström
2021-06-02 17:07   ` [Intel-gfx] " Thomas Hellström
2021-06-03 11:17   ` Matthew Auld
2021-06-03 11:17     ` Matthew Auld
2021-06-03 14:08     ` Thomas Hellström
2021-06-03 14:08       ` Thomas Hellström
2021-06-02 17:07 ` [PATCH 2/5] drm/i915/ttm: Adjust gem flags and caching settings after a move Thomas Hellström
2021-06-02 17:07   ` [Intel-gfx] " Thomas Hellström
2021-06-03 10:35   ` Matthew Auld
2021-06-03 10:35     ` Matthew Auld
2021-06-03 13:40     ` Thomas Hellström
2021-06-03 13:40       ` Thomas Hellström
2021-06-02 17:07 ` [PATCH 3/5] drm/i915/ttm: Calculate the object placement at get_pages time Thomas Hellström
2021-06-02 17:07   ` [Intel-gfx] " Thomas Hellström
2021-06-03 10:58   ` Matthew Auld
2021-06-03 10:58     ` Matthew Auld
2021-06-02 17:07 ` [PATCH 4/5] drm/i915/ttm: Use TTM for system memory Thomas Hellström
2021-06-02 17:07   ` [Intel-gfx] " Thomas Hellström
2021-06-03  9:48   ` Matthew Auld
2021-06-03  9:48     ` Matthew Auld
2021-06-03 14:27     ` Thomas Hellström [this message]
2021-06-03 14:27       ` Thomas Hellström
2021-06-02 17:07 ` [PATCH 5/5] drm/i915/ttm: Implement object migration Thomas Hellström
2021-06-02 17:07   ` [Intel-gfx] " Thomas Hellström
2021-06-02 17:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Move system memory to TTM for discrete Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=da197ad6-f408-004b-dd7b-9348ca602f0d@linux.intel.com \
    --to=thomas.hellstrom@linux.intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.william.auld@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.