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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006f3ef214dc7sm7416333ejb.45.2022.06.29.02.20.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jun 2022 02:20:38 -0700 (PDT) Message-ID: Date: Wed, 29 Jun 2022 11:20:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Content-Language: en-US To: Chanho Park , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220628044222.152794-1-chanho61.park@samsung.com> <20220628044222.152794-3-chanho61.park@samsung.com> From: Krzysztof Kozlowski In-Reply-To: <20220628044222.152794-3-chanho61.park@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 28/06/2022 06:42, Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 has different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park > --- > drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index b3c50c7665fc..51a0e830441b 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { > * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. > * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. > * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. > + * @clk_div: Internal clock divider, if not specified, use 2 as the default. > * @quirks: Bitmask of known quirks > * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. > * @clk_from_cmu: True, if the controller does not include a clock mux and > @@ -148,6 +149,7 @@ struct s3c64xx_spi_port_config { > int rx_lvl_offset; > int tx_st_done; > int quirks; > + int clk_div; > bool high_speed; > bool clk_from_cmu; > bool clk_ioclk; > @@ -620,6 +622,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) > void __iomem *regs = sdd->regs; > int ret; > u32 val; > + u32 div = sdd->port_conf->clk_div; > > /* Disable Clock */ > if (!sdd->port_conf->clk_from_cmu) { > @@ -668,16 +671,15 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) > writel(val, regs + S3C64XX_SPI_MODE_CFG); > > if (sdd->port_conf->clk_from_cmu) { > - /* The src_clk clock is divided internally by 2 */ > - ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); > + ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); > if (ret) > return ret; > - sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; > + sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; > } else { > /* Configure Clock */ > val = readl(regs + S3C64XX_SPI_CLK_CFG); > val &= ~S3C64XX_SPI_PSR_MASK; > - val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) > + val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) > & S3C64XX_SPI_PSR_MASK); > writel(val, regs + S3C64XX_SPI_CLK_CFG); > > @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > struct s3c64xx_spi_csinfo *cs = spi->controller_data; > struct s3c64xx_spi_driver_data *sdd; > int err; > + u32 div = 2; This assignment is not effective - shortly later is being overwritten. > > sdd = spi_master_get_devdata(spi->master); > if (spi->dev.of_node) { > @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > > pm_runtime_get_sync(&sdd->pdev->dev); > > + div = sdd->port_conf->clk_div; > + Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7406C433EF for ; Wed, 29 Jun 2022 09:21:37 +0000 (UTC) DKIM-Signature: v=1; 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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006f3ef214dc7sm7416333ejb.45.2022.06.29.02.20.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jun 2022 02:20:38 -0700 (PDT) Message-ID: Date: Wed, 29 Jun 2022 11:20:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Content-Language: en-US To: Chanho Park , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220628044222.152794-1-chanho61.park@samsung.com> <20220628044222.152794-3-chanho61.park@samsung.com> From: Krzysztof Kozlowski In-Reply-To: <20220628044222.152794-3-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220629_022039_929209_5942BEC3 X-CRM114-Status: GOOD ( 21.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 28/06/2022 06:42, Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 has different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park > --- > drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index b3c50c7665fc..51a0e830441b 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { > * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. > * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. > * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. > + * @clk_div: Internal clock divider, if not specified, use 2 as the default. > * @quirks: Bitmask of known quirks > * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. > * @clk_from_cmu: True, if the controller does not include a clock mux and > @@ -148,6 +149,7 @@ struct s3c64xx_spi_port_config { > int rx_lvl_offset; > int tx_st_done; > int quirks; > + int clk_div; > bool high_speed; > bool clk_from_cmu; > bool clk_ioclk; > @@ -620,6 +622,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) > void __iomem *regs = sdd->regs; > int ret; > u32 val; > + u32 div = sdd->port_conf->clk_div; > > /* Disable Clock */ > if (!sdd->port_conf->clk_from_cmu) { > @@ -668,16 +671,15 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) > writel(val, regs + S3C64XX_SPI_MODE_CFG); > > if (sdd->port_conf->clk_from_cmu) { > - /* The src_clk clock is divided internally by 2 */ > - ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); > + ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); > if (ret) > return ret; > - sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; > + sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; > } else { > /* Configure Clock */ > val = readl(regs + S3C64XX_SPI_CLK_CFG); > val &= ~S3C64XX_SPI_PSR_MASK; > - val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) > + val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) > & S3C64XX_SPI_PSR_MASK); > writel(val, regs + S3C64XX_SPI_CLK_CFG); > > @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > struct s3c64xx_spi_csinfo *cs = spi->controller_data; > struct s3c64xx_spi_driver_data *sdd; > int err; > + u32 div = 2; This assignment is not effective - shortly later is being overwritten. > > sdd = spi_master_get_devdata(spi->master); > if (spi->dev.of_node) { > @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > > pm_runtime_get_sync(&sdd->pdev->dev); > > + div = sdd->port_conf->clk_div; > + Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel