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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id u23sm3713829edt.87.2021.02.05.01.20.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Feb 2021 01:20:39 -0800 (PST) Subject: Re: [PATCH v4 4/5] KVM: MMU: Add support for PKS emulation To: Chenyi Qiang , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Xiaoyao Li Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210205083706.14146-1-chenyi.qiang@intel.com> <20210205083706.14146-5-chenyi.qiang@intel.com> From: Paolo Bonzini Message-ID: Date: Fri, 5 Feb 2021 10:20:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210205083706.14146-5-chenyi.qiang@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/02/21 09:37, Chenyi Qiang wrote: > |In addition to the pkey check for user pages, advertise pkr_mask also > to cache the conditions where protection key checks for supervisor pages > are needed. Add CR4_PKS in mmu_role_bits to track the pkr_mask update on > a per-mmu basis. In original cache conditions of pkr_mask, U/S bit in > page tables is a judgement condition and replace the PFEC.RSVD in page > fault error code to form the index of 16 domains. PKS support would > extend the U/S bits (if U/S=0, PKS check required). It adds an > additional check for cr4_pke/cr4_pks to ensure the necessity and > distinguish PKU and PKS from each other. | Slight changes to the commit message: Up until now, pkr_mask had 0 bits for supervisor pages (the U/S bit in page tables replaces the PFEC.RSVD in page fault error code). For PKS support, fill in the bits using the same algorithm used for user mode pages, but with CR4.PKE replaced by CR4.PKS. Because of this change, CR4.PKS must also be included in the MMU role. Paolo