From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rhyland Klein Subject: Re: [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Date: Thu, 23 Jun 2016 11:27:07 -0400 Message-ID: References: <20160623105231.24383-1-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160623105231.24383-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Peter De Schrijver , Jon Hunter , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 6/23/2016 6:52 AM, Thierry Reding wrote: > From: Thierry Reding > > It turns out that sor_safe, rather than pll_p, is the parent of the > dpaux and dpaux1 clocks. > > Signed-off-by: Thierry Reding > --- > drivers/clk/tegra/clk-tegra210.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index aab32af77aa2..fe295b4102ca 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, > 1, 2); > clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, > 1, 17, 181); > clks[TEGRA210_CLK_DPAUX] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, > 1, 17, 207); > clks[TEGRA210_CLK_DPAUX1] = clk; > > Acked-by: Rhyland Klein -- nvpublic From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hqemgate15.nvidia.com ([216.228.121.64]:5171 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750919AbcFWP1Q (ORCPT ); Thu, 23 Jun 2016 11:27:16 -0400 Subject: Re: [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 To: Thierry Reding References: <20160623105231.24383-1-thierry.reding@gmail.com> CC: Peter De Schrijver , Jon Hunter , , From: Rhyland Klein Message-ID: Date: Thu, 23 Jun 2016 11:27:07 -0400 MIME-Version: 1.0 In-Reply-To: <20160623105231.24383-1-thierry.reding@gmail.com> Content-Type: text/plain; charset="windows-1252" Sender: linux-clk-owner@vger.kernel.org List-ID: On 6/23/2016 6:52 AM, Thierry Reding wrote: > From: Thierry Reding > > It turns out that sor_safe, rather than pll_p, is the parent of the > dpaux and dpaux1 clocks. > > Signed-off-by: Thierry Reding > --- > drivers/clk/tegra/clk-tegra210.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index aab32af77aa2..fe295b4102ca 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, > 1, 2); > clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, > 1, 17, 181); > clks[TEGRA210_CLK_DPAUX] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, > 1, 17, 207); > clks[TEGRA210_CLK_DPAUX1] = clk; > > Acked-by: Rhyland Klein -- nvpublic