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([2001:b07:6468:f312:8d3e:39e5:cd88:13cc]) by smtp.gmail.com with ESMTPSA id w6sm9767182wrt.39.2020.05.07.10.42.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2020 10:42:25 -0700 (PDT) Subject: Re: [PATCH 9/9] KVM: VMX: pass correct DR6 for GD userspace exit To: Peter Xu Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org References: <20200507115011.494562-1-pbonzini@redhat.com> <20200507115011.494562-10-pbonzini@redhat.com> <20200507161854.GF228260@xz-x1> <7abe5f7b-2b5a-4e32-34e2-f37d0afef00a@redhat.com> <20200507163839.GG228260@xz-x1> From: Paolo Bonzini Message-ID: Date: Thu, 7 May 2020 19:42:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200507163839.GG228260@xz-x1> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/05/20 18:38, Peter Xu wrote: > On Thu, May 07, 2020 at 06:21:18PM +0200, Paolo Bonzini wrote: >> On 07/05/20 18:18, Peter Xu wrote: >>>> if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { >>>> - vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; >>>> + vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1; >>> After a second thought I'm thinking whether it would be okay to have BS set in >>> that test case. I just remembered there's a test case in the kvm-unit-test >>> that checks explicitly against BS leftover as long as dr6 is not cleared >>> explicitly by the guest code, while the spec seems to have no explicit >>> description on this case. >> >> Yes, I noticed that test as well. But I don't like having different >> behavior for Intel and AMD, and the Intel behavior is more sensible. >> Also... > > Do you mean the AMD behavior is more sensible instead? :) No, I mean within the context of KVM_EXIT_DEBUG: the Intel behavior is to only include the latest debug exception in kvm_run's DR6 field, while the AMD behavior would be to include all of them. This was an implementation detail (it happens because Intel sets kvm_run's DR6 from the exit qualification of #DB), but it's more sensible too. In addition: * AMD was completely broken until this week, so the behavior of KVM_EXIT_DEBUG is defined de facto by kvm_intel.ko. Userspace has not been required to set DR6 with KVM_SET_GUEST_DEBUG, and since we can emulate that on AMD, we should. * we have to fix anyway the fact that on AMD a KVM_EXIT_DEBUG is clobbering the contents of the guest's DR6 >>> Intead of above, I'm thinking whether we should allow the userspace to also >>> change dr6 with the KVM_SET_GUEST_DEBUG ioctl when they wanted to (right now >>> iiuc dr6 from userspace is completely ignored), instead of offering a fake dr6. >>> Or to make it simple, maybe we can just check BD bit only? >> >> ... I'm afraid that this would be a backwards-incompatible change, and >> it would require changes in userspace. If you look at v2, emulating the >> Intel behavior in AMD turns out to be self-contained and relatively >> elegant (will be better when we finish cleaning up nested SVM). > > I'm still trying to read the other patches (I need some more digest because I'm > even less familiar with nested...). I agree that it would be good to keep the > same behavior across Intel/AMD. Actually that also does not violate Intel spec > because the AMD one is stricter. Again, careful---we're talking about KVM_EXIT_DEBUG, not the #DB exception. Thanks, Paolo > However I guess then we might also want to > fixup the kvm-unit-test too to aligh with the behaviors on leftover set bits.