From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752687AbeC2KDd (ORCPT ); Thu, 29 Mar 2018 06:03:33 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:43671 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752246AbeC2KDb (ORCPT ); Thu, 29 Mar 2018 06:03:31 -0400 Subject: Re: [PATCH v5 11/12] PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly To: Niklas Cassel , , Jingoo Han , Joao Pinto , Lorenzo Pieralisi , Bjorn Helgaas References: <20180328115018.31921-1-niklas.cassel@axis.com> <20180328115018.31921-12-niklas.cassel@axis.com> CC: Niklas Cassel , , From: Kishon Vijay Abraham I Message-ID: Date: Thu, 29 Mar 2018 15:33:16 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20180328115018.31921-12-niklas.cassel@axis.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 28 March 2018 05:20 PM, Niklas Cassel wrote: > Since a 64-bit BAR consists of a BAR pair, we need to write to both > BARs in the BAR pair to clear the BAR properly. > > Signed-off-by: Niklas Cassel Acked-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/pcie-designware-ep.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c > index cc4d8381c1dc..4d304e3ccf24 100644 > --- a/drivers/pci/dwc/pcie-designware-ep.c > +++ b/drivers/pci/dwc/pcie-designware-ep.c > @@ -28,6 +28,10 @@ static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar, > dw_pcie_dbi_ro_wr_en(pci); > dw_pcie_writel_dbi2(pci, reg, 0x0); > dw_pcie_writel_dbi(pci, reg, 0x0); > + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { > + dw_pcie_writel_dbi2(pci, reg + 4, 0x0); > + dw_pcie_writel_dbi(pci, reg + 4, 0x0); > + } > dw_pcie_dbi_ro_wr_dis(pci); > } > >