From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 392FCC433EF for ; Tue, 12 Apr 2022 07:37:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6093C10E497; Tue, 12 Apr 2022 07:37:57 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id CCE8E10EB5F for ; Tue, 12 Apr 2022 07:37:55 +0000 (UTC) X-UUID: a112a8e74bcc4e8cafd2fe0dbea82415-20220412 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:0009f623-99a6-4f2d-b87c-b7bf1ad04e0d, OB:0, LO B:10,IP:0,URL:0,TC:0,Content:14,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:59 X-CID-INFO: VERSION:1.1.4, REQID:0009f623-99a6-4f2d-b87c-b7bf1ad04e0d, OB:0, LOB: 10,IP:0,URL:0,TC:0,Content:14,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:59 X-CID-META: VersionHash:faefae9, CLOUDID:d549dea8-d103-4e36-82b9-b0e86991b3df, C OID:6db2902810e7,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:3,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: a112a8e74bcc4e8cafd2fe0dbea82415-20220412 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 204760330; Tue, 12 Apr 2022 15:37:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 12 Apr 2022 15:37:48 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Apr 2022 15:37:48 +0800 Message-ID: Subject: Re: [PATCH v4,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 From: Rex-BC Chen To: , , , , , Date: Tue, 12 Apr 2022 15:37:48 +0800 In-Reply-To: <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> References: <1649644308-8455-1-git-send-email-xinlei.lee@mediatek.com> <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jitao.shi@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > Old sequence: > 1. Pull the MIPI signal high > 2. Delay & Dsi_reset > 3. Set the dsi timing register > 4. dsi clk & lanes leave ulp mode and enter hs mode > > The sequence after patching is: > 1. Set the dsi timing register > 2. Pull the MIPI signal high > 3. Delay & Dsi_reset > 4. dsi clk & lanes leave ulp mode and enter hs mode > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index ccb0511b9cd5..262c027d8c2f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > mtk_dsi_clk_ulp_mode_leave(dsi); > mtk_dsi_lane0_ulp_mode_leave(dsi); > mtk_dsi_clk_hs_mode(dsi, 0); Reviewed-by: Rex-BC Chen From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8CC3C433F5 for ; Tue, 12 Apr 2022 07:53:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/RJswAQz9mbfMFYSxfepjEIkPCGeTpJ7V1QAbbDnWks=; b=mNTod/NQ/ys43H 0pfvWqNGGqO272xuwebo+gKMICtj+FTJBB1BJataCxlhaTuTJvUGf8dTTfar2EN0J4mNCKI0Op3B4 dub3cz8TLeUdDMZ+N5ycNfjLlDjJRKhO/s/DQ6jgnW8c6lzr8N6r+DZQB5NBd34YR5pE5+O5BlpaS 1er+2rjcD9DO9Ux7KbgNKKYgUlizOJqqSymDcryLK3GyB2FH9QZwQr1DIJDOpeNeWn5vDNRRZH0W4 WcTbcIwG8wpcQ6KOoEDOjYnmnqUTKj+fR//99K8HZf8ZgCR742VyNaEUrW+H2BdRaU6aD+yn/CLf+ phcpdq1zdInHvsvLIJ2w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neBLO-00CLre-KW; Tue, 12 Apr 2022 07:53:46 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neBCh-00CHTU-3b; Tue, 12 Apr 2022 07:44:48 +0000 X-UUID: 95aeb87111514b45bef10d171cb56989-20220412 X-UUID: 95aeb87111514b45bef10d171cb56989-20220412 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1386769746; Tue, 12 Apr 2022 00:44:40 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Apr 2022 00:37:49 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 12 Apr 2022 15:37:48 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Apr 2022 15:37:48 +0800 Message-ID: Subject: Re: [PATCH v4,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 From: Rex-BC Chen To: , , , , , CC: , , , , , Date: Tue, 12 Apr 2022 15:37:48 +0800 In-Reply-To: <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> References: <1649644308-8455-1-git-send-email-xinlei.lee@mediatek.com> <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_004447_194800_D78D1C26 X-CRM114-Status: GOOD ( 15.10 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > Old sequence: > 1. Pull the MIPI signal high > 2. Delay & Dsi_reset > 3. Set the dsi timing register > 4. dsi clk & lanes leave ulp mode and enter hs mode > > The sequence after patching is: > 1. Set the dsi timing register > 2. Pull the MIPI signal high > 3. Delay & Dsi_reset > 4. dsi clk & lanes leave ulp mode and enter hs mode > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index ccb0511b9cd5..262c027d8c2f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > mtk_dsi_clk_ulp_mode_leave(dsi); > mtk_dsi_lane0_ulp_mode_leave(dsi); > mtk_dsi_clk_hs_mode(dsi, 0); Reviewed-by: Rex-BC Chen _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0DBBC433FE for ; Tue, 12 Apr 2022 07:55:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gngc8cBXb0WSNdV/fnXKLQu4jFj1cQRlx40H2sJzlIA=; b=d5/eBbxwaiWodt rf566ioJ4BeDUd+Soqe9jkLrRGUBY/ZwX7rrAESgBYLKvVZclNk5Rg/JIxFRjCGwzFnvlyVUyXxLF FnpxlP27GcSC1MfZ9fr4aSmPodhqb6p3MtEdVI7ipozYxCn9jJtFGeWwvLotCUNvuz01q5EnVuSfL 8Qz2KtFJl4xa314GcXRivHL+8QWNhRUOTcgB7Hp70MnpJjEtc6VmucUsRs8OcrgbGeMdLjhhN7CLc nVVR+4cfhwkriT3N82uXge64vjGAVIIISCszF8QJP0WRQS2KlRM+2GlMqK0XJqlWTbvGYk4YZJ2PW twU166nCKDsglXjUdEhg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neBLa-00CLu5-Dp; Tue, 12 Apr 2022 07:53:59 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neBCh-00CHTU-3b; Tue, 12 Apr 2022 07:44:48 +0000 X-UUID: 95aeb87111514b45bef10d171cb56989-20220412 X-UUID: 95aeb87111514b45bef10d171cb56989-20220412 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1386769746; Tue, 12 Apr 2022 00:44:40 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Apr 2022 00:37:49 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 12 Apr 2022 15:37:48 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Apr 2022 15:37:48 +0800 Message-ID: Subject: Re: [PATCH v4,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 From: Rex-BC Chen To: , , , , , CC: , , , , , Date: Tue, 12 Apr 2022 15:37:48 +0800 In-Reply-To: <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> References: <1649644308-8455-1-git-send-email-xinlei.lee@mediatek.com> <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_004447_194800_D78D1C26 X-CRM114-Status: GOOD ( 15.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > Old sequence: > 1. Pull the MIPI signal high > 2. Delay & Dsi_reset > 3. Set the dsi timing register > 4. dsi clk & lanes leave ulp mode and enter hs mode > > The sequence after patching is: > 1. Set the dsi timing register > 2. Pull the MIPI signal high > 3. Delay & Dsi_reset > 4. dsi clk & lanes leave ulp mode and enter hs mode > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index ccb0511b9cd5..262c027d8c2f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > mtk_dsi_clk_ulp_mode_leave(dsi); > mtk_dsi_lane0_ulp_mode_leave(dsi); > mtk_dsi_clk_hs_mode(dsi, 0); Reviewed-by: Rex-BC Chen _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E02C3527D for ; Tue, 12 Apr 2022 09:28:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390062AbiDLJYa (ORCPT ); Tue, 12 Apr 2022 05:24:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355539AbiDLIIb (ORCPT ); Tue, 12 Apr 2022 04:08:31 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E867CB78 for ; Tue, 12 Apr 2022 00:37:54 -0700 (PDT) X-UUID: a112a8e74bcc4e8cafd2fe0dbea82415-20220412 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:0009f623-99a6-4f2d-b87c-b7bf1ad04e0d,OB:0,LO B:10,IP:0,URL:0,TC:0,Content:14,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:59 X-CID-INFO: VERSION:1.1.4,REQID:0009f623-99a6-4f2d-b87c-b7bf1ad04e0d,OB:0,LOB: 10,IP:0,URL:0,TC:0,Content:14,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:59 X-CID-META: VersionHash:faefae9,CLOUDID:d549dea8-d103-4e36-82b9-b0e86991b3df,C OID:6db2902810e7,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:3,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: a112a8e74bcc4e8cafd2fe0dbea82415-20220412 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 204760330; Tue, 12 Apr 2022 15:37:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 12 Apr 2022 15:37:48 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Apr 2022 15:37:48 +0800 Message-ID: Subject: Re: [PATCH v4,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 From: Rex-BC Chen To: , , , , , CC: , , , , , Date: Tue, 12 Apr 2022 15:37:48 +0800 In-Reply-To: <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> References: <1649644308-8455-1-git-send-email-xinlei.lee@mediatek.com> <1649644308-8455-2-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > Old sequence: > 1. Pull the MIPI signal high > 2. Delay & Dsi_reset > 3. Set the dsi timing register > 4. dsi clk & lanes leave ulp mode and enter hs mode > > The sequence after patching is: > 1. Set the dsi timing register > 2. Pull the MIPI signal high > 3. Delay & Dsi_reset > 4. dsi clk & lanes leave ulp mode and enter hs mode > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index ccb0511b9cd5..262c027d8c2f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > mtk_dsi_clk_ulp_mode_leave(dsi); > mtk_dsi_lane0_ulp_mode_leave(dsi); > mtk_dsi_clk_hs_mode(dsi, 0); Reviewed-by: Rex-BC Chen