From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v6] drm/i915/icl: Fix clockgating issue when using scalers Date: Thu, 11 Apr 2019 21:41:13 +0000 Message-ID: References: <20190405150700.GL3888@intel.com> <20190405211437.8143-1-radhakrishna.sripada@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1294427165==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id B0FEC89870 for ; Thu, 11 Apr 2019 21:43:01 +0000 (UTC) In-Reply-To: <20190405211437.8143-1-radhakrishna.sripada@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Sripada, Radhakrishna" , "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org --===============1294427165== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-En4wnQhZ6QFGz4/GM+AG" --=-En4wnQhZ6QFGz4/GM+AG Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2019-04-05 at 14:14 -0700, Radhakrishna Sripada wrote: > Fixes the clock-gating issue when pipe scaling is enabled. > (Lineage #2006604312) >=20 > V2: Fix typo in headline(Chris) > Handle the non double buffered nature of the register(Ville) > V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks > unrelated. > V4: Split the icl and skl wa's(Ville) > V5: Split the checks for icl and skl(Ville) > V6: Correct the flipped checks in intel_pre_plane_update(Ville) >=20 > Cc: Chris Wilson > Cc: Ville Syrjala > Cc: Rodrigo Vivi > Cc: Aditya Swarup > Signed-off-by: Radhakrishna Sripada > --- > drivers/gpu/drm/i915/intel_display.c | 39 ++++++++++++++++++++++++ > ---- > 1 file changed, 34 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index cf6046390eeb..ab820cad990d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -466,6 +466,7 @@ static const struct intel_limit intel_limits_bxt > =3D { > .p2 =3D { .p2_slow =3D 1, .p2_fast =3D 20 }, > }; > =20 > +/* WA Display #0827: Gen9:all */ > static void > skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable) > { > @@ -479,6 +480,18 @@ skl_wa_827(struct drm_i915_private *dev_priv, > int pipe, bool enable) > ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); > } > =20 > +/* Wa_2006604312:icl */ > +static void > +icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, int pipe, > bool enable) > +{ > + if (enable) > + I915_WRITE(CLKGATE_DIS_PSL(pipe), > + I915_READ(CLKGATE_DIS_PSL(pipe)) | > DPFR_GATING_DIS); > + else > + I915_WRITE(CLKGATE_DIS_PSL(pipe), > + I915_READ(CLKGATE_DIS_PSL(pipe)) & > ~DPFR_GATING_DIS); > +} > + > static bool > needs_modeset(const struct drm_crtc_state *state) > { > @@ -5495,6 +5508,16 @@ static bool needs_nv12_wa(struct > drm_i915_private *dev_priv, > return false; > } > =20 > +static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv, > + const struct intel_crtc_state > *crtc_state) > +{ > + /* Wa_2006604312:icl */ > + if (crtc_state->pch_pfit.enabled && IS_ICELAKE(dev_priv)) > + return true; Looking to BSpec this WA is needed for other platforms too like elkhartlake, so I would change to: if (INTEL_GEN(dev_priv) >=3D 11) return crtc_state->pch_pfit.enabled; > + > + return false; > +} > + > static void intel_post_plane_update(struct intel_crtc_state > *old_crtc_state) > { > struct intel_crtc *crtc =3D to_intel_crtc(old_crtc_state- > >base.crtc); > @@ -5528,11 +5551,13 @@ static void intel_post_plane_update(struct > intel_crtc_state *old_crtc_state) > intel_post_enable_primary(&crtc->base, > pipe_config); > } > =20 > - /* Display WA 827 */ > if (needs_nv12_wa(dev_priv, old_crtc_state) && > - !needs_nv12_wa(dev_priv, pipe_config)) { > + !needs_nv12_wa(dev_priv, pipe_config)) > skl_wa_827(dev_priv, crtc->pipe, false); > - } > + > + if (needs_scalerclk_wa(dev_priv, old_crtc_state) && > + !needs_scalerclk_wa(dev_priv, pipe_config)) > + icl_wa_scalerclkgating(dev_priv, crtc->pipe, false); > } > =20 > static void intel_pre_plane_update(struct intel_crtc_state > *old_crtc_state, > @@ -5569,9 +5594,13 @@ static void intel_pre_plane_update(struct > intel_crtc_state *old_crtc_state, > =20 > /* Display WA 827 */ > if (!needs_nv12_wa(dev_priv, old_crtc_state) && > - needs_nv12_wa(dev_priv, pipe_config)) { > + needs_nv12_wa(dev_priv, pipe_config)) > skl_wa_827(dev_priv, crtc->pipe, true); > - } > + > + /* Wa_2006604312:icl */ > + if (!needs_scalerclk_wa(dev_priv, old_crtc_state) && > + needs_scalerclk_wa(dev_priv, pipe_config)) > + icl_wa_scalerclkgating(dev_priv, crtc->pipe, true); > =20 > /* > * Vblank time updates from the shadow to live plane control > register --=-En4wnQhZ6QFGz4/GM+AG Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlyvtHgACgkQVenbO/mO Wkn+/wf+MzxzEGL76veh7bSQebV/s21YBRVE80/1HUiFUE3ddpdKk7WW3nOC0jn+ k4/l79mucqWG+xk+l1s8FQnmWHR3iT5+pfgTshCchvFsbFpyogaXVk4thrWA6Ae5 U1+tr8v5QLwDp+D+XpOk6gjVQ5g91o4heP4G9IYmqvylbaK1ZxQOwkmMIiAgXMP3 CYbuXaw5GKhRj53i/kOru9zaq0qCsie7TJEIQABjV75IyGegQ2lb3kL1CIACUttI CO4CkIRe4XLBW3hrHD/usJiTZ/F1/r8a8MII05JrDSNeG8cz/TwmCBBTPO+wavR8 ci6R55TdV2guyY1HH/6AI4owZrUfhw== =InZx -----END PGP SIGNATURE----- --=-En4wnQhZ6QFGz4/GM+AG-- --===============1294427165== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============1294427165==--