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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id fs24sm13029476pjb.6.2021.06.07.12.02.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 12:02:52 -0700 (PDT) Subject: Re: [PATCH 02/55] target/arm: Enable FPSCR.QC bit for MVE To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210607165821.9892-1-peter.maydell@linaro.org> <20210607165821.9892-3-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 7 Jun 2021 12:02:50 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210607165821.9892-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/7/21 9:57 AM, Peter Maydell wrote: > MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE > is implemented make the bit writeable, both in the generic "load and > store FPSCR" helper functions and in the code for handling the NZCVQC > sysreg which we had previously left as "TODO when we implement MVE". > > Signed-off-by: Peter Maydell > --- > target/arm/translate-vfp.c | 32 +++++++++++++++++++++++--------- > target/arm/vfp_helper.c | 3 ++- > 2 files changed, 25 insertions(+), 10 deletions(-) > > diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c > index d01e465821b..22a619eb2c5 100644 > --- a/target/arm/translate-vfp.c > +++ b/target/arm/translate-vfp.c > @@ -784,10 +784,19 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, > { > TCGv_i32 fpscr; > tmp = loadfn(s, opaque); > - /* > - * TODO: when we implement MVE, write the QC bit. > - * For non-MVE, QC is RES0. > - */ > + if (dc_isar_feature(aa32_mve, s)) { > + /* QC is only present for MVE; otherwise RES0 */ > + TCGv_i32 qc = tcg_temp_new_i32(); > + TCGv_i32 zero; > + tcg_gen_andi_i32(qc, tmp, FPCR_QC); > + store_cpu_field(qc, vfp.qc[0]); > + zero = tcg_const_i32(0); > + store_cpu_field(zero, vfp.qc[1]); > + zero = tcg_const_i32(0); > + store_cpu_field(zero, vfp.qc[2]); > + zero = tcg_const_i32(0); > + store_cpu_field(zero, vfp.qc[3]); > + } Ok I guess. You could store the same i32 into all elements: tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc), 16, 16, qc); Either way, Reviewed-by: Richard Henderson r~