From: Tom Lendacky <firstname.lastname@example.org>
To: Sean Christopherson <email@example.com>, Borislav Petkov <firstname.lastname@example.org>
Cc: Pu Wen <email@example.com>, Joerg Roedel <firstname.lastname@example.org>,
email@example.com, firstname.lastname@example.org, email@example.com,
firstname.lastname@example.org, email@example.com, firstname.lastname@example.org,
email@example.com, firstname.lastname@example.org, email@example.com,
Subject: Re: [PATCH] x86/sev: Check whether SEV or SME is supported first
Date: Tue, 1 Jun 2021 11:36:31 -0500 [thread overview]
Message-ID: <firstname.lastname@example.org> (raw)
On 6/1/21 11:14 AM, Sean Christopherson wrote:
> On Tue, Jun 01, 2021, Borislav Petkov wrote:
>> On Mon, May 31, 2021 at 10:56:50PM +0800, Pu Wen wrote:
>>> Thanks for your suggestion, I'll try to set up early #GP handler to fix
>>> the problem.
>> Why? AFAICT, you only need to return early in sme_enable() if CPUID is
>> not "AuthenticAMD". Just do that please.
> I don't think that would suffice, presumably MSR_AMD64_SEV doesn't exist on older
> AMD CPUs either. E.g. there's no mention of MSR 0xC001_0131 in the dev's guide
> from 2015[*].
That is the reason for checking the maximum supported leaf being at least
0x8000001f. If that leaf is supported, we expect the SEV status MSR to be
valid. The problem is that the Hygon ucode does not support the MSR in
question. I'm not sure what it would take for that to be added to their
ucode and just always return 0.
> I also don't see the point in checking the vendor string. A malicious hypervisor
> can lie about CPUID.0x0 just as easily as it can lie about CPUID.0x8000001f, so
> for SEV the options are to either trust the hypervisor or eat #GPs on RDMSR for
> non-SEV CPUs. If we go with "trust the hypervisor", then the original patch of
> hoisting the CPUID.0x8000001f check up is simpler than checking the vendor string.
Because a hypervisor can put anything it wants in the CPUID 0x0 /
0x80000000 fields, I don't think we can just check for "AuthenticAMD".
If we want the read of CPUID 0x8000001f done before reading the SEV status
MSR, then the original patch is close, but slightly flawed, e.g. only SME
can be indicated but then MSR_AMD64_SEV can say SEV active.
If we want to introduce support for handling/detecting #GP, this might
become overly complicated because of the very early, identity mapped state
the code is in - especially for backport to stable.
> [*] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F48751_16h_bkdg.pdf&data=04%7C01%7Cthomas.lendacky%40amd.com%7C6025fb08694e4e6b74bb08d92518549a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637581608717458896%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=CeJXPNxAOPiXQYYXxDKqSrcVBbiY%2FrkQ%2FmPzbRXbSHQ%3D&reserved=0
next prev parent reply other threads:[~2021-06-01 16:36 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-26 7:24 [PATCH] x86/sev: Check whether SEV or SME is supported first Pu Wen
2021-05-26 17:27 ` Sean Christopherson
2021-05-27 15:08 ` Pu Wen
2021-05-31 9:37 ` Joerg Roedel
2021-05-31 14:56 ` Pu Wen
2021-06-01 14:39 ` Borislav Petkov
2021-06-01 16:14 ` Sean Christopherson
2021-06-01 16:36 ` Tom Lendacky [this message]
2021-06-01 16:59 ` Borislav Petkov
2021-06-01 17:16 ` Sean Christopherson
2021-06-01 17:48 ` Borislav Petkov
2021-06-01 18:08 ` Sean Christopherson
2021-06-01 18:24 ` Borislav Petkov
2021-06-01 17:09 ` Sean Christopherson
2021-06-01 18:30 ` Tom Lendacky
2021-06-02 6:55 ` Wen Pu
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