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[83.59.163.107]) by smtp.gmail.com with ESMTPSA id o10sm718525eju.89.2021.02.03.01.22.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Feb 2021 01:22:04 -0800 (PST) Subject: Re: [PULL 00/21] target-arm queue To: Peter Maydell , Prasad J Pandit References: <20210202175517.28729-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 3 Feb 2021 10:22:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.155, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Prasad J Pandit , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Peter, On 2/2/21 6:54 PM, Peter Maydell wrote: > Mostly just bug fixes. The important one here is > hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register > which fixes a buffer overrun that's a security issue if you're running > KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in > a security context, because kernel-irqchip=on is the default and the > sensible choice for performance). FYI Prasad mentioned a CVE was requested: https://www.mail-archive.com/qemu-devel@nongnu.org/msg778659.html As you said it is an odd configuration, I am not sure it is worth to wait for the CVE number to add it to the commit (which helps downstream distributions tracking these). [updating] Just got detail from Prasad on IRC, it usually takes ~1 day to get the CVE number assigned, so maybe worth postponing this until tomorrow. Prasad, can you reply to this message ASAP once you get the number? Thanks, Phil. > -- PMM > > The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e: > > Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210202-1 > > for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a: > > hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * hw/intc/arm_gic: Allow to use QTest without crashing > * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled > * hw/char/exynos4210_uart: Fix missing call to report ready for input > * hw/arm/smmuv3: Fix addr_mask for range-based invalidation > * hw/ssi/imx_spi: Fix various minor bugs > * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register > * hw/arm: Add missing Kconfig dependencies > * hw/arm: Display CPU type in machine description > > ---------------------------------------------------------------- > Bin Meng (5): > hw/ssi: imx_spi: Use a macro for number of chip selects supported > hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() > hw/ssi: imx_spi: Round up the burst length to be multiple of 8 > hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic > hw/ssi: imx_spi: Correct tx and rx fifo endianness > > Iris Johnson (2): > hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled > hw/char/exynos4210_uart: Fix missing call to report ready for input > > Philippe Mathieu-Daudé (12): > hw/intc/arm_gic: Allow to use QTest without crashing > hw/ssi: imx_spi: Remove pointless variable initialization > hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value > hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled > hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled > hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register > hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ > hw/arm/exynos4210: Add missing dependency on OR_IRQ > hw/arm/xlnx-versal: Versal SoC requires ZDMA > hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals > hw/net/can: ZynqMP CAN device requires PTIMER > hw/arm: Display CPU type in machine description > > Xuzhou Cheng (1): > hw/ssi: imx_spi: Disable chip selects when controller is disabled > > Zenghui Yu (1): > hw/arm/smmuv3: Fix addr_mask for range-based invalidation > > include/hw/ssi/imx_spi.h | 5 +- > hw/arm/digic_boards.c | 2 +- > hw/arm/microbit.c | 2 +- > hw/arm/netduino2.c | 2 +- > hw/arm/netduinoplus2.c | 2 +- > hw/arm/orangepi.c | 2 +- > hw/arm/smmuv3.c | 4 +- > hw/arm/stellaris.c | 4 +- > hw/char/exynos4210_uart.c | 7 ++- > hw/intc/arm_gic.c | 5 +- > hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++----------------- > hw/Kconfig | 1 + > hw/arm/Kconfig | 5 ++ > hw/dma/Kconfig | 3 + > hw/dma/meson.build | 2 +- > 15 files changed, 130 insertions(+), 69 deletions(-) >