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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?L3hUUnRCMkJLNSttSFZYVTFKSmZ3bmthUCtlOUF6ei9pS0xBTVpFdHFLU1FU?= =?utf-8?B?czVidm01aUZCUGx0enBsSCtlakxrbjl4U2tMaUt1MnRkSjFmSytSVXg4OVNl?= =?utf-8?B?ODdIYWExT01NeGVOTjcybDVPbVhHbG1TR0pDS1BvYlVUYURzR0VvSnZuZ25v?= =?utf-8?B?VmNnaVlDMENwK0JIeTdoL2F3L1hpdktucCtTMHdWV0xDMFp1Wk13NFgyZmlk?= =?utf-8?B?Yld0QnZGaXc3NnE1dytETEVMNDJ3U0dSU2VmUzZuRHdhVEQxeWo2cnA0c1Q0?= =?utf-8?B?QmtBU3M4MC9LWS9rUGk1aC9CQStSVjhYUk5nVmFJSzRVV3FzbjREMlBjZUlU?= =?utf-8?B?UFR2K3A4cnprMHhYUytTcUdZbklla1dVS2ErREpCS1FYc09URzczQnVjSTZk?= =?utf-8?B?RHFkbCtDQzcvTGQrYTlqcXNRWjdubGtlZ0hiSWptNDZ5ZVczcS9nekFJbXJM?= =?utf-8?B?Z1N3NER3UGVpTkVkckMvOHplWmt1clNqQVJXd2JlaWl1cEFUNmRiWDdWbWcr?= =?utf-8?B?SWc1THRFZEVNdFZVcFpuNHFwd09kM1BESzYyL1gxRVQ1MDQ1eXFTUHA5YUU5?= =?utf-8?B?ZStQYTNOd2NoMGF5SFB6TFliLzllU1FCRXpkdmc3bHNnR2ZvaFdVcERDbmov?= =?utf-8?B?dGNvYkNqYW9wNHk4ZER6dFp5UjVKbmlRd2t0bXNYRUt0am0xTzdBTFB0bVhr?= =?utf-8?B?ZnV1TWtueU5pV1lweU92RnB3UkZIak9KdWp0RzM1d0syclo0NXh1NHkzblBD?= =?utf-8?B?dkNBSlV0cFI5b1VtNzc4d2d5TFREWUMvUXJXTGx4WU1JMU5oU2tXMzFWdXJm?= =?utf-8?B?cHBiTy95MGZBWFVkbk00K0cxQkxWZzdVOGhaLzVWT012SFdYSnZzamYrNVNU?= =?utf-8?B?MDcvUVF2VXhVSjJCaDI5ZmVjRldnRExZY1MzbTJBZnhPcHNDQXhPTXF5ZVBk?= =?utf-8?B?bERCSUMyVkhsN3p6bkNScERZeWp2TnpnUitCZ3c1SDcxbU1IS1RuamJjNnl5?= =?utf-8?B?RzlQVVc5QkpUdGpEU21tVFBsRm5LWDJyMTZZVDA3SzQvU1BhYU1VSWo1a08x?= =?utf-8?B?OWF0UkM0RWYxSkdlMy8wVFlJcmRENmZyblNOY0RFUzFocDJDTE9BMnNrUlBk?= =?utf-8?B?RW1MQ2RBOXpUNitVRmRhOUlmNVppNTZOMGlnb0VCQkdGSDF1WGE3U3ZmNm04?= =?utf-8?B?QTJxS1I0MXhJdTBjUlg4RXMyczYxMXl3Ty9QUGhkVG1WZlg0dWVaL2FQMFlY?= =?utf-8?B?dSs4ZmlFSWxKcWtUVHFqdWw5VW5tL241RGFRRzBvS253ZHVHb3g1b2RXMTBy?= =?utf-8?B?WURoU0VpTUJoZnVQNWlycld2dEl3ZEZvVGE5bmlyZ3VKSHFYR29JdnJnNWJF?= =?utf-8?B?UnNxV0JsYVh6U0FIeGdYRnYzZXdXak9zQXMyWDU2Nks3QXNXY2dob3FPUEhS?= =?utf-8?B?c29lV2tKcnVBTk1BNEk3RzNWT2I4RWNQdkQ0RmNoVzdxWWVHVTlDOTBZTVVL?= =?utf-8?B?NkJmUUFyS0Z5c3Z0MG5GWm5keUlZZGYxT051VHdWa2xuNkJDWjQveloxeHlh?= =?utf-8?B?YmlQR1RHb3VUdTk1ejBGWjV2R1lId0J4eHUyeEhUV0ppWEZDbXhIcFVJRmYz?= =?utf-8?B?MVBTclJNdHhlUlNsWmhhaGkxMis0dmY2bGl4bzVXNkV2MTRmZmFNZEozM1I4?= =?utf-8?B?MnFFcWdqcEhNQW9WcU9PT0pIbXRSWUF0T1EvT2gyUStZSmkzL3p5MEMwOXlW?= =?utf-8?Q?JAz8Og6l7oflZGmFVvqs1ZJs7cazRq/tqcjrPQ/?= X-MS-Exchange-CrossTenant-Network-Message-Id: c51edc4a-7dac-4f68-772c-08d972034851 X-MS-Exchange-CrossTenant-AuthSource: BYAPR03MB3623.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2021 13:27:47.5091 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1qegWzUvuOVh20oKIBvHEmKo5Dpz8ZeHYDzaUgMp3v+LJ6hYaXF8tvDKXtSVhIi1LbzzuMz0PzHhAKt80bUvh5MzNWzEZv1u91cKrRcLeyk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR03MB6391 X-OriginatorOrg: citrix.com On 07/09/2021 07:09, Jan Beulich wrote: > On 06.09.2021 20:07, Andrew Cooper wrote: >> On 06/09/2021 16:17, Jan Beulich wrote: >>> On 06.09.2021 14:00, Jane Malalane wrote: >>>> --- a/xen/arch/x86/cpu/amd.c >>>> +++ b/xen/arch/x86/cpu/amd.c >>>> @@ -681,6 +681,19 @@ void amd_init_lfence(struct cpuinfo_x86 *c) >>>> c->x86_capability); >>>> } >>>> =20 >>>> +void detect_zen2_null_seg_behaviour(void) >>> This can in principle be marked __init. >>> >>>> +{ >>>> + uint64_t base; >>>> + >>>> + wrmsrl(MSR_FS_BASE, 1); >>>> + asm volatile ( "mov %0, %%fs" :: "rm" (0) ); >>> While I don't strictly mind the "m" part of the constraint to remain >>> there (in the hope for compilers actually to support this), iirc it's >>> not useful to have when the value is a constant: Last time I checked, >>> the compiler would not instantiate an anonymous (stack) variable to >>> fulfill this constraint (as can be seen when dropping the "r" part of >>> the constraint). >> This is "rm" because it is what we use elsewhere in Xen for selectors, >> and because it is the correct constraints based on the legal instruction >> encodings. > grep-ing for "%%[defgs]s" reveals: > > efi_arch_post_exit_boot(), svm_ctxt_switch_to(), These are writing multiple selectors in one go, and a register constraint is the only sane option. > and do_set_segment_base() all use just "r". I had missed this one. > This grep has not produced > any use of "rm". What are you talking about? TRY_LOAD_SEG(), pv_emul_read_descriptor() for both lar and lsl, do_double_fault() for another lsl, lldt(), ltr(). So ok - not everything, but most. > >> If you want to work around what you perceive to be bugs in compilers >> then submit a independent change yourself. > I don't perceive this as a bug; perhaps a desirable feature. I also > did start my response with "While I don't strictly mind the "m" > part ..." - was this not careful enough to indicate I'm not going > to insist on the change, but I'd prefer it to be made? No, because a maintainer saying "I'd prefer this to be changed" is still an instruction to the submitter to make the change. But the request is inappropriate.=C2=A0 "Last time I checked, the compiler would" presumably means you've checked GCC and not Clang, and therefore any conclusions about the behaviour are incomplete. Unless there is a real concrete compiler bug to work around, "rm" is the appropriate constraint to use, all other things being equal.=C2=A0 If the complier is merely doing something dumb with the flexibility it has been permitted, then fix the compiler and the problem will resolve itself the proper way. > >>>> @@ -731,6 +744,11 @@ static void init_amd(struct cpuinfo_x86 *c) >>>> else /* Implicily "=3D=3D 0x10 || >=3D 0x12" by being 64bit. */ >>>> amd_init_lfence(c); >>>> =20 >>>> + /* Probe for NSCB on Zen2 CPUs when not virtualised */ >>>> + if (!cpu_has_hypervisor && !cpu_has_nscb && c =3D=3D &boot_cpu_data = && >>>> + c->x86 =3D=3D 0x17 && c->x86_model >=3D 30 && c->x86_model <=3D = 0x5f) >>> DYM 0x30 here? >> 0x30, although it turns out that some of the mobile Zen2 CPUs exceed >> 0x60 in terms of model number. >> >> As Zen3 changes the family number to 0x19, I'd just drop the upper bound= . > Minor note: Even if it didn't, the !cpu_has_nscb would also be enough > to avoid the probing there. There is actually a problem.=C2=A0 From a non-AMD source, I've found the Sucor Z+ CPU which is a Fam17h Model 0x50 Zen1. So instead I'm going to recommend dropping all model checks and just keeping the family checks.=C2=A0 This will extend the probe function to Zen= 1 too, but it is once on boot, trivial in terms of complexity, and really not worth the time/effort it has taken to discover that the model list wasn't correct to start with. ~Andrew