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 for <linuxppc-dev@lists.ozlabs.org>; Wed,  4 Jul 2018 16:12:40 +1000 (AEST)
Message-ID: <de891d5858b4ea39aeac425fa13260ffd22f7753.camel@russell.cc>
Subject: Re: [PATCH 2/3] powerpc/powernv: DMA operations for discontiguous
 allocation
From: Russell Currey <ruscur@russell.cc>
To: linuxppc-dev@lists.ozlabs.org
Cc: benh@kernel.crashing.org, alistair@popple.id.au, aik@ozlabs.ru,
 tpearson@raptorengineering.com
Date: Wed, 04 Jul 2018 16:12:28 +1000
In-Reply-To: <20180629073437.4060-3-ruscur@russell.cc>
References: <20180629073437.4060-1-ruscur@russell.cc>
 <20180629073437.4060-3-ruscur@russell.cc>
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On Fri, 2018-06-29 at 17:34 +1000, Russell Currey wrote:

<snip>

> +		/*
> +		 * The TCE isn't being used, so let's try and
> allocate it.
> +		 * Bits 0 and 1 are read/write, and we use bit 2 as
> a "lock"
> +		 * bit.  This is to prevent any race where the value
> is set in
> +		 * the TCE table but the invalidate/mb() hasn't
> finished yet.
> +		 */
> +		entry = cpu_to_be64((addr - offset) | 7);
> +		ret = cmpxchg(&pe->tces[i], tce, entry);
> +		if (ret != tce) {
> +			/* conflict, start looking again just in
> case */
> +			i--;
> +			continue;
> +		}
> +		pnv_pci_phb3_tce_invalidate(pe, 0, 0, addr - offset,
> 1);

This is wrong and won't work outside of PHB3, will make a generic
handler

> +		mb();
> +		/* clear the lock bit now that we know it's active
> */
> +		ret = cmpxchg(&pe->tces[i], entry, cpu_to_be64((addr
> - offset) | 3));
> +		if (ret != entry) {
> +			/* conflict, start looking again just in
> case */
> +			i--;
> +			continue;
> +		}
> +
> +		return (i << phb->ioda.max_tce_order) | offset;
> +	}
> +	/* If we get here, the table must be full, so error out. */
> +	return -1ULL;
> +}
> +
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