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From: "Andrew Abbott" <andrew@mirx.dev>
To: u-boot@lists.denx.de
Cc: sjg@chromium.org
Subject: Re: [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64
Date: Sun, 12 Feb 2023 10:29:23 +1100	[thread overview]
Message-ID: <df2c4ab1-1c8a-4652-bfb1-a7e746b8c7a2@app.fastmail.com> (raw)
In-Reply-To: <20230107215731.484317-14-sjg@chromium.org>

On Sun, Jan 8, 2023, at 08:57, Simon Glass wrote:
> This board is useful for benchmarking overall U-Boot performance. Enable
> the bootstage feature so we get a report.
> 
> Since this returns to the boot rom before finishing executing
> board_init_r() in SPL, add a few bootstage calls so that we can collect
> timing from TPL.
> 
> For the stash region, use a portion of SRAM, 64KB below the stack top.
> This allows the TPL image to be up to nearly 120KB (it is typically about
> 64KB). SPL normally runs from SDRAM at 0, so can use the same stash
> region.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

> diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
> index 5b8d678f6bb..2f1ae156bd4 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
> CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
> CONFIG_ROCKCHIP_RK3399=y
> CONFIG_TARGET_ROCKPRO64_RK3399=y
> +CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e0000
> CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_SPL_SPI_FLASH_SUPPORT=y
> @@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800
> CONFIG_DEBUG_UART=y
> CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
> +CONFIG_BOOTSTAGE=y

Building from master commit a1e6b529e57c622e862e93fa6da03d9504565089 and copying u-boot-rockchip.bin to an SD card and booting from that on a RockPRO64 v2.1, I don't get past this:
(dirty because building on NixOS applies some patches)

>U-Boot TPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00)
>Channel 0: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>Channel 1: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>256B stride
>lpddr4_set_rate: change freq to 800MHz 1, 0
>Trying to boot from BOOTROM
>Returning to boot ROM...
>
>U-Boot SPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00 +0000)
>Trying to boot from MMC2

I bisected down to this patch. If I disable CONFIG_BOOTSTATE, I can boot. Is there something I need to do to successfully boot with bootstate enabled?

  parent reply	other threads:[~2023-02-11 23:29 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-07 21:57 [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
2023-01-07 21:57 ` [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass
2023-01-08 15:48   ` Simon Glass
2023-02-11 23:29   ` Andrew Abbott [this message]
2023-02-14  0:01     ` Simon Glass
2023-01-08  2:40 ` [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
  -- strict thread matches above, loose matches on Subject: below --
2022-12-22 21:14 [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass

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