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From: Suravee Suthikulanit <suravee.suthikulpanit@amd.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: <pbonzini@redhat.com>, <rkrcmar@redhat.com>, <bp@alien8.de>,
	<gleb@kernel.org>, <alex.williamson@redhat.com>,
	<kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<wei@redhat.com>, <sherry.hurwitz@amd.com>
Subject: Re: [PART2 RFC v1 1/9] iommu/amd: Detect and enable guest vAPIC support
Date: Thu, 2 Jun 2016 15:38:43 -0500	[thread overview]
Message-ID: <df9c87c7-b7d8-4de7-99a8-ad5ae133bf36@amd.com> (raw)
In-Reply-To: <20160509114927.GC13971@8bytes.org>

On 5/9/2016 6:49 AM, Joerg Roedel wrote:
> On Fri, Apr 08, 2016 at 07:49:22AM -0500, Suthikulpanit, Suravee wrote:
>> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>
>> This patch introduces a new IOMMU driver parameter, amd_iommu_guest_ir,
>> which can be used to specify different interrupt remapping mode for
>> passthrough devices to VM guest:
>>     * legacy: Legacy interrupt remapping mode (w/ 32-bit IRTE)
>>     * ga    : Guest vAPIC interrupt remapping mode (w/ 128-bit IRTE)
>>
>> Note that the GA mode also supports legacy interrupt remapping
>> for non-passthrough devices with the 128-bit IRTE.
>
> Does this need to be under user control? The code can just check what
> the hardware supports and use the 128bit IRTEs if supported, no?
>
> 	Joerg

It does not need to be signified by user.

Currently, if the MMIO Offset 30h[GASup] bit (of IOMMU Extended Feature 
Register) is set, the driver should default to using the 128bit IRTE by 
setting MMIO Offset 0018h[GAEn] bit (of IOMMU Control Register). The 
default is also enabling GA mode (by setting MMIO 0018h[GAEn] if MMIO 
0030h[GASup] is set).

However, if SVM AVIC is not enabled, or if the AVIC HW cannot support 
the type of interrupt (e.g. multicast/broadcast), it falls back to use 
legacy  interrupt remapping mode w/ 128-bit IRTE.

This option is intended for the case when we want to force IOMMU to use 
legacy interrupt remapping (hence no need for 128-bit IRTE).

I will improve on the documentation in the next patch series.

Thanks,
Suravee

  reply	other threads:[~2016-06-02 20:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-08 12:49 [PART2 RFC v1 0/9] iommu/AMD: Introduce IOMMU AVIC support Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 1/9] iommu/amd: Detect and enable guest vAPIC support Suravee Suthikulpanit
2016-05-09 11:49   ` Joerg Roedel
2016-06-02 20:38     ` Suravee Suthikulanit [this message]
2016-04-08 12:49 ` [PART2 RFC v1 2/9] iommu/amd: Add data structure for " Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 3/9] iommu/amd: Detect and initialize guest vAPIC log Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 4/9] iommu/amd: Adding GALOG interrupt handler Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 5/9] iommu/amd: Introduce amd_iommu_update_ga() Suravee Suthikulpanit
2016-04-13 17:06   ` Radim Krčmář
2016-06-09 23:59     ` Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 6/9] iommu/amd: Implements irq_set_vcpu_affinity hook to setup GA mode for pass-through devices Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 7/9] svm: Introduce AMD IOMMU avic_ga_log_notifier Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 8/9] svm: Implements update_pi_irte hook to setup posted interrupt Suravee Suthikulpanit
2016-04-08 12:49 ` [PART2 RFC v1 9/9] svm: Update AMD IOMMU IRTE with vcpu scheduling information when enable AVIC Suravee Suthikulpanit

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