From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Laszlo Ersek <lersek@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PULL 08/10] target/arm: Conditionalize some asserts on aarch32 support
Date: Tue, 16 Jul 2019 22:10:21 +0200 [thread overview]
Message-ID: <dfeab9fd-7ee1-01f2-dd38-cba449b1de63@redhat.com> (raw)
In-Reply-To: <8d06b8f2-7ee8-a77a-81d7-3219d5e43c45@redhat.com>
On 7/16/19 8:42 PM, Laszlo Ersek wrote:
> On 07/16/19 18:59, Peter Maydell wrote:
>> On Tue, 16 Jul 2019 at 17:51, Laszlo Ersek <lersek@redhat.com> wrote:
>>> The issue still reproduces, so it makes sense for me to look at the host
>>> kernel version... Well, I'm afraid it won't help much, for an upstream
>>> investigation:
>>>
>>> 4.14.0-115.8.2.el7a.aarch64
>>>
>>> This is the latest released kernel from "Red Hat Enterprise Linux for
>>> ARM 64 7".
>>
>> OK. (I'm using 4.15.0-51-generic from ubuntu).
>>
>> Could you run with QEMU under gdb, and when it hits the
>> assertion go back up a stack frame to the arm_cpu_realizefn()
>> frame, and then "print /x cpu->isar" ? That should show us
>> what we think we've got as ID registers from the kernel.
>> (You might need to build QEMU with --enable-debug to get
>> useful enough debug info to do that, not sure.)
>
> (My qemu build script always builds QEMU in two configs, the difference
> being --prefix and --enable-debug.)
>
> This is what I got:
>
> (gdb) frame 4
> #4 0x00000000006a063c in arm_cpu_realizefn (dev=0x1761140,
> errp=0xffffffffe540)
> at .../qemu/target/arm/cpu.c:1159
> 1159 assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
> (gdb) print /x cpu->isar
> $1 = {id_isar0 = 0x0, id_isar1 = 0x0, id_isar2 = 0x0, id_isar3 = 0x0,
> id_isar4 = 0x0, id_isar5 = 0x0, id_isar6 = 0x0, mvfr0 = 0x0,
> mvfr1 = 0x0, mvfr2 = 0x0, id_aa64isar0 = 0x0, id_aa64isar1 = 0x0,
> id_aa64pfr0 = 0x11, id_aa64pfr1 = 0x0, id_aa64mmfr0 = 0x0,
> id_aa64mmfr1 = 0x0}
For ISAR0, DIVIDE=0
so cpu_isar_feature(arm_div, cpu)=false
For AA64PFR0, EL0=1, EL1=1.
EL0 = 1: EL0 can be executed in AArch64 state only.
EL1 = 1: EL1 can be executed in AArch64 state only.
so cpu_isar_feature(aa64_aa32, cpu)=false
then no_aa32=true
The commit description is "on a host that doesn't support aarch32 mode
at all, neither arm_div nor jazelle will be supported either."
Shouldn't we use a slighly different logic? Such:
- assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
+ assert(no_aa32 && !cpu_isar_feature(arm_div, cpu));
next prev parent reply other threads:[~2019-07-16 20:10 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-02 17:16 [Qemu-devel] [PULL v3 00/10] target-arm queue Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 01/10] hw/arm/virt: Set VIRT_COMPAT_3_0 compat Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 02/10] hw/char: Implement nRF51 SoC UART Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 03/10] hw/arm/nrf51_soc: Connect UART to nRF51 SoC Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 04/10] tests/boot-serial-test: Add microbit board testcase Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 05/10] MAINTAINERS: Remove bouncing email in ARM ACPI Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 06/10] strongarm: mask off high[31:28] bits from dir and state registers Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 07/10] hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 08/10] target/arm: Conditionalize some asserts on aarch32 support Peter Maydell
2019-05-24 12:33 ` Laszlo Ersek
2019-05-24 12:45 ` Laszlo Ersek
2019-05-24 13:11 ` Philippe Mathieu-Daudé
2019-07-16 12:03 ` Peter Maydell
2019-07-16 14:02 ` Richard Henderson
2019-07-16 14:18 ` Peter Maydell
2019-07-16 15:04 ` Richard Henderson
2019-07-16 16:50 ` Laszlo Ersek
2019-07-16 16:59 ` Peter Maydell
2019-07-16 18:42 ` Laszlo Ersek
2019-07-16 20:10 ` Philippe Mathieu-Daudé [this message]
2019-07-17 8:36 ` Laszlo Ersek
2019-07-17 9:22 ` Laszlo Ersek
2019-07-17 9:24 ` Laszlo Ersek
2019-07-17 12:49 ` Laszlo Ersek
2019-07-17 12:53 ` Laszlo Ersek
2019-07-17 13:36 ` Philippe Mathieu-Daudé
2019-07-17 13:46 ` Peter Maydell
2019-07-17 15:08 ` Laszlo Ersek
2019-07-18 12:30 ` Peter Maydell
2019-07-18 19:07 ` Laszlo Ersek
2019-07-17 13:45 ` Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 09/10] hw/arm: versal: Add a model of Xilinx Versal SoC Peter Maydell
2018-11-02 17:16 ` [Qemu-devel] [PULL 10/10] hw/arm: versal: Add a virtual Xilinx Versal board Peter Maydell
2018-12-04 10:28 ` Peter Maydell
2018-12-12 22:05 ` Edgar E. Iglesias
2022-01-27 13:10 ` Peter Maydell
2022-01-30 10:33 ` Edgar E. Iglesias
2018-11-02 18:22 ` [Qemu-devel] [PULL v3 00/10] target-arm queue Peter Maydell
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