From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F5E0C433F5 for ; Mon, 27 Dec 2021 06:56:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235408AbhL0G4M (ORCPT ); Mon, 27 Dec 2021 01:56:12 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:12930 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229490AbhL0G4L (ORCPT ); Mon, 27 Dec 2021 01:56:11 -0500 Received: from [10.18.29.173] (10.18.29.173) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 27 Dec 2021 14:56:09 +0800 Message-ID: Date: Mon, 27 Dec 2021 14:56:09 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: Re: [PATCH 3/3] tty: serial: meson: add UART driver compatible with S4 SoC on-chip Content-Language: en-US To: Martin Blumenstingl CC: , , , , Greg Kroah-Hartman , Jiri Slaby , Neil Armstrong , Kevin Hilman , Jerome Brunet References: <20211221071634.25980-1-yu.tu@amlogic.com> <20211221071634.25980-4-yu.tu@amlogic.com> From: Yu Tu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.29.173] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, Thank you very much for your reply. On 2021/12/25 1:25, Martin Blumenstingl wrote: > [ EXTERNAL EMAIL ] > > Hello, > > On Tue, Dec 21, 2021 at 8:17 AM Yu Tu wrote: >> >> The S4 SoC on-chip UART uses a 12M clock as the clock source for >> calculating the baud rate of the UART. But previously, chips used 24M or >> other clock sources. So add this change. The specific clock source is >> determined by chip design. > Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL? > If there's still a 24MHz XTAL then I think this description is not > correct - at least based on how I understand the UART controller. > The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode). This register description is the same as the G12A and G12B you know. > SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in > the UART controller IP and an external 24MHz XTAL. > This was not configurable, so the clock for all baud-rates had to be > derived from an 8MHz (24MHz divided by 3) clock. > > With the A311D (G12B, which is still using an external 24MHz XTAL) SoC > the UART controller gained two new bits - with configurable dividers - > according to the public datasheets: > UART_EE_A_REG5[26]: > - 0x0: divide the input clock by 3 (meaning: this internally works > with an 8MHz clock) > - 0x1: use the input clock directly without further division (meaning: > this internally work with an 24MHz clock) > UART_EE_A_REG5[27]: > - 0x0: use the clock as configured in UART_EE_A_REG5[26] > - 0x1: divide the input clock by 2 (meaning: this internally works > with an 12MHz clock) > > While writing this email I did some investigation and found that > UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM > SoCs. > So this probably has been introduced with the GXL generation (and thus > is missing on GXBB and earlier SoCs). > Also UART_EE_A_REG5[27] seems to have been introduced with the G12A > generation of SoCs (not surprising since G12A and G12B peripherals are > very similar). > > Does the UART controller not work with divide-by-3 (as we have it > today) or are these configurable dividers to reduce jitter? > The UART controller can work with divide-by-3. The chip history as you described above, the current reason for using 12MHz clock is really what you call reduce jitter. The UART mainly connects to Bluetooth and uses typical baud rates of 2Mhz, 3MHz and 4MHz, so 12MHz is used as the clock source. > > Best regards, > Martin > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65779C433F5 for ; Mon, 27 Dec 2021 06:56:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TLuuieB2UmlSEiMFmrjkI+VENqDPGAMNj3kxgi2cFXA=; b=0nkj++bP7wGhxs maf5qCROD+Mxs0qlC+/vecC9A4bs41Kg2bO3F7yRgQneFislWaQDrMGhSiIOdjmIaRQG4E5q6S707 +MtaLPn53rMaHFyBlxuJvZNNo8n4Sxidt/xx/Pi1jZv8VGDm9QunO3Id+bKFB49NtFKtcfmWirgZ4 2P28kfdZCl5SiDw8tO79lzviLNZbEMJQsulQ0uyDJItk4h3sEv26IPo+X9jlYCShN+xfEVmRDV56E EhKZgnvFUOMmoukOOs7x0gNU05BQFdDNEScnpt2eC0dqfDDfcs8R+sH0//wJJC3/tEWIzIOFk+6co ChV3g88+zeEMCDzBxp0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n1jvo-00GHha-OQ; Mon, 27 Dec 2021 06:56:28 +0000 Received: from mail-sh.amlogic.com ([58.32.228.43]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n1jvc-00GHfS-Du; Mon, 27 Dec 2021 06:56:17 +0000 Received: from [10.18.29.173] (10.18.29.173) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 27 Dec 2021 14:56:09 +0800 Message-ID: Date: Mon, 27 Dec 2021 14:56:09 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: Re: [PATCH 3/3] tty: serial: meson: add UART driver compatible with S4 SoC on-chip Content-Language: en-US To: Martin Blumenstingl CC: , , , , Greg Kroah-Hartman , Jiri Slaby , Neil Armstrong , Kevin Hilman , Jerome Brunet References: <20211221071634.25980-1-yu.tu@amlogic.com> <20211221071634.25980-4-yu.tu@amlogic.com> From: Yu Tu In-Reply-To: X-Originating-IP: [10.18.29.173] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211226_225616_530296_96D79FF0 X-CRM114-Status: GOOD ( 22.94 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Martin, Thank you very much for your reply. On 2021/12/25 1:25, Martin Blumenstingl wrote: > [ EXTERNAL EMAIL ] > > Hello, > > On Tue, Dec 21, 2021 at 8:17 AM Yu Tu wrote: >> >> The S4 SoC on-chip UART uses a 12M clock as the clock source for >> calculating the baud rate of the UART. But previously, chips used 24M or >> other clock sources. So add this change. The specific clock source is >> determined by chip design. > Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL? > If there's still a 24MHz XTAL then I think this description is not > correct - at least based on how I understand the UART controller. > The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode). This register description is the same as the G12A and G12B you know. > SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in > the UART controller IP and an external 24MHz XTAL. > This was not configurable, so the clock for all baud-rates had to be > derived from an 8MHz (24MHz divided by 3) clock. > > With the A311D (G12B, which is still using an external 24MHz XTAL) SoC > the UART controller gained two new bits - with configurable dividers - > according to the public datasheets: > UART_EE_A_REG5[26]: > - 0x0: divide the input clock by 3 (meaning: this internally works > with an 8MHz clock) > - 0x1: use the input clock directly without further division (meaning: > this internally work with an 24MHz clock) > UART_EE_A_REG5[27]: > - 0x0: use the clock as configured in UART_EE_A_REG5[26] > - 0x1: divide the input clock by 2 (meaning: this internally works > with an 12MHz clock) > > While writing this email I did some investigation and found that > UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM > SoCs. > So this probably has been introduced with the GXL generation (and thus > is missing on GXBB and earlier SoCs). > Also UART_EE_A_REG5[27] seems to have been introduced with the G12A > generation of SoCs (not surprising since G12A and G12B peripherals are > very similar). > > Does the UART controller not work with divide-by-3 (as we have it > today) or are these configurable dividers to reduce jitter? > The UART controller can work with divide-by-3. The chip history as you described above, the current reason for using 12MHz clock is really what you call reduce jitter. The UART mainly connects to Bluetooth and uses typical baud rates of 2Mhz, 3MHz and 4MHz, so 12MHz is used as the clock source. > > Best regards, > Martin > _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3A74C433F5 for ; Mon, 27 Dec 2021 06:57:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ieOts1xH2YRJAwPwy/kdhM52hrhdg13m55Goe8SfwDw=; b=MHmbcA6BvLqIIk IaVrKqm6N9CXozZBu6wd7bZ75m/CH4eg7rqstlJDHz1jMaOjFc6IEUz4LFHwMNtbMs+x3+i8Hrl3U Fckhy5vJwT/T0+mD1dCx+GvI4qvBjM65IW8vVI7lzArGy0ulzb1F9ogJumEXkLDCLBsJk6P4n8kzC rSeQQ+IbyYOxpakpPd7iGHpkB0QjcU3UbgRrhjyTpH+ITpdP3BVy1KZ+03fNAXaPKlPcmx/0nFQ1Q 0evqG5ADReFYFbEpeAtLJP1qTuoYpkwRB4BVLi2SG0rZnva0alZ4VflKetwKQ9YdlHyHeEdoJWXrr L7E0sSVNcT7qXhRlSynw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n1jvg-00GHgg-ES; Mon, 27 Dec 2021 06:56:20 +0000 Received: from mail-sh.amlogic.com ([58.32.228.43]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n1jvc-00GHfS-Du; Mon, 27 Dec 2021 06:56:17 +0000 Received: from [10.18.29.173] (10.18.29.173) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 27 Dec 2021 14:56:09 +0800 Message-ID: Date: Mon, 27 Dec 2021 14:56:09 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: Re: [PATCH 3/3] tty: serial: meson: add UART driver compatible with S4 SoC on-chip Content-Language: en-US To: Martin Blumenstingl CC: , , , , Greg Kroah-Hartman , Jiri Slaby , Neil Armstrong , Kevin Hilman , Jerome Brunet References: <20211221071634.25980-1-yu.tu@amlogic.com> <20211221071634.25980-4-yu.tu@amlogic.com> From: Yu Tu In-Reply-To: X-Originating-IP: [10.18.29.173] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211226_225616_530296_96D79FF0 X-CRM114-Status: GOOD ( 22.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Martin, Thank you very much for your reply. On 2021/12/25 1:25, Martin Blumenstingl wrote: > [ EXTERNAL EMAIL ] > > Hello, > > On Tue, Dec 21, 2021 at 8:17 AM Yu Tu wrote: >> >> The S4 SoC on-chip UART uses a 12M clock as the clock source for >> calculating the baud rate of the UART. But previously, chips used 24M or >> other clock sources. So add this change. The specific clock source is >> determined by chip design. > Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL? > If there's still a 24MHz XTAL then I think this description is not > correct - at least based on how I understand the UART controller. > The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode). This register description is the same as the G12A and G12B you know. > SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in > the UART controller IP and an external 24MHz XTAL. > This was not configurable, so the clock for all baud-rates had to be > derived from an 8MHz (24MHz divided by 3) clock. > > With the A311D (G12B, which is still using an external 24MHz XTAL) SoC > the UART controller gained two new bits - with configurable dividers - > according to the public datasheets: > UART_EE_A_REG5[26]: > - 0x0: divide the input clock by 3 (meaning: this internally works > with an 8MHz clock) > - 0x1: use the input clock directly without further division (meaning: > this internally work with an 24MHz clock) > UART_EE_A_REG5[27]: > - 0x0: use the clock as configured in UART_EE_A_REG5[26] > - 0x1: divide the input clock by 2 (meaning: this internally works > with an 12MHz clock) > > While writing this email I did some investigation and found that > UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM > SoCs. > So this probably has been introduced with the GXL generation (and thus > is missing on GXBB and earlier SoCs). > Also UART_EE_A_REG5[27] seems to have been introduced with the G12A > generation of SoCs (not surprising since G12A and G12B peripherals are > very similar). > > Does the UART controller not work with divide-by-3 (as we have it > today) or are these configurable dividers to reduce jitter? > The UART controller can work with divide-by-3. The chip history as you described above, the current reason for using 12MHz clock is really what you call reduce jitter. The UART mainly connects to Bluetooth and uses typical baud rates of 2Mhz, 3MHz and 4MHz, so 12MHz is used as the clock source. > > Best regards, > Martin > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel