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From: Andrew Cooper <amc96@srcf.net>
To: Jan Beulich <jbeulich@suse.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH] x86/Intel: use CPUID bit to determine PPIN availability
Date: Tue, 18 Jan 2022 20:28:40 +0000	[thread overview]
Message-ID: <e076f39f-7364-b9a2-ba0c-fd84e7f19ab0@srcf.net> (raw)
In-Reply-To: <239d8868-0c8a-b512-a2bf-3e91689a8218@suse.com>

On 17/01/2022 15:30, Jan Beulich wrote:
> As of SDM revision 076 there is a CPUID bit for this functionality. Use
> it to amend the existing model-based logic.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

https://lore.kernel.org/lkml/20220107225442.1690165-1-tony.luck@intel.com/T/#u
suggests that Sapphire Rapids also needs the model specific treatment.

I agree with the "only-expose-on-error" observation, so perhaps we ought
to make these details available to the hardware domain in a suitable form.

~Andrew


  parent reply	other threads:[~2022-01-18 20:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-17 15:30 [PATCH] x86/Intel: use CPUID bit to determine PPIN availability Jan Beulich
2022-01-18 12:18 ` Andrew Cooper
2022-01-18 13:27   ` Jan Beulich
2022-01-18 20:28 ` Andrew Cooper [this message]
2022-01-19  7:15   ` Jan Beulich

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