All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-23  3:05 vathsala nagaraju
  2018-05-23  3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-23  3:05 UTC (permalink / raw)
  To: intel-gfx
  Cc: Jani Nikula, Maulik V Vaghela, Dhinakaran Pandiyan, Rodrigo Vivi,
	Puthikorn Voravootivat

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us.
v6: Jani
    Handle default first and then fall through for case 2.
v7: Rodrigo
    Apply this change for IS_GEN9_BC and vbt version > 209
v8: Puthik
    Add new function vbt_psr_to_us.
v9: Jani
    Change to v7 version as it's more readable.
    DK
    add comment /*fall through*/ after case2.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 48 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++----------------
 4 files changed, 72 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..dcfa791 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb..513b4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4088,10 +4088,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 54270bd..417f656 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);
+			/* fallthrough */
+		case 2:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp2_tp3_wakeup_time);
+			/* fallthrough */
+		case 2:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2f..d64f039 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10)
  2018-05-23  3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
@ 2018-05-23  3:24 ` Patchwork
  2018-05-23  3:45 ` ✗ Fi.CI.BAT: failure " Patchwork
  2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
  2 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2018-05-23  3:24 UTC (permalink / raw)
  To: vathsala nagaraju; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev10)
URL   : https://patchwork.freedesktop.org/series/41289/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
46c7737a0d9a drm/i915/psr: vbt change for psr
-:85: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#85: FILE: drivers/gpu/drm/i915/i915_reg.h:4091:
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
                                  	  ^

-:86: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#86: FILE: drivers/gpu/drm/i915/i915_reg.h:4092:
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
                                  	  ^

-:87: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:4093:
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
                                   	  ^

-:88: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#88: FILE: drivers/gpu/drm/i915/i915_reg.h:4094:
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
                                 	  ^

-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/intel_bios.c:704:
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);

-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/intel_bios.c:723:
+			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp2_tp3_wakeup_time);

total: 0 errors, 0 warnings, 6 checks, 135 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* ✗ Fi.CI.BAT: failure for drm/i915/psr: vbt change for psr (rev10)
  2018-05-23  3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
  2018-05-23  3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
@ 2018-05-23  3:45 ` Patchwork
  2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
  2 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2018-05-23  3:45 UTC (permalink / raw)
  To: vathsala nagaraju; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev10)
URL   : https://patchwork.freedesktop.org/series/41289/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4222 -> Patchwork_9090 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9090 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9090, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/10/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9090:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       PASS -> FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_9090 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    
    ==== Possible fixes ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-skl-6770hq:      FAIL (fdo#103928, fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-FAIL (fdo#106103, fdo#102614) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (44 -> 39) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4222 -> Patchwork_9090

  CI_DRM_4222: e783c316409040dab016975896e718fc36cbd8e6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4492: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9090: 46c7737a0d9a5e7256fa23032816fe97c2059da0 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4492: 53aa71861efe0095405673c98ff15f6dcf268901 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

46c7737a0d9a drm/i915/psr: vbt change for psr

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9090/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-23  3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
  2018-05-23  3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
  2018-05-23  3:45 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-05-23 10:03 ` Jani Nikula
  2018-05-23 12:55   ` Nagaraju, Vathsala
  2 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-05-23 10:03 UTC (permalink / raw)
  To: vathsala nagaraju, intel-gfx
  Cc: Maulik V Vaghela, Dhinakaran Pandiyan, Rodrigo Vivi,
	Puthikorn Voravootivat

On Wed, 23 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to gen9_bc and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us.
> v6: Jani
>     Handle default first and then fall through for case 2.
> v7: Rodrigo
>     Apply this change for IS_GEN9_BC and vbt version > 209
> v8: Puthik
>     Add new function vbt_psr_to_us.
> v9: Jani
>     Change to v7 version as it's more readable.
>     DK
>     add comment /*fall through*/ after case2.

Why did you send this again? Did you change something? I already
reviewed the version from yesterday.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
@ 2018-05-23 12:55   ` Nagaraju, Vathsala
  2018-05-23 13:10     ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-23 12:55 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan,
	Rodrigo Vivi



On 5/23/2018 3:33 PM, Jani Nikula wrote:
> On Wed, 23 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>      move the 165 version check to intel_bios.c
>> v3: Jani
>>      Move the abstraction to intel_bios.
>> v4: Jani
>>      Rename tp*_wakeup_time to have "us" suffix.
>>      For values outside range[0-3],default to max 2500us.
>>      Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>>      Handle option 2 in default condition.
>>      Print oustide range value.
>>      For negetive values default to 2500us.
>> v6: Jani
>>      Handle default first and then fall through for case 2.
>> v7: Rodrigo
>>      Apply this change for IS_GEN9_BC and vbt version > 209
>> v8: Puthik
>>      Add new function vbt_psr_to_us.
>> v9: Jani
>>      Change to v7 version as it's more readable.
>>      DK
>>      add comment /*fall through*/ after case2.
> Why did you send this again? Did you change something? I already
> reviewed the version from yesterday.
no code change, added only  rb tag by you and resent it.
> BR,
> Jani.
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-23 12:55   ` Nagaraju, Vathsala
@ 2018-05-23 13:10     ` Jani Nikula
  0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-05-23 13:10 UTC (permalink / raw)
  To: Nagaraju, Vathsala, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan,
	Rodrigo Vivi

On Wed, 23 May 2018, "Nagaraju, Vathsala" <vathsala.nagaraju@intel.com> wrote:
> On 5/23/2018 3:33 PM, Jani Nikula wrote:
>> Why did you send this again? Did you change something? I already
>> reviewed the version from yesterday.
> no code change, added only  rb tag by you and resent it.

For future reference, you should *not* resend for that.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-22 12:46 ` Jani Nikula
@ 2018-05-24 13:04   ` Jani Nikula
  0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-05-24 13:04 UTC (permalink / raw)
  To: vathsala nagaraju, dhinakaran.pandiyan
  Cc: intel-gfx, Rodrigo Vivi, Puthikorn Voravootivat, Maulik V Vaghela

On Tue, 22 May 2018, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 22 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>     move the 165 version check to intel_bios.c
>> v3: Jani
>>     Move the abstraction to intel_bios.
>> v4: Jani
>>     Rename tp*_wakeup_time to have "us" suffix.
>>     For values outside range[0-3],default to max 2500us.
>>     Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>>     Handle option 2 in default condition.
>>     Print oustide range value.
>>     For negetive values default to 2500us.
>> v6: Jani
>>     Handle default first and then fall through for case 2.
>> v7: Rodrigo
>>     Apply this change for IS_GEN9_BC and vbt version > 209
>> v8: Puthik
>>     Add new function vbt_psr_to_us.
>> v9: Jani
>>     Change to v7 version as it's more readable.
>>     DK
>>     add comment /*fall through*/ after case2.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Puthikorn Voravootivat <puthik@chromium.org>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

And pushed to dinq. Thanks for the patch.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>  drivers/gpu/drm/i915/intel_bios.c | 48 +++++++++++++++++++++++++++++++++++++--
>>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++----------------
>>  4 files changed, 72 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index e33c380..dcfa791 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>  		bool require_aux_wakeup;
>>  		int idle_frames;
>>  		enum psr_lines_to_wait lines_to_wait;
>> -		int tp1_wakeup_time;
>> -		int tp2_tp3_wakeup_time;
>> +		int tp1_wakeup_time_us;
>> +		int tp2_tp3_wakeup_time_us;
>>  	} psr;
>>  
>>  	struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 196a0eb..513b4a4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4088,10 +4088,10 @@ enum {
>>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 54270bd..417f656 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>  		break;
>>  	}
>>  
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	/*
>> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>> +	 * Old decimal value is wake up time in multiples of 100 us.
>> +	 */
>> +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
>> +		switch (psr_table->tp1_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		default:
>> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>> +					psr_table->tp1_wakeup_time);
>> +			/* fallthrough */
>> +		case 2:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
>> +			break;
>> +		}
>> +
>> +		switch (psr_table->tp2_tp3_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		default:
>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>> +					psr_table->tp2_tp3_wakeup_time);
>> +			/* fallthrough */
>> +		case 2:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
>> +		break;
>> +		}
>> +	} else {
>> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
>> +	}
>>  }
>>  
>>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index db27f2f..d64f039 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>  	if (dev_priv->psr.link_standby)
>>  		val |= EDP_PSR_LINK_STANDBY;
>>  
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>> +		val |=  EDP_PSR_TP1_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>  		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP1_TIME_500us;
>>  	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>  
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>  	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>  
>>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  
>>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>  
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>> +		val |= EDP_PSR2_TP2_TIME_50us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>> +		val |= EDP_PSR2_TP2_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>  	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>  
>>  	I915_WRITE(EDP_PSR2_CTL, val);
>>  }

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-22  9:27 vathsala nagaraju
@ 2018-05-22 12:46 ` Jani Nikula
  2018-05-24 13:04   ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-05-22 12:46 UTC (permalink / raw)
  To: vathsala nagaraju, dhinakaran.pandiyan
  Cc: intel-gfx, Rodrigo Vivi, Puthikorn Voravootivat, Maulik V Vaghela

On Tue, 22 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to gen9_bc and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us.
> v6: Jani
>     Handle default first and then fall through for case 2.
> v7: Rodrigo
>     Apply this change for IS_GEN9_BC and vbt version > 209
> v8: Puthik
>     Add new function vbt_psr_to_us.
> v9: Jani
>     Change to v7 version as it's more readable.
>     DK
>     add comment /*fall through*/ after case2.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Puthikorn Voravootivat <puthik@chromium.org>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 48 +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++----------------
>  4 files changed, 72 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e33c380..dcfa791 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb..513b4a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4088,10 +4088,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bd..417f656 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +			/* fallthrough */
> +		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp2_tp3_wakeup_time);
> +			/* fallthrough */
> +		case 2:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2f..d64f039 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-22  9:27 vathsala nagaraju
  2018-05-22 12:46 ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-22  9:27 UTC (permalink / raw)
  To: dhinakaran.pandiyan, jani.nikula
  Cc: Jani Nikula, intel-gfx, Rodrigo Vivi, Puthikorn Voravootivat,
	Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us.
v6: Jani
    Handle default first and then fall through for case 2.
v7: Rodrigo
    Apply this change for IS_GEN9_BC and vbt version > 209
v8: Puthik
    Add new function vbt_psr_to_us.
v9: Jani
    Change to v7 version as it's more readable.
    DK
    add comment /*fall through*/ after case2.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 48 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++----------------
 4 files changed, 72 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..dcfa791 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb..513b4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4088,10 +4088,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 54270bd..417f656 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);
+			/* fallthrough */
+		case 2:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp2_tp3_wakeup_time);
+			/* fallthrough */
+		case 2:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2f..d64f039 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-22  8:05     ` Jani Nikula
@ 2018-05-22  8:36       ` Nagaraju, Vathsala
  0 siblings, 0 replies; 45+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-22  8:36 UTC (permalink / raw)
  To: Jani Nikula, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan



On 5/22/2018 1:35 PM, Jani Nikula wrote:
> On Tue, 22 May 2018, "Nagaraju, Vathsala" <vathsala.nagaraju@intel.com> wrote:
>> On 5/18/2018 3:01 PM, Jani Nikula wrote:
>>> On Fri, 18 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>>>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>>>
>>>> For psr block #9, the vbt description has moved to options [0-3] for
>>>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>>>> structure. Since spec does not  mention from which VBT version this
>>>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>>>> to change for all the platforms.
>>>>
>>>> There is RCR inplace for GOP team to  provide the version number
>>>> to make generic change. Since Kabylake with bdb version 209 is having this
>>>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>>>
>>>> Tested on skl(bdb version 203,without options) and
>>>> kabylake(bdb version 209,212) having new options.
>>>>
>>>> bspec 20131
>>>>
>>>> v2: (Jani and Rodrigo)
>>>>       move the 165 version check to intel_bios.c
>>>> v3: Jani
>>>>       Move the abstraction to intel_bios.
>>>> v4: Jani
>>>>       Rename tp*_wakeup_time to have "us" suffix.
>>>>       For values outside range[0-3],default to max 2500us.
>>>>       Old decimal value was wake up time in multiples of 100us.
>>>> v5: Jani and Rodrigo
>>>>       Handle option 2 in default condition.
>>>>       Print oustide range value.
>>>>       For negetive values default to 2500us.
>>>> v6: Jani
>>>>       Handle default first and then fall through for case 2.
>>>> v7: Rodrigo
>>>>       Apply this change for IS_GEN9_BC and vbt version > 209.
>>>> v8: Puthik
>>>>       add new function vbt_psr_to_us.
>>>>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Cc: Puthikorn Voravootivat <puthik@chromium.org>
>>>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>>
>>>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>>>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>>>    drivers/gpu/drm/i915/i915_reg.h   |  8 ++++----
>>>>    drivers/gpu/drm/i915/intel_bios.c | 38 ++++++++++++++++++++++++++++++++++++--
>>>>    drivers/gpu/drm/i915/intel_psr.c  | 39 ++++++++++++++++++++-------------------
>>>>    4 files changed, 62 insertions(+), 27 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index e33c380..dcfa791 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>>>    		bool require_aux_wakeup;
>>>>    		int idle_frames;
>>>>    		enum psr_lines_to_wait lines_to_wait;
>>>> -		int tp1_wakeup_time;
>>>> -		int tp2_tp3_wakeup_time;
>>>> +		int tp1_wakeup_time_us;
>>>> +		int tp2_tp3_wakeup_time_us;
>>>>    	} psr;
>>>>    
>>>>    	struct {
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index 196a0eb..513b4a4 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -4088,10 +4088,10 @@ enum {
>>>>    #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>>>    #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>>>    #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>>>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>>>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>>>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>>>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>>>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>>>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>>>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>>>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>>>    #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>>>    #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>>>    #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>>>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>>>> index 54270bd..5d8c29f 100644
>>>> --- a/drivers/gpu/drm/i915/intel_bios.c
>>>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>>>> @@ -647,12 +647,26 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>>    	}
>>>>    }
>>>>    
>>>> +static int vbt_psr_to_us(bool is_waketime_options, int vbt_value)
>>>> +{
>>>> +	if (is_waketime_options) {
>>>> +		int waketime_map[] = {500, 100, 2500, 0};
>>>> +		/* Reset to value 2 = 2500us for outside range [0-3] */
>>>> +		if (vbt_value < 0 || vbt_value > 3)
>>>> +			vbt_value = 2;
>>>> +		return waketime_map[vbt_value];
>>>> +	} else {
>>>> +		return vbt_value * 100;
>>>> +	}
>>>> +}
>>>> +
>>>>    static void
>>>>    parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>>>    {
>>>>    	const struct bdb_psr *psr;
>>>>    	const struct psr_table *psr_table;
>>>>    	int panel_type = dev_priv->vbt.panel_type;
>>>> +	bool is_waketime_options = false;
>>>>    
>>>>    	psr = find_section(bdb, BDB_PSR);
>>>>    	if (!psr) {
>>>> @@ -688,8 +702,28 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>>    		break;
>>>>    	}
>>>>    
>>>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>>>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>>>> +	/*
>>>> +	 * New psr wake options 0=500us, 1=100us, 2=2500us, 3=0us
>>>> +	 * Old decimal value is wake up time in multiples of 100 us.
>>>> +	 * TODO: add other platforms having new psr options.
>>>> +	 */
>>>> +	is_waketime_options = ((bdb->version >= 209) && IS_GEN9_BC(dev_priv));
>>>> +	if (is_waketime_options) {
>>>> +		/* Reset to value 2 = 2500us for outside range [0-3] */
>>>> +		if (psr_table->tp1_wakeup_time < 0 ||
>>>> +			psr_table->tp1_wakeup_time > 3) {
>>>> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>>>> +					psr_table->tp1_wakeup_time);
>>>> +		}
>>>> +		if (psr_table->tp2_tp3_wakeup_time < 0 ||
>>>> +			psr_table->tp2_tp3_wakeup_time > 3) {
>>>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>>>> +					psr_table->tp2_tp3_wakeup_time);
>>>> +		}
>>>> +	}
>>> Why did you take something that was obvious at a glance and turn it into
>>> this complicated mess?
>> Which parts you find it complicated?
> This splits and duplicates the checks for valid values to two places
> that you need to keep in sync as the spec inevitably gets updated. The
> responsibilities between the caller and the callee are unclear, which is
> just silly for such a small amount of code. You have checks for negative
> values but the field is unsigned. I could go on.
>
> The bottom line is that the spec makes a fundamentally simple thing
> unnecessarily complicated, and it's our job to implement that in a way
> that makes it again simple for human beings. That's the primary goal,
> make the code easy for the reader. We have enough hard things, we should
> not have to stop and think about simple things.
>
> BR,
> Jani.
>
Thanks, will stick with the previous version (v7)
>> new version is
>> 1) check if vbt data is  wake_options
>> 2) if wake options , then  if out of range print the message
>> 3)then  for both new and old version , we call vbt_psr_to_us , which
>> takes care of the mapping and conversion to us.
>>> I'd rather take the previous version, even with the duplication.
>> puthik suggested to use vbt_psr_to_us to remove code duplication.
>> Puthik , is it okay if  we switch to v7 version?
>>
>>> BR,
>>> Jani.
>>>
>>>
>>>> +
>>>> +	dev_priv->vbt.psr.tp1_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp1_wakeup_time);
>>>> +	dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp2_tp3_wakeup_time);
>>>>    }
>>>>    
>>>>    static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>>> index db27f2f..d64f039 100644
>>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>>>    	if (dev_priv->psr.link_standby)
>>>>    		val |= EDP_PSR_LINK_STANDBY;
>>>>    
>>>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>>>> -		val |= EDP_PSR_TP1_TIME_2500us;
>>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>>>> -		val |= EDP_PSR_TP1_TIME_500us;
>>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>>>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>>>> +		val |=  EDP_PSR_TP1_TIME_0us;
>>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>>>    		val |= EDP_PSR_TP1_TIME_100us;
>>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>>>> +		val |= EDP_PSR_TP1_TIME_500us;
>>>>    	else
>>>> -		val |= EDP_PSR_TP1_TIME_0us;
>>>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>>>    
>>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>>>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>>>    		val |= EDP_PSR_TP2_TP3_TIME_100us;
>>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>>>    	else
>>>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>>>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>>>    
>>>>    	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>>>    	    drm_dp_tps3_supported(intel_dp->dpcd))
>>>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>>    
>>>>    	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>>>    
>>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>>> -		val |= EDP_PSR2_TP2_TIME_2500;
>>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>>> -		val |= EDP_PSR2_TP2_TIME_500;
>>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>>> -		val |= EDP_PSR2_TP2_TIME_100;
>>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>>>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>>>> +		val |= EDP_PSR2_TP2_TIME_50us;
>>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>>> +		val |= EDP_PSR2_TP2_TIME_100us;
>>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>>>    	else
>>>> -		val |= EDP_PSR2_TP2_TIME_50;
>>>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>>>    
>>>>    	I915_WRITE(EDP_PSR2_CTL, val);
>>>>    }

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-22  4:48   ` Nagaraju, Vathsala
@ 2018-05-22  8:05     ` Jani Nikula
  2018-05-22  8:36       ` Nagaraju, Vathsala
  0 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-05-22  8:05 UTC (permalink / raw)
  To: Nagaraju, Vathsala, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan

On Tue, 22 May 2018, "Nagaraju, Vathsala" <vathsala.nagaraju@intel.com> wrote:
> On 5/18/2018 3:01 PM, Jani Nikula wrote:
>> On Fri, 18 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>>
>>> For psr block #9, the vbt description has moved to options [0-3] for
>>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>>> structure. Since spec does not  mention from which VBT version this
>>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>>> to change for all the platforms.
>>>
>>> There is RCR inplace for GOP team to  provide the version number
>>> to make generic change. Since Kabylake with bdb version 209 is having this
>>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>>
>>> Tested on skl(bdb version 203,without options) and
>>> kabylake(bdb version 209,212) having new options.
>>>
>>> bspec 20131
>>>
>>> v2: (Jani and Rodrigo)
>>>      move the 165 version check to intel_bios.c
>>> v3: Jani
>>>      Move the abstraction to intel_bios.
>>> v4: Jani
>>>      Rename tp*_wakeup_time to have "us" suffix.
>>>      For values outside range[0-3],default to max 2500us.
>>>      Old decimal value was wake up time in multiples of 100us.
>>> v5: Jani and Rodrigo
>>>      Handle option 2 in default condition.
>>>      Print oustide range value.
>>>      For negetive values default to 2500us.
>>> v6: Jani
>>>      Handle default first and then fall through for case 2.
>>> v7: Rodrigo
>>>      Apply this change for IS_GEN9_BC and vbt version > 209.
>>> v8: Puthik
>>>      add new function vbt_psr_to_us.
>>>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Puthikorn Voravootivat <puthik@chromium.org>
>>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>
>>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>>   drivers/gpu/drm/i915/i915_reg.h   |  8 ++++----
>>>   drivers/gpu/drm/i915/intel_bios.c | 38 ++++++++++++++++++++++++++++++++++++--
>>>   drivers/gpu/drm/i915/intel_psr.c  | 39 ++++++++++++++++++++-------------------
>>>   4 files changed, 62 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index e33c380..dcfa791 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>>   		bool require_aux_wakeup;
>>>   		int idle_frames;
>>>   		enum psr_lines_to_wait lines_to_wait;
>>> -		int tp1_wakeup_time;
>>> -		int tp2_tp3_wakeup_time;
>>> +		int tp1_wakeup_time_us;
>>> +		int tp2_tp3_wakeup_time_us;
>>>   	} psr;
>>>   
>>>   	struct {
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 196a0eb..513b4a4 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -4088,10 +4088,10 @@ enum {
>>>   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>>   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>>   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>>   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>>> index 54270bd..5d8c29f 100644
>>> --- a/drivers/gpu/drm/i915/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>>> @@ -647,12 +647,26 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>   	}
>>>   }
>>>   
>>> +static int vbt_psr_to_us(bool is_waketime_options, int vbt_value)
>>> +{
>>> +	if (is_waketime_options) {
>>> +		int waketime_map[] = {500, 100, 2500, 0};
>>> +		/* Reset to value 2 = 2500us for outside range [0-3] */
>>> +		if (vbt_value < 0 || vbt_value > 3)
>>> +			vbt_value = 2;
>>> +		return waketime_map[vbt_value];
>>> +	} else {
>>> +		return vbt_value * 100;
>>> +	}
>>> +}
>>> +
>>>   static void
>>>   parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>>   {
>>>   	const struct bdb_psr *psr;
>>>   	const struct psr_table *psr_table;
>>>   	int panel_type = dev_priv->vbt.panel_type;
>>> +	bool is_waketime_options = false;
>>>   
>>>   	psr = find_section(bdb, BDB_PSR);
>>>   	if (!psr) {
>>> @@ -688,8 +702,28 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>   		break;
>>>   	}
>>>   
>>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>>> +	/*
>>> +	 * New psr wake options 0=500us, 1=100us, 2=2500us, 3=0us
>>> +	 * Old decimal value is wake up time in multiples of 100 us.
>>> +	 * TODO: add other platforms having new psr options.
>>> +	 */
>>> +	is_waketime_options = ((bdb->version >= 209) && IS_GEN9_BC(dev_priv));
>>> +	if (is_waketime_options) {
>>> +		/* Reset to value 2 = 2500us for outside range [0-3] */
>>> +		if (psr_table->tp1_wakeup_time < 0 ||
>>> +			psr_table->tp1_wakeup_time > 3) {
>>> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>>> +					psr_table->tp1_wakeup_time);
>>> +		}
>>> +		if (psr_table->tp2_tp3_wakeup_time < 0 ||
>>> +			psr_table->tp2_tp3_wakeup_time > 3) {
>>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>>> +					psr_table->tp2_tp3_wakeup_time);
>>> +		}
>>> +	}
>> Why did you take something that was obvious at a glance and turn it into
>> this complicated mess?
> Which parts you find it complicated?

This splits and duplicates the checks for valid values to two places
that you need to keep in sync as the spec inevitably gets updated. The
responsibilities between the caller and the callee are unclear, which is
just silly for such a small amount of code. You have checks for negative
values but the field is unsigned. I could go on.

The bottom line is that the spec makes a fundamentally simple thing
unnecessarily complicated, and it's our job to implement that in a way
that makes it again simple for human beings. That's the primary goal,
make the code easy for the reader. We have enough hard things, we should
not have to stop and think about simple things.

BR,
Jani.


> new version is
> 1) check if vbt data is  wake_options
> 2) if wake options , then  if out of range print the message
> 3)then  for both new and old version , we call vbt_psr_to_us , which 
> takes care of the mapping and conversion to us.
>>
>> I'd rather take the previous version, even with the duplication.
> puthik suggested to use vbt_psr_to_us to remove code duplication.
> Puthik , is it okay if  we switch to v7 version?
>
>> BR,
>> Jani.
>>
>>
>>> +
>>> +	dev_priv->vbt.psr.tp1_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp1_wakeup_time);
>>> +	dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp2_tp3_wakeup_time);
>>>   }
>>>   
>>>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>> index db27f2f..d64f039 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>>   	if (dev_priv->psr.link_standby)
>>>   		val |= EDP_PSR_LINK_STANDBY;
>>>   
>>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP1_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP1_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>>> +		val |=  EDP_PSR_TP1_TIME_0us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>>   		val |= EDP_PSR_TP1_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR_TP1_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR_TP1_TIME_0us;
>>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>>   
>>>   	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>>   	    drm_dp_tps3_supported(intel_dp->dpcd))
>>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>   
>>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR2_TP2_TIME_2500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR2_TP2_TIME_500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> -		val |= EDP_PSR2_TP2_TIME_100;
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>>> +		val |= EDP_PSR2_TP2_TIME_50us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>> +		val |= EDP_PSR2_TP2_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR2_TP2_TIME_50;
>>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>>   
>>>   	I915_WRITE(EDP_PSR2_CTL, val);
>>>   }
>

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-18  9:31 ` Jani Nikula
@ 2018-05-22  4:48   ` Nagaraju, Vathsala
  2018-05-22  8:05     ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-22  4:48 UTC (permalink / raw)
  To: Jani Nikula, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan



On 5/18/2018 3:01 PM, Jani Nikula wrote:
> On Fri, 18 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>      move the 165 version check to intel_bios.c
>> v3: Jani
>>      Move the abstraction to intel_bios.
>> v4: Jani
>>      Rename tp*_wakeup_time to have "us" suffix.
>>      For values outside range[0-3],default to max 2500us.
>>      Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>>      Handle option 2 in default condition.
>>      Print oustide range value.
>>      For negetive values default to 2500us.
>> v6: Jani
>>      Handle default first and then fall through for case 2.
>> v7: Rodrigo
>>      Apply this change for IS_GEN9_BC and vbt version > 209.
>> v8: Puthik
>>      add new function vbt_psr_to_us.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Puthikorn Voravootivat <puthik@chromium.org>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>   drivers/gpu/drm/i915/i915_reg.h   |  8 ++++----
>>   drivers/gpu/drm/i915/intel_bios.c | 38 ++++++++++++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_psr.c  | 39 ++++++++++++++++++++-------------------
>>   4 files changed, 62 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index e33c380..dcfa791 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>   		bool require_aux_wakeup;
>>   		int idle_frames;
>>   		enum psr_lines_to_wait lines_to_wait;
>> -		int tp1_wakeup_time;
>> -		int tp2_tp3_wakeup_time;
>> +		int tp1_wakeup_time_us;
>> +		int tp2_tp3_wakeup_time_us;
>>   	} psr;
>>   
>>   	struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 196a0eb..513b4a4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4088,10 +4088,10 @@ enum {
>>   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 54270bd..5d8c29f 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -647,12 +647,26 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   	}
>>   }
>>   
>> +static int vbt_psr_to_us(bool is_waketime_options, int vbt_value)
>> +{
>> +	if (is_waketime_options) {
>> +		int waketime_map[] = {500, 100, 2500, 0};
>> +		/* Reset to value 2 = 2500us for outside range [0-3] */
>> +		if (vbt_value < 0 || vbt_value > 3)
>> +			vbt_value = 2;
>> +		return waketime_map[vbt_value];
>> +	} else {
>> +		return vbt_value * 100;
>> +	}
>> +}
>> +
>>   static void
>>   parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>   {
>>   	const struct bdb_psr *psr;
>>   	const struct psr_table *psr_table;
>>   	int panel_type = dev_priv->vbt.panel_type;
>> +	bool is_waketime_options = false;
>>   
>>   	psr = find_section(bdb, BDB_PSR);
>>   	if (!psr) {
>> @@ -688,8 +702,28 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   		break;
>>   	}
>>   
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	/*
>> +	 * New psr wake options 0=500us, 1=100us, 2=2500us, 3=0us
>> +	 * Old decimal value is wake up time in multiples of 100 us.
>> +	 * TODO: add other platforms having new psr options.
>> +	 */
>> +	is_waketime_options = ((bdb->version >= 209) && IS_GEN9_BC(dev_priv));
>> +	if (is_waketime_options) {
>> +		/* Reset to value 2 = 2500us for outside range [0-3] */
>> +		if (psr_table->tp1_wakeup_time < 0 ||
>> +			psr_table->tp1_wakeup_time > 3) {
>> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>> +					psr_table->tp1_wakeup_time);
>> +		}
>> +		if (psr_table->tp2_tp3_wakeup_time < 0 ||
>> +			psr_table->tp2_tp3_wakeup_time > 3) {
>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
>> +					psr_table->tp2_tp3_wakeup_time);
>> +		}
>> +	}
> Why did you take something that was obvious at a glance and turn it into
> this complicated mess?
Which parts you find it complicated?
new version is
1) check if vbt data is  wake_options
2) if wake options , then  if out of range print the message
3)then  for both new and old version , we call vbt_psr_to_us , which 
takes care of the mapping and conversion to us.
>
> I'd rather take the previous version, even with the duplication.
puthik suggested to use vbt_psr_to_us to remove code duplication.
Puthik , is it okay if  we switch to v7 version?

> BR,
> Jani.
>
>
>> +
>> +	dev_priv->vbt.psr.tp1_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp1_wakeup_time);
>> +	dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp2_tp3_wakeup_time);
>>   }
>>   
>>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index db27f2f..d64f039 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>   	if (dev_priv->psr.link_standby)
>>   		val |= EDP_PSR_LINK_STANDBY;
>>   
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>> +		val |=  EDP_PSR_TP1_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>   		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP1_TIME_500us;
>>   	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>   	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>   
>>   	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>   	    drm_dp_tps3_supported(intel_dp->dpcd))
>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>   
>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>> +		val |= EDP_PSR2_TP2_TIME_50us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>> +		val |= EDP_PSR2_TP2_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>   	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>   
>>   	I915_WRITE(EDP_PSR2_CTL, val);
>>   }

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-18  8:55 vathsala nagaraju
@ 2018-05-18  9:31 ` Jani Nikula
  2018-05-22  4:48   ` Nagaraju, Vathsala
  0 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-05-18  9:31 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan

On Fri, 18 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to gen9_bc and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us.
> v6: Jani
>     Handle default first and then fall through for case 2.
> v7: Rodrigo
>     Apply this change for IS_GEN9_BC and vbt version > 209.
> v8: Puthik
>     add new function vbt_psr_to_us.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Puthikorn Voravootivat <puthik@chromium.org>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 ++++----
>  drivers/gpu/drm/i915/intel_bios.c | 38 ++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 ++++++++++++++++++++-------------------
>  4 files changed, 62 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e33c380..dcfa791 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb..513b4a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4088,10 +4088,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bd..5d8c29f 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -647,12 +647,26 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +static int vbt_psr_to_us(bool is_waketime_options, int vbt_value)
> +{
> +	if (is_waketime_options) {
> +		int waketime_map[] = {500, 100, 2500, 0};
> +		/* Reset to value 2 = 2500us for outside range [0-3] */
> +		if (vbt_value < 0 || vbt_value > 3)
> +			vbt_value = 2;
> +		return waketime_map[vbt_value];
> +	} else {
> +		return vbt_value * 100;
> +	}
> +}
> +
>  static void
>  parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  {
>  	const struct bdb_psr *psr;
>  	const struct psr_table *psr_table;
>  	int panel_type = dev_priv->vbt.panel_type;
> +	bool is_waketime_options = false;
>  
>  	psr = find_section(bdb, BDB_PSR);
>  	if (!psr) {
> @@ -688,8 +702,28 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr wake options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 * TODO: add other platforms having new psr options.
> +	 */
> +	is_waketime_options = ((bdb->version >= 209) && IS_GEN9_BC(dev_priv));
> +	if (is_waketime_options) {
> +		/* Reset to value 2 = 2500us for outside range [0-3] */
> +		if (psr_table->tp1_wakeup_time < 0 ||
> +			psr_table->tp1_wakeup_time > 3) {
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		}
> +		if (psr_table->tp2_tp3_wakeup_time < 0 ||
> +			psr_table->tp2_tp3_wakeup_time > 3) {
> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp2_tp3_wakeup_time);
> +		}
> +	}

Why did you take something that was obvious at a glance and turn it into
this complicated mess?

I'd rather take the previous version, even with the duplication.

BR,
Jani.


> +
> +	dev_priv->vbt.psr.tp1_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp1_wakeup_time);
> +	dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp2_tp3_wakeup_time);
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2f..d64f039 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-18  8:55 vathsala nagaraju
  2018-05-18  9:31 ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-18  8:55 UTC (permalink / raw)
  To: rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Jani Nikula, Maulik V Vaghela, Dhinakaran Pandiyan,
	Puthikorn Voravootivat

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us.
v6: Jani
    Handle default first and then fall through for case 2.
v7: Rodrigo
    Apply this change for IS_GEN9_BC and vbt version > 209.
v8: Puthik
    add new function vbt_psr_to_us.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 ++++----
 drivers/gpu/drm/i915/intel_bios.c | 38 ++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 ++++++++++++++++++++-------------------
 4 files changed, 62 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..dcfa791 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb..513b4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4088,10 +4088,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 54270bd..5d8c29f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -647,12 +647,26 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 	}
 }
 
+static int vbt_psr_to_us(bool is_waketime_options, int vbt_value)
+{
+	if (is_waketime_options) {
+		int waketime_map[] = {500, 100, 2500, 0};
+		/* Reset to value 2 = 2500us for outside range [0-3] */
+		if (vbt_value < 0 || vbt_value > 3)
+			vbt_value = 2;
+		return waketime_map[vbt_value];
+	} else {
+		return vbt_value * 100;
+	}
+}
+
 static void
 parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 {
 	const struct bdb_psr *psr;
 	const struct psr_table *psr_table;
 	int panel_type = dev_priv->vbt.panel_type;
+	bool is_waketime_options = false;
 
 	psr = find_section(bdb, BDB_PSR);
 	if (!psr) {
@@ -688,8 +702,28 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr wake options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 * TODO: add other platforms having new psr options.
+	 */
+	is_waketime_options = ((bdb->version >= 209) && IS_GEN9_BC(dev_priv));
+	if (is_waketime_options) {
+		/* Reset to value 2 = 2500us for outside range [0-3] */
+		if (psr_table->tp1_wakeup_time < 0 ||
+			psr_table->tp1_wakeup_time > 3) {
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);
+		}
+		if (psr_table->tp2_tp3_wakeup_time < 0 ||
+			psr_table->tp2_tp3_wakeup_time > 3) {
+			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp2_tp3_wakeup_time);
+		}
+	}
+
+	dev_priv->vbt.psr.tp1_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp1_wakeup_time);
+	dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = vbt_psr_to_us(is_waketime_options, psr_table->tp2_tp3_wakeup_time);
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2f..d64f039 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-17  8:02         ` Jani Nikula
@ 2018-05-17 20:12           ` Dhinakaran Pandiyan
  0 siblings, 0 replies; 45+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-17 20:12 UTC (permalink / raw)
  To: Jani Nikula, vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Thu, 2018-05-17 at 11:02 +0300, Jani Nikula wrote:
> On Wed, 16 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.c
> om> wrote:
> > 
> > On Wed, 2018-05-16 at 11:08 +0300, Jani Nikula wrote:
> > > 
> > > I think the patch is now the way it should be. We should not
> > > change
> > > our interpretation based on the value.
> > Is it correct to infer, from your response, that VBT values are not
> > always set based on hardware capability as documented in bspec?
> Correct. I think it was the good intention of the VBT change to only
> allow values that map to valid hardware values, but I think it has
> caused much more trouble than it has helped.
> 
> First, the change was not universally tied to a VBT version, and I've
> seen VBTs in the wild with version >= 209 that still use multiples of
> 100 us. (And the spec is still in contradiction with itself.)
> 
> Second, regardless of mapping or multiples of 100 us we need to
> verify
> our input. Because I've seen VBTs in the wild that are bogus
> regardless
> of how they're supposed to be interpreted.
> 
> Third, we already had the code in place to map multiples of 100 us to
> hardware. We'll need to keep that practically forever. And now we
> need
> to have *another* mapping.
> 
> Fourth, the multiples of 100 us does not require *any* spec change
> when
> hardware changes to support different values. The new mapping
> requires
> changes throughout the stack that looks at the values. (Basically I
> object to any VBT specification that says anything platform
> dependent. It should be generic.)
> 
> Now, the patch at hand uses the best guesses we can make to translate
> whatever the VBT has to microseconds, in intel_bios.c. That part does
> not care about hardware capability. For validity, it only looks at
> what
> we think is according to VBT spec. It should be hardware agnostic,
> except for the IS_GEN9_BC() thing, which should probably include
> gen10+
> too.
> 
> The code in intel_psr.c gets the microseconds as input, and maps that
> to
> hardware capability as best we can, erring towards longer delays.
> 
> Two different abstractions for two different things. One to abstract
> VBT, another to abstract hardware. This is in line with the direction
> I've tried to take intel_bios.c and VBT parsing and the VBT spec (the
> little I've had influence for that) for the longest time. We must not
> let the VBT abstractions to leak into the driver code.

Thanks for the detailed explanation of the problem and the idea behind
the design.

-DK


> 
> BR,
> Jani.
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-16 17:44       ` Dhinakaran Pandiyan
@ 2018-05-17  8:02         ` Jani Nikula
  2018-05-17 20:12           ` Dhinakaran Pandiyan
  0 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-05-17  8:02 UTC (permalink / raw)
  To: dhinakaran.pandiyan, vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 16 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> On Wed, 2018-05-16 at 11:08 +0300, Jani Nikula wrote:
>> I think the patch is now the way it should be. We should not change
>> our interpretation based on the value.
>
> Is it correct to infer, from your response, that VBT values are not
> always set based on hardware capability as documented in bspec?

Correct. I think it was the good intention of the VBT change to only
allow values that map to valid hardware values, but I think it has
caused much more trouble than it has helped.

First, the change was not universally tied to a VBT version, and I've
seen VBTs in the wild with version >= 209 that still use multiples of
100 us. (And the spec is still in contradiction with itself.)

Second, regardless of mapping or multiples of 100 us we need to verify
our input. Because I've seen VBTs in the wild that are bogus regardless
of how they're supposed to be interpreted.

Third, we already had the code in place to map multiples of 100 us to
hardware. We'll need to keep that practically forever. And now we need
to have *another* mapping.

Fourth, the multiples of 100 us does not require *any* spec change when
hardware changes to support different values. The new mapping requires
changes throughout the stack that looks at the values. (Basically I
object to any VBT specification that says anything platform
dependent. It should be generic.)

Now, the patch at hand uses the best guesses we can make to translate
whatever the VBT has to microseconds, in intel_bios.c. That part does
not care about hardware capability. For validity, it only looks at what
we think is according to VBT spec. It should be hardware agnostic,
except for the IS_GEN9_BC() thing, which should probably include gen10+
too.

The code in intel_psr.c gets the microseconds as input, and maps that to
hardware capability as best we can, erring towards longer delays.

Two different abstractions for two different things. One to abstract
VBT, another to abstract hardware. This is in line with the direction
I've tried to take intel_bios.c and VBT parsing and the VBT spec (the
little I've had influence for that) for the longest time. We must not
let the VBT abstractions to leak into the driver code.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-16  3:44   ` vathsala nagaraju
  2018-05-16  8:08     ` Jani Nikula
  2018-05-16  8:13     ` Jani Nikula
@ 2018-05-16 22:04     ` Dhinakaran Pandiyan
  2 siblings, 0 replies; 45+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-16 22:04 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 2018-05-16 at 09:14 +0530, vathsala nagaraju wrote:
> On Wednesday 16 May 2018 04:33 AM, Dhinakaran Pandiyan wrote:
> > 
> > On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
> > > 
> > > From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > > 
> > > For psr block #9, the vbt description has moved to options [0-3]
> > > for
> > > TP1,TP2,TP3 Wakeup time from decimal value without any change to
> > > vbt
> > > structure. Since spec does not  mention from which VBT version
> > > this
> > > change was added to vbt.bsf file, we cannot depend on bdb-
> > > >version
> > > check
> > > to change for all the platforms.
> > > 
> > > There is RCR inplace for GOP team to  provide the version number
> > > to make generic change. Since Kabylake with bdb version 209 is
> > > having
> > > this
> > > change, limiting this change to gen9_bc and version 209+ to
> > > unblock
> > > google.
> > > 
> > > Tested on skl(bdb version 203,without options) and
> > > kabylake(bdb version 209,212) having new options.
> > > 
> > > bspec 20131
> > > 
> > > v2: (Jani and Rodrigo)
> > >      move the 165 version check to intel_bios.c
> > > v3: Jani
> > >      Move the abstraction to intel_bios.
> > > v4: Jani
> > >      Rename tp*_wakeup_time to have "us" suffix.
> > >      For values outside range[0-3],default to max 2500us.
> > >      Old decimal value was wake up time in multiples of 100us.
> > > v5: Jani and Rodrigo
> > >      Handle option 2 in default condition.
> > >      Print oustide range value.
> > >      For negetive values default to 2500us.
> > > v6: Jani
> > >      Handle default first and then fall through for case 2.
> > > v7: Rodrigo
> > >      Apply this change for IS_GEN9_BC and vbt version > 209
> > > 
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > > 
> > > Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
> > >   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
> > >   drivers/gpu/drm/i915/intel_bios.c | 46
> > > +++++++++++++++++++++++++++++++++++++--
> > >   drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++-------
> > > ---
> > > ------
> > >   4 files changed, 70 insertions(+), 27 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 57fb3aa..268b059 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
> > >   		bool require_aux_wakeup;
> > >   		int idle_frames;
> > >   		enum psr_lines_to_wait lines_to_wait;
> > > -		int tp1_wakeup_time;
> > > -		int tp2_tp3_wakeup_time;
> > > +		int tp1_wakeup_time_us;
> > > +		int tp2_tp3_wakeup_time_us;
> > >   	} psr;
> > >   
> > >   	struct {
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index f11bb21..6820658 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4088,10 +4088,10 @@ enum {
> > >   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and
> > > CNL+ */
> > >   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
> > >   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> > > -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> > > -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> > > -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> > > -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> > > +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> > > +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> > > +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> > > +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
> > >   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
> > >   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> > >   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> > > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > > b/drivers/gpu/drm/i915/intel_bios.c
> > > index 54270bd..695ca73 100644
> > > --- a/drivers/gpu/drm/i915/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > > @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
> > > drm_i915_private *dev_priv,
> > >   		break;
> > >   	}
> > >   
> > > -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table-
> > > > 
> > > > tp1_wakeup_time;
> > > -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table-
> > > > 
> > > > tp2_tp3_wakeup_time;
> > > +	/*
> > > +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> > > +	 * Old decimal value is wake up time in multiples of 100
> > > us.
> > > +	 */
> > > +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> > Since this is the 'new' mapping, shouldn't this check be
> > 
> > if (version >= 209) {
> > 
> > }
> check is for bdb version.
> > 
> > i.e., what versions do BXT, GLK, CFL and CNL have?
> waiting for GOP's team confirmation on above platforms.
> We can add them later.
> > 
> > 
> > Since gen-9 tables can have ambiguous interpretations, I think we
> > can
> > do this.
> > 
> > if (version >= 209 || (IS_GEN9() && wakeup_time <=3)) {
> > 	// Read this as {0:500, 1:100, 2:2500, 3:0}
> With old bsf file , it's multiple of 100 ms.
> if user inputs  2  , thinking that  it's 200 ms , with above change
> we 
> are setting this to  2500 ms.
> As per old spec, it should be set to 500 ms.   (>1 , set to 500)
> Jani /Maulik, is it okay to make the above change?
> > 
> > } else {
> > 	// Read this as wakeup_time * 100
> > }
> > 
> > This is assuming all versions => 209 use the new mapping
> > consistently.
> > 
> > 2 and 3 are invalid values in the x*100 us scheme, so we can assume
> > it
> > really means 2.5 ms and 0.
> > 1 means the same.
> > 0 is a problem, but we can check dpcd 0071h to confirm whether the
> > sink
> > needs training or not. And it is safer to assume the sink needs
> > training at interpret is as 500 us.
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d
> is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		/*fall through*/
> 		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
> 
> > 
> > nit: That's an interesting order, it is neither sorted by the
> > switch
> > variable nor by wake up time. It is easier to read if you chose one
> > way
> > or the other IMO.
> As per Jani's suggesttion , we need to set 2500ms for out of range[0-
> 3]. 
This is what I meant -
               switch (psr_table->tp1_wakeup_time) {
                case 0:
                        dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
                        break;
                case 1:
                        dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
                        break;
                default:
                        DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is
outside range[0-3], defaulting to max value 2500us\n",
                                        psr_table->tp1_wakeup_time);
                case 2:
                        dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
                        break;

                case 3:
                        dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
                        break;
                }



> It's a fall through.
> should i add comment /*fall through*/  as above?

Yeah, no harm in adding that and iirc you get a gcc warning if the fall
through isn't marked..

> > 
> >   
> > > 
> > > +		switch (psr_table->tp2_tp3_wakeup_time) {
> > > +		case 0:
> > > +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us 
> > > =
> > > 500;
> > > +			break;
> > > +		case 1:
> > > +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us 
> > > =
> > > 100;
> > > +			break;
> > > +		case 3:
> > > +			dev_priv->vbt.psr.tp1_wakeup_time_us =
> > > 0;
> > > +			break;
> > > +		default:
> > > +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time
> > > value
> > > %d is outside range[0-3], defaulting to max value 2500us\n",
> > > +					psr_table-
> > > > 
> > > > tp2_tp3_wakeup_time);
> > > +		case 2:
> > > +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us 
> > > =
> > > 2500;
> > > +		break;
> > > +		}
> > > +	} else {
> > > +		dev_priv->vbt.psr.tp1_wakeup_time_us =
> > > psr_table-
> > > > 
> > > > tp1_wakeup_time * 100;
> > > +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> > > psr_table->tp2_tp3_wakeup_time * 100;
> > > +	}
> > >   }
> > >   
> > >   static void parse_dsi_backlight_ports(struct drm_i915_private
> > > *dev_priv,
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index db27f2f..d64f039 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct
> > > intel_dp
> > > *intel_dp)
> > >   	if (dev_priv->psr.link_standby)
> > >   		val |= EDP_PSR_LINK_STANDBY;
> > >   
> > > -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> > > -		val |= EDP_PSR_TP1_TIME_2500us;
> > > -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> > > -		val |= EDP_PSR_TP1_TIME_500us;
> > > -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> > > +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> > > +		val |=  EDP_PSR_TP1_TIME_0us;
> > > +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> > >   		val |= EDP_PSR_TP1_TIME_100us;
> > > +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> > > +		val |= EDP_PSR_TP1_TIME_500us;
> > >   	else
> > > -		val |= EDP_PSR_TP1_TIME_0us;
> > > +		val |= EDP_PSR_TP1_TIME_2500us;
> > >   
> > > -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> > > -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > > -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> > > +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> > > +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > 100)
> > >   		val |= EDP_PSR_TP2_TP3_TIME_100us;
> > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > 500)
> > > +		val |= EDP_PSR_TP2_TP3_TIME_500us;
> > >   	else
> > > -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> > > +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> > >   
> > >   	if (intel_dp_source_supports_hbr2(intel_dp) &&
> > >   	    drm_dp_tps3_supported(intel_dp->dpcd))
> > > @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct
> > > intel_dp
> > > *intel_dp)
> > >   
> > >   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv-
> > > > 
> > > > psr.sink_sync_latency + 1);
> > >   
> > > -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> > > -		val |= EDP_PSR2_TP2_TIME_2500;
> > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > > -		val |= EDP_PSR2_TP2_TIME_500;
> > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> > > -		val |= EDP_PSR2_TP2_TIME_100;
> > > +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> > > +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> > > +		val |= EDP_PSR2_TP2_TIME_50us;
> > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > 100)
> > > +		val |= EDP_PSR2_TP2_TIME_100us;
> > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > 500)
> > > +		val |= EDP_PSR2_TP2_TIME_500us;
> > >   	else
> > > -		val |= EDP_PSR2_TP2_TIME_50;
> > > +		val |= EDP_PSR2_TP2_TIME_2500us;
> > >   
> > >   	I915_WRITE(EDP_PSR2_CTL, val);
> > >   }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-16  8:08     ` Jani Nikula
@ 2018-05-16 17:44       ` Dhinakaran Pandiyan
  2018-05-17  8:02         ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-16 17:44 UTC (permalink / raw)
  To: Jani Nikula, vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 2018-05-16 at 11:08 +0300, Jani Nikula wrote:
> On Wed, 16 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com>
> wrote:
> > 
> > On Wednesday 16 May 2018 04:33 AM, Dhinakaran Pandiyan wrote:
> > > 
> > > On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
> > > > 
> > > > From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > > > 
> > > > For psr block #9, the vbt description has moved to options [0-
> > > > 3] for
> > > > TP1,TP2,TP3 Wakeup time from decimal value without any change
> > > > to vbt
> > > > structure. Since spec does not  mention from which VBT version
> > > > this
> > > > change was added to vbt.bsf file, we cannot depend on bdb-
> > > > >version
> > > > check
> > > > to change for all the platforms.
> > > > 
> > > > There is RCR inplace for GOP team to  provide the version
> > > > number
> > > > to make generic change. Since Kabylake with bdb version 209 is
> > > > having
> > > > this
> > > > change, limiting this change to gen9_bc and version 209+ to
> > > > unblock
> > > > google.
> > > > 
> > > > Tested on skl(bdb version 203,without options) and
> > > > kabylake(bdb version 209,212) having new options.
> > > > 
> > > > bspec 20131
> > > > 
> > > > v2: (Jani and Rodrigo)
> > > >      move the 165 version check to intel_bios.c
> > > > v3: Jani
> > > >      Move the abstraction to intel_bios.
> > > > v4: Jani
> > > >      Rename tp*_wakeup_time to have "us" suffix.
> > > >      For values outside range[0-3],default to max 2500us.
> > > >      Old decimal value was wake up time in multiples of 100us.
> > > > v5: Jani and Rodrigo
> > > >      Handle option 2 in default condition.
> > > >      Print oustide range value.
> > > >      For negetive values default to 2500us.
> > > > v6: Jani
> > > >      Handle default first and then fall through for case 2.
> > > > v7: Rodrigo
> > > >      Apply this change for IS_GEN9_BC and vbt version > 209
> > > > 
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > > > 
> > > > Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> > > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > > > ---
> > > >   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
> > > >   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
> > > >   drivers/gpu/drm/i915/intel_bios.c | 46
> > > > +++++++++++++++++++++++++++++++++++++--
> > > >   drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++-----
> > > > -----
> > > > ------
> > > >   4 files changed, 70 insertions(+), 27 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 57fb3aa..268b059 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
> > > >   		bool require_aux_wakeup;
> > > >   		int idle_frames;
> > > >   		enum psr_lines_to_wait lines_to_wait;
> > > > -		int tp1_wakeup_time;
> > > > -		int tp2_tp3_wakeup_time;
> > > > +		int tp1_wakeup_time_us;
> > > > +		int tp2_tp3_wakeup_time_us;
> > > >   	} psr;
> > > >   
> > > >   	struct {
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index f11bb21..6820658 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -4088,10 +4088,10 @@ enum {
> > > >   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and
> > > > CNL+ */
> > > >   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
> > > >   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> > > > -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> > > > -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> > > > -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> > > > -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> > > > +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> > > > +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> > > > +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> > > > +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
> > > >   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
> > > >   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> > > >   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> > > > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > > > b/drivers/gpu/drm/i915/intel_bios.c
> > > > index 54270bd..695ca73 100644
> > > > --- a/drivers/gpu/drm/i915/intel_bios.c
> > > > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > > > @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
> > > > drm_i915_private *dev_priv,
> > > >   		break;
> > > >   	}
> > > >   
> > > > -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table-
> > > > > 
> > > > > tp1_wakeup_time;
> > > > -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table-
> > > > > 
> > > > > tp2_tp3_wakeup_time;
> > > > +	/*
> > > > +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> > > > +	 * Old decimal value is wake up time in multiples of
> > > > 100 us.
> > > > +	 */
> > > > +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> > > Since this is the 'new' mapping, shouldn't this check be
> > > 
> > > if (version >= 209) {
> > > 
> > > }
> > check is for bdb version.
> > > 
> > > i.e., what versions do BXT, GLK, CFL and CNL have?
> > waiting for GOP's team confirmation on above platforms.
> > We can add them later.
> > > 
> > > 
> > > Since gen-9 tables can have ambiguous interpretations, I think we
> > > can
> > > do this.
> > > 
> > > if (version >= 209 || (IS_GEN9() && wakeup_time <=3)) {
> > > 	// Read this as {0:500, 1:100, 2:2500, 3:0}
> > With old bsf file , it's multiple of 100 ms.
> > if user inputs  2  , thinking that  it's 200 ms , with above change
> > we 
> > are setting this to  2500 ms.
> > As per old spec, it should be set to 500 ms.   (>1 , set to 500)
> > Jani /Maulik, is it okay to make the above change?
> I think the patch is now the way it should be. We should not change
> our
> interpretation based on the value.

Is it correct to infer, from your response, that VBT values are not
always set based on hardware capability as documented in bspec?



> 
> BR,
> Jani.
> 
> 
> 
> > 
> > > 
> > > } else {
> > > 	// Read this as wakeup_time * 100
> > > }
> > > 
> > > This is assuming all versions => 209 use the new mapping
> > > consistently.
> > > 
> > > 2 and 3 are invalid values in the x*100 us scheme, so we can
> > > assume it
> > > really means 2.5 ms and 0.
> > > 1 means the same.
> > > 0 is a problem, but we can check dpcd 0071h to confirm whether
> > > the sink
> > > needs training or not. And it is safer to assume the sink needs
> > > training at interpret is as 500 us.
> > +		switch (psr_table->tp1_wakeup_time) {
> > +		case 0:
> > +			dev_priv->vbt.psr.tp1_wakeup_time_us =
> > 500;
> > +			break;
> > +		case 1:
> > +			dev_priv->vbt.psr.tp1_wakeup_time_us =
> > 100;
> > +			break;
> > +		case 3:
> > +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> > +			break;
> > +		default:
> > +			DRM_DEBUG_KMS("VBT tp1 wakeup time value
> > %d
> > is outside range[0-3], defaulting to max value 2500us\n",
> > +					psr_table-
> > >tp1_wakeup_time);
> > +		/*fall through*/
> > 		case 2:
> > +			dev_priv->vbt.psr.tp1_wakeup_time_us =
> > 2500;
> > +			break;
> > +		}
> > +
> > 
> > > 
> > > nit: That's an interesting order, it is neither sorted by the
> > > switch
> > > variable nor by wake up time. It is easier to read if you chose
> > > one way
> > > or the other IMO.
> > As per Jani's suggesttion , we need to set 2500ms for out of
> > range[0-3]. 
> > It's a fall through.
> > should i add comment /*fall through*/  as above?
> > > 
> > >   
> > > > 
> > > > +		switch (psr_table->tp2_tp3_wakeup_time) {
> > > > +		case 0:
> > > > +			dev_priv-
> > > > >vbt.psr.tp2_tp3_wakeup_time_us =
> > > > 500;
> > > > +			break;
> > > > +		case 1:
> > > > +			dev_priv-
> > > > >vbt.psr.tp2_tp3_wakeup_time_us =
> > > > 100;
> > > > +			break;
> > > > +		case 3:
> > > > +			dev_priv->vbt.psr.tp1_wakeup_time_us =
> > > > 0;
> > > > +			break;
> > > > +		default:
> > > > +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time
> > > > value
> > > > %d is outside range[0-3], defaulting to max value 2500us\n",
> > > > +					psr_table-
> > > > > 
> > > > > tp2_tp3_wakeup_time);
> > > > +		case 2:
> > > > +			dev_priv-
> > > > >vbt.psr.tp2_tp3_wakeup_time_us =
> > > > 2500;
> > > > +		break;
> > > > +		}
> > > > +	} else {
> > > > +		dev_priv->vbt.psr.tp1_wakeup_time_us =
> > > > psr_table-
> > > > > 
> > > > > tp1_wakeup_time * 100;
> > > > +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> > > > psr_table->tp2_tp3_wakeup_time * 100;
> > > > +	}
> > > >   }
> > > >   
> > > >   static void parse_dsi_backlight_ports(struct drm_i915_private
> > > > *dev_priv,
> > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > index db27f2f..d64f039 100644
> > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct
> > > > intel_dp
> > > > *intel_dp)
> > > >   	if (dev_priv->psr.link_standby)
> > > >   		val |= EDP_PSR_LINK_STANDBY;
> > > >   
> > > > -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> > > > -		val |= EDP_PSR_TP1_TIME_2500us;
> > > > -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> > > > -		val |= EDP_PSR_TP1_TIME_500us;
> > > > -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> > > > +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> > > > +		val |=  EDP_PSR_TP1_TIME_0us;
> > > > +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> > > >   		val |= EDP_PSR_TP1_TIME_100us;
> > > > +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> > > > +		val |= EDP_PSR_TP1_TIME_500us;
> > > >   	else
> > > > -		val |= EDP_PSR_TP1_TIME_0us;
> > > > +		val |= EDP_PSR_TP1_TIME_2500us;
> > > >   
> > > > -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> > > > -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> > > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > > > -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> > > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> > > > +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> > > > +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> > > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > > 100)
> > > >   		val |= EDP_PSR_TP2_TP3_TIME_100us;
> > > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > > 500)
> > > > +		val |= EDP_PSR_TP2_TP3_TIME_500us;
> > > >   	else
> > > > -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> > > > +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> > > >   
> > > >   	if (intel_dp_source_supports_hbr2(intel_dp) &&
> > > >   	    drm_dp_tps3_supported(intel_dp->dpcd))
> > > > @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct
> > > > intel_dp
> > > > *intel_dp)
> > > >   
> > > >   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv-
> > > > > 
> > > > > psr.sink_sync_latency + 1);
> > > >   
> > > > -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> > > > -		val |= EDP_PSR2_TP2_TIME_2500;
> > > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > > > -		val |= EDP_PSR2_TP2_TIME_500;
> > > > -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> > > > -		val |= EDP_PSR2_TP2_TIME_100;
> > > > +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> > > > +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> > > > +		val |= EDP_PSR2_TP2_TIME_50us;
> > > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > > 100)
> > > > +		val |= EDP_PSR2_TP2_TIME_100us;
> > > > +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <=
> > > > 500)
> > > > +		val |= EDP_PSR2_TP2_TIME_500us;
> > > >   	else
> > > > -		val |= EDP_PSR2_TP2_TIME_50;
> > > > +		val |= EDP_PSR2_TP2_TIME_2500us;
> > > >   
> > > >   	I915_WRITE(EDP_PSR2_CTL, val);
> > > >   }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-16  3:44   ` vathsala nagaraju
  2018-05-16  8:08     ` Jani Nikula
@ 2018-05-16  8:13     ` Jani Nikula
  2018-05-16 22:04     ` Dhinakaran Pandiyan
  2 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-05-16  8:13 UTC (permalink / raw)
  To: vathsala nagaraju, dhinakaran.pandiyan, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 16 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> On Wednesday 16 May 2018 04:33 AM, Dhinakaran Pandiyan wrote:
>> On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
>>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>>
>>> For psr block #9, the vbt description has moved to options [0-3] for
>>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>>> structure. Since spec does not  mention from which VBT version this
>>> change was added to vbt.bsf file, we cannot depend on bdb->version
>>> check
>>> to change for all the platforms.
>>>
>>> There is RCR inplace for GOP team to  provide the version number
>>> to make generic change. Since Kabylake with bdb version 209 is having
>>> this
>>> change, limiting this change to gen9_bc and version 209+ to unblock
>>> google.
>>>
>>> Tested on skl(bdb version 203,without options) and
>>> kabylake(bdb version 209,212) having new options.
>>>
>>> bspec 20131
>>>
>>> v2: (Jani and Rodrigo)
>>>      move the 165 version check to intel_bios.c
>>> v3: Jani
>>>      Move the abstraction to intel_bios.
>>> v4: Jani
>>>      Rename tp*_wakeup_time to have "us" suffix.
>>>      For values outside range[0-3],default to max 2500us.
>>>      Old decimal value was wake up time in multiples of 100us.
>>> v5: Jani and Rodrigo
>>>      Handle option 2 in default condition.
>>>      Print oustide range value.
>>>      For negetive values default to 2500us.
>>> v6: Jani
>>>      Handle default first and then fall through for case 2.
>>> v7: Rodrigo
>>>      Apply this change for IS_GEN9_BC and vbt version > 209
>>>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>>
>>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>>   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>>   drivers/gpu/drm/i915/intel_bios.c | 46
>>> +++++++++++++++++++++++++++++++++++++--
>>>   drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------
>>> ------
>>>   4 files changed, 70 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 57fb3aa..268b059 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>>   		bool require_aux_wakeup;
>>>   		int idle_frames;
>>>   		enum psr_lines_to_wait lines_to_wait;
>>> -		int tp1_wakeup_time;
>>> -		int tp2_tp3_wakeup_time;
>>> +		int tp1_wakeup_time_us;
>>> +		int tp2_tp3_wakeup_time_us;
>>>   	} psr;
>>>   
>>>   	struct {
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index f11bb21..6820658 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -4088,10 +4088,10 @@ enum {
>>>   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>>   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>>   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>>   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>>> b/drivers/gpu/drm/i915/intel_bios.c
>>> index 54270bd..695ca73 100644
>>> --- a/drivers/gpu/drm/i915/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>>> @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
>>> drm_i915_private *dev_priv,
>>>   		break;
>>>   	}
>>>   
>>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table-
>>>> tp1_wakeup_time;
>>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table-
>>>> tp2_tp3_wakeup_time;
>>> +	/*
>>> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>>> +	 * Old decimal value is wake up time in multiples of 100 us.
>>> +	 */
>>> +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
>> Since this is the 'new' mapping, shouldn't this check be
>>
>> if (version >= 209) {
>>
>> }
> check is for bdb version.

The reality is that this was screwed up royally. We have to include the
platform checks. I hate it as much as you do.

Besides, IMO there was *never* *any* need to change the encoding to
begin with. The driver has to check the values against what the hardware
is capable of, so the right course of action would have been to keep it
as a multiple of 100 us. It's the only sensible thing, and forward
compatible for all platforms to come. Now we map the VBT crap to us, and
then back to what the hardware can do. Ugh.


BR,
Jani.

>> i.e., what versions do BXT, GLK, CFL and CNL have?
> waiting for GOP's team confirmation on above platforms.
> We can add them later.
>>
>> Since gen-9 tables can have ambiguous interpretations, I think we can
>> do this.
>>
>> if (version >= 209 || (IS_GEN9() && wakeup_time <=3)) {
>> 	// Read this as {0:500, 1:100, 2:2500, 3:0}
> With old bsf file , it's multiple of 100 ms.
> if user inputs  2  , thinking that  it's 200 ms , with above change we 
> are setting this to  2500 ms.
> As per old spec, it should be set to 500 ms.   (>1 , set to 500)
> Jani /Maulik, is it okay to make the above change?
>> } else {
>> 	// Read this as wakeup_time * 100
>> }
>>
>> This is assuming all versions => 209 use the new mapping consistently.
>>
>> 2 and 3 are invalid values in the x*100 us scheme, so we can assume it
>> really means 2.5 ms and 0.
>> 1 means the same.
>> 0 is a problem, but we can check dpcd 0071h to confirm whether the sink
>> needs training or not. And it is safer to assume the sink needs
>> training at interpret is as 500 us.
>
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d
> is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		/*fall through*/
> 		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
>
>> nit: That's an interesting order, it is neither sorted by the switch
>> variable nor by wake up time. It is easier to read if you chose one way
>> or the other IMO.
> As per Jani's suggesttion , we need to set 2500ms for out of range[0-3]. 
> It's a fall through.
> should i add comment /*fall through*/  as above?
>>   
>>> +		switch (psr_table->tp2_tp3_wakeup_time) {
>>> +		case 0:
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> 500;
>>> +			break;
>>> +		case 1:
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> 100;
>>> +			break;
>>> +		case 3:
>>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>>> +			break;
>>> +		default:
>>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value
>>> %d is outside range[0-3], defaulting to max value 2500us\n",
>>> +					psr_table-
>>>> tp2_tp3_wakeup_time);
>>> +		case 2:
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> 2500;
>>> +		break;
>>> +		}
>>> +	} else {
>>> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table-
>>>> tp1_wakeup_time * 100;
>>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> psr_table->tp2_tp3_wakeup_time * 100;
>>> +	}
>>>   }
>>>   
>>>   static void parse_dsi_backlight_ports(struct drm_i915_private
>>> *dev_priv,
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>>> b/drivers/gpu/drm/i915/intel_psr.c
>>> index db27f2f..d64f039 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
>>> *intel_dp)
>>>   	if (dev_priv->psr.link_standby)
>>>   		val |= EDP_PSR_LINK_STANDBY;
>>>   
>>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP1_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP1_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>>> +		val |=  EDP_PSR_TP1_TIME_0us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>>   		val |= EDP_PSR_TP1_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR_TP1_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR_TP1_TIME_0us;
>>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>>   
>>>   	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>>   	    drm_dp_tps3_supported(intel_dp->dpcd))
>>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
>>> *intel_dp)
>>>   
>>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv-
>>>> psr.sink_sync_latency + 1);
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR2_TP2_TIME_2500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR2_TP2_TIME_500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> -		val |= EDP_PSR2_TP2_TIME_100;
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>>> +		val |= EDP_PSR2_TP2_TIME_50us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>> +		val |= EDP_PSR2_TP2_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR2_TP2_TIME_50;
>>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>>   
>>>   	I915_WRITE(EDP_PSR2_CTL, val);
>>>   }
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-16  3:44   ` vathsala nagaraju
@ 2018-05-16  8:08     ` Jani Nikula
  2018-05-16 17:44       ` Dhinakaran Pandiyan
  2018-05-16  8:13     ` Jani Nikula
  2018-05-16 22:04     ` Dhinakaran Pandiyan
  2 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-05-16  8:08 UTC (permalink / raw)
  To: vathsala nagaraju, dhinakaran.pandiyan, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 16 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> On Wednesday 16 May 2018 04:33 AM, Dhinakaran Pandiyan wrote:
>> On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
>>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>>
>>> For psr block #9, the vbt description has moved to options [0-3] for
>>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>>> structure. Since spec does not  mention from which VBT version this
>>> change was added to vbt.bsf file, we cannot depend on bdb->version
>>> check
>>> to change for all the platforms.
>>>
>>> There is RCR inplace for GOP team to  provide the version number
>>> to make generic change. Since Kabylake with bdb version 209 is having
>>> this
>>> change, limiting this change to gen9_bc and version 209+ to unblock
>>> google.
>>>
>>> Tested on skl(bdb version 203,without options) and
>>> kabylake(bdb version 209,212) having new options.
>>>
>>> bspec 20131
>>>
>>> v2: (Jani and Rodrigo)
>>>      move the 165 version check to intel_bios.c
>>> v3: Jani
>>>      Move the abstraction to intel_bios.
>>> v4: Jani
>>>      Rename tp*_wakeup_time to have "us" suffix.
>>>      For values outside range[0-3],default to max 2500us.
>>>      Old decimal value was wake up time in multiples of 100us.
>>> v5: Jani and Rodrigo
>>>      Handle option 2 in default condition.
>>>      Print oustide range value.
>>>      For negetive values default to 2500us.
>>> v6: Jani
>>>      Handle default first and then fall through for case 2.
>>> v7: Rodrigo
>>>      Apply this change for IS_GEN9_BC and vbt version > 209
>>>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>>
>>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>>   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>>   drivers/gpu/drm/i915/intel_bios.c | 46
>>> +++++++++++++++++++++++++++++++++++++--
>>>   drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------
>>> ------
>>>   4 files changed, 70 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 57fb3aa..268b059 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>>   		bool require_aux_wakeup;
>>>   		int idle_frames;
>>>   		enum psr_lines_to_wait lines_to_wait;
>>> -		int tp1_wakeup_time;
>>> -		int tp2_tp3_wakeup_time;
>>> +		int tp1_wakeup_time_us;
>>> +		int tp2_tp3_wakeup_time_us;
>>>   	} psr;
>>>   
>>>   	struct {
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index f11bb21..6820658 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -4088,10 +4088,10 @@ enum {
>>>   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>>   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>>   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>>   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>>> b/drivers/gpu/drm/i915/intel_bios.c
>>> index 54270bd..695ca73 100644
>>> --- a/drivers/gpu/drm/i915/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>>> @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
>>> drm_i915_private *dev_priv,
>>>   		break;
>>>   	}
>>>   
>>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table-
>>>> tp1_wakeup_time;
>>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table-
>>>> tp2_tp3_wakeup_time;
>>> +	/*
>>> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>>> +	 * Old decimal value is wake up time in multiples of 100 us.
>>> +	 */
>>> +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
>> Since this is the 'new' mapping, shouldn't this check be
>>
>> if (version >= 209) {
>>
>> }
> check is for bdb version.
>> i.e., what versions do BXT, GLK, CFL and CNL have?
> waiting for GOP's team confirmation on above platforms.
> We can add them later.
>>
>> Since gen-9 tables can have ambiguous interpretations, I think we can
>> do this.
>>
>> if (version >= 209 || (IS_GEN9() && wakeup_time <=3)) {
>> 	// Read this as {0:500, 1:100, 2:2500, 3:0}
> With old bsf file , it's multiple of 100 ms.
> if user inputs  2  , thinking that  it's 200 ms , with above change we 
> are setting this to  2500 ms.
> As per old spec, it should be set to 500 ms.   (>1 , set to 500)
> Jani /Maulik, is it okay to make the above change?

I think the patch is now the way it should be. We should not change our
interpretation based on the value.

BR,
Jani.



>> } else {
>> 	// Read this as wakeup_time * 100
>> }
>>
>> This is assuming all versions => 209 use the new mapping consistently.
>>
>> 2 and 3 are invalid values in the x*100 us scheme, so we can assume it
>> really means 2.5 ms and 0.
>> 1 means the same.
>> 0 is a problem, but we can check dpcd 0071h to confirm whether the sink
>> needs training or not. And it is safer to assume the sink needs
>> training at interpret is as 500 us.
>
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d
> is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		/*fall through*/
> 		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
>
>> nit: That's an interesting order, it is neither sorted by the switch
>> variable nor by wake up time. It is easier to read if you chose one way
>> or the other IMO.
> As per Jani's suggesttion , we need to set 2500ms for out of range[0-3]. 
> It's a fall through.
> should i add comment /*fall through*/  as above?
>>   
>>> +		switch (psr_table->tp2_tp3_wakeup_time) {
>>> +		case 0:
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> 500;
>>> +			break;
>>> +		case 1:
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> 100;
>>> +			break;
>>> +		case 3:
>>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>>> +			break;
>>> +		default:
>>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value
>>> %d is outside range[0-3], defaulting to max value 2500us\n",
>>> +					psr_table-
>>>> tp2_tp3_wakeup_time);
>>> +		case 2:
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> 2500;
>>> +		break;
>>> +		}
>>> +	} else {
>>> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table-
>>>> tp1_wakeup_time * 100;
>>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>>> psr_table->tp2_tp3_wakeup_time * 100;
>>> +	}
>>>   }
>>>   
>>>   static void parse_dsi_backlight_ports(struct drm_i915_private
>>> *dev_priv,
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>>> b/drivers/gpu/drm/i915/intel_psr.c
>>> index db27f2f..d64f039 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
>>> *intel_dp)
>>>   	if (dev_priv->psr.link_standby)
>>>   		val |= EDP_PSR_LINK_STANDBY;
>>>   
>>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP1_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP1_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>>> +		val |=  EDP_PSR_TP1_TIME_0us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>>   		val |= EDP_PSR_TP1_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR_TP1_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR_TP1_TIME_0us;
>>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>>   
>>>   	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>>   	    drm_dp_tps3_supported(intel_dp->dpcd))
>>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
>>> *intel_dp)
>>>   
>>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv-
>>>> psr.sink_sync_latency + 1);
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR2_TP2_TIME_2500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR2_TP2_TIME_500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> -		val |= EDP_PSR2_TP2_TIME_100;
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>>> +		val |= EDP_PSR2_TP2_TIME_50us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>> +		val |= EDP_PSR2_TP2_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>>   	else
>>> -		val |= EDP_PSR2_TP2_TIME_50;
>>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>>   
>>>   	I915_WRITE(EDP_PSR2_CTL, val);
>>>   }
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-15 22:55 ` Puthikorn Voravootivat
@ 2018-05-16  3:48   ` vathsala nagaraju
  0 siblings, 0 replies; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-16  3:48 UTC (permalink / raw)
  To: Puthikorn Voravootivat; +Cc: intel-gfx, maulik.v.vaghela, Rodrigo Vivi

On Wednesday 16 May 2018 04:25 AM, Puthikorn Voravootivat wrote:
> On Sun, May 13, 2018 at 8:32 PM vathsala nagaraju <
> vathsala.nagaraju@intel.com> wrote:
>
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to gen9_bc and version 209+ to unblock
> google.
>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>> bspec 20131
>> v2: (Jani and Rodrigo)
>>       move the 165 version check to intel_bios.c
>> v3: Jani
>>       Move the abstraction to intel_bios.
>> v4: Jani
>>       Rename tp*_wakeup_time to have "us" suffix.
>>       For values outside range[0-3],default to max 2500us.
>>       Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>>       Handle option 2 in default condition.
>>       Print oustide range value.
>>       For negetive values default to 2500us.
>> v6: Jani
>>       Handle default first and then fall through for case 2.
>> v7: Rodrigo
>>       Apply this change for IS_GEN9_BC and vbt version > 209
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>    drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>    drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>    drivers/gpu/drm/i915/intel_bios.c | 46
> +++++++++++++++++++++++++++++++++++++--
>>    drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
>>    4 files changed, 70 insertions(+), 27 deletions(-)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
>> index 57fb3aa..268b059 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>                   bool require_aux_wakeup;
>>                   int idle_frames;
>>                   enum psr_lines_to_wait lines_to_wait;
>> -               int tp1_wakeup_time;
>> -               int tp2_tp3_wakeup_time;
>> +               int tp1_wakeup_time_us;
>> +               int tp2_tp3_wakeup_time_us;
>>           } psr;
>>           struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
>> index f11bb21..6820658 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4088,10 +4088,10 @@ enum {
>>    #define   EDP_Y_COORDINATE_ENABLE      (1<<25) /* GLK and CNL+ */
>>    #define   EDP_MAX_SU_DISABLE_TIME(t)   ((t)<<20)
>>    #define   EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500                (0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100                (1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500       (2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50         (3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us      (0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us      (1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us     (2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us       (3<<8)
>>    #define   EDP_PSR2_TP2_TIME_MASK       (3<<8)
>>    #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>    #define   EDP_PSR2_FRAME_BEFORE_SU_MASK        (0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
>> index 54270bd..695ca73 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
> drm_i915_private *dev_priv,
>>                   break;
>>           }
>> -       dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -       dev_priv->vbt.psr.tp2_tp3_wakeup_time =
> psr_table->tp2_tp3_wakeup_time;
>> +       /*
>> +        * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>> +        * Old decimal value is wake up time in multiples of 100 us.
>> +        */
>> +       if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
>> +               switch (psr_table->tp1_wakeup_time) {
>> +               case 0:
>> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
>> +                       break;
>> +               case 1:
>> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
>> +                       break;
>> +               case 3:
>> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +                       break;
>> +               default:
>> +                       DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is
> outside range[0-3], defaulting to max value 2500us\n",
>> +                                       psr_table->tp1_wakeup_time);
>> +               case 2:
>> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
>> +                       break;
>> +               }
>> +
>> +               switch (psr_table->tp2_tp3_wakeup_time) {
>> +               case 0:
>> +                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
>> +                       break;
>> +               case 1:
>> +                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
>> +                       break;
>> +               case 3:
>> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +                       break;
>> +               default:
>> +                       DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d
> is outside range[0-3], defaulting to max value 2500us\n",
>> +                                       psr_table->tp2_tp3_wakeup_time);
>> +               case 2:
>> +                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
>> +               break;
>> +               }
>> +       } else {
>> +               dev_priv->vbt.psr.tp1_wakeup_time_us =
> psr_table->tp1_wakeup_time * 100;
>> +               dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> psr_table->tp2_tp3_wakeup_time * 100;
>> +       }
> Quick question:
> Why did you write the same thing twice instead of extract to a new function
> like this?
>
> dev_priv->vbt.psr.tp1_wakeup_time_us =
> vbt_psr_to_us(psr_table->tp1_wakeup_time)
> dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> vbt_psr_to_us(psr_table->tp2_tp3_wakeup_time)
>
> static int vbt_psr_to_us(int vbt_value) {
>      if (bdb->version >= 209 ...) {
>         return as {0:500, 1:100, 2:2500, 3:0}
>      return vbt_value * 100;
> }
Will make this change  in next version.
>>    }
>>    static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
>> index db27f2f..d64f039 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
> *intel_dp)
>>           if (dev_priv->psr.link_standby)
>>                   val |= EDP_PSR_LINK_STANDBY;
>> -       if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -               val |= EDP_PSR_TP1_TIME_2500us;
>> -       else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -               val |= EDP_PSR_TP1_TIME_500us;
>> -       else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +       if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>> +               val |=  EDP_PSR_TP1_TIME_0us;
>> +       else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>                   val |= EDP_PSR_TP1_TIME_100us;
>> +       else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>> +               val |= EDP_PSR_TP1_TIME_500us;
>>           else
>> -               val |= EDP_PSR_TP1_TIME_0us;
>> +               val |= EDP_PSR_TP1_TIME_2500us;
>> -       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -               val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -               val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>> +               val |=  EDP_PSR_TP2_TP3_TIME_0us;
>> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>                   val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +               val |= EDP_PSR_TP2_TP3_TIME_500us;
>>           else
>> -               val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +               val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>           if (intel_dp_source_supports_hbr2(intel_dp) &&
>>               drm_dp_tps3_supported(intel_dp->dpcd))
>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>
>>           val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency +
> 1);
>
>> -       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -               val |= EDP_PSR2_TP2_TIME_2500;
>> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -               val |= EDP_PSR2_TP2_TIME_500;
>> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -               val |= EDP_PSR2_TP2_TIME_100;
>> +       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>> +           dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>> +               val |= EDP_PSR2_TP2_TIME_50us;
>> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>> +               val |= EDP_PSR2_TP2_TIME_100us;
>> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +               val |= EDP_PSR2_TP2_TIME_500us;
>>           else
>> -               val |= EDP_PSR2_TP2_TIME_50;
>> +               val |= EDP_PSR2_TP2_TIME_2500us;
>>           I915_WRITE(EDP_PSR2_CTL, val);
>>    }
>> --
>> 1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-15 23:03 ` Dhinakaran Pandiyan
@ 2018-05-16  3:44   ` vathsala nagaraju
  2018-05-16  8:08     ` Jani Nikula
                       ` (2 more replies)
  0 siblings, 3 replies; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-16  3:44 UTC (permalink / raw)
  To: dhinakaran.pandiyan, rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wednesday 16 May 2018 04:33 AM, Dhinakaran Pandiyan wrote:
> On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version
>> check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having
>> this
>> change, limiting this change to gen9_bc and version 209+ to unblock
>> google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>      move the 165 version check to intel_bios.c
>> v3: Jani
>>      Move the abstraction to intel_bios.
>> v4: Jani
>>      Rename tp*_wakeup_time to have "us" suffix.
>>      For values outside range[0-3],default to max 2500us.
>>      Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>>      Handle option 2 in default condition.
>>      Print oustide range value.
>>      For negetive values default to 2500us.
>> v6: Jani
>>      Handle default first and then fall through for case 2.
>> v7: Rodrigo
>>      Apply this change for IS_GEN9_BC and vbt version > 209
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>   drivers/gpu/drm/i915/intel_bios.c | 46
>> +++++++++++++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------
>> ------
>>   4 files changed, 70 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 57fb3aa..268b059 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>   		bool require_aux_wakeup;
>>   		int idle_frames;
>>   		enum psr_lines_to_wait lines_to_wait;
>> -		int tp1_wakeup_time;
>> -		int tp2_tp3_wakeup_time;
>> +		int tp1_wakeup_time_us;
>> +		int tp2_tp3_wakeup_time_us;
>>   	} psr;
>>   
>>   	struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index f11bb21..6820658 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4088,10 +4088,10 @@ enum {
>>   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 54270bd..695ca73 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
>> drm_i915_private *dev_priv,
>>   		break;
>>   	}
>>   
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table-
>>> tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table-
>>> tp2_tp3_wakeup_time;
>> +	/*
>> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>> +	 * Old decimal value is wake up time in multiples of 100 us.
>> +	 */
>> +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> Since this is the 'new' mapping, shouldn't this check be
>
> if (version >= 209) {
>
> }
check is for bdb version.
> i.e., what versions do BXT, GLK, CFL and CNL have?
waiting for GOP's team confirmation on above platforms.
We can add them later.
>
> Since gen-9 tables can have ambiguous interpretations, I think we can
> do this.
>
> if (version >= 209 || (IS_GEN9() && wakeup_time <=3)) {
> 	// Read this as {0:500, 1:100, 2:2500, 3:0}
With old bsf file , it's multiple of 100 ms.
if user inputs  2  , thinking that  it's 200 ms , with above change we 
are setting this to  2500 ms.
As per old spec, it should be set to 500 ms.   (>1 , set to 500)
Jani /Maulik, is it okay to make the above change?
> } else {
> 	// Read this as wakeup_time * 100
> }
>
> This is assuming all versions => 209 use the new mapping consistently.
>
> 2 and 3 are invalid values in the x*100 us scheme, so we can assume it
> really means 2.5 ms and 0.
> 1 means the same.
> 0 is a problem, but we can check dpcd 0071h to confirm whether the sink
> needs training or not. And it is safer to assume the sink needs
> training at interpret is as 500 us.

+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d
is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);
+		/*fall through*/
		case 2:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+

> nit: That's an interesting order, it is neither sorted by the switch
> variable nor by wake up time. It is easier to read if you chose one way
> or the other IMO.
As per Jani's suggesttion , we need to set 2500ms for out of range[0-3]. 
It's a fall through.
should i add comment /*fall through*/  as above?
>   
>> +		switch (psr_table->tp2_tp3_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>> 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>> 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		default:
>> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value
>> %d is outside range[0-3], defaulting to max value 2500us\n",
>> +					psr_table-
>>> tp2_tp3_wakeup_time);
>> +		case 2:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>> 2500;
>> +		break;
>> +		}
>> +	} else {
>> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table-
>>> tp1_wakeup_time * 100;
>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
>> psr_table->tp2_tp3_wakeup_time * 100;
>> +	}
>>   }
>>   
>>   static void parse_dsi_backlight_ports(struct drm_i915_private
>> *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index db27f2f..d64f039 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
>> *intel_dp)
>>   	if (dev_priv->psr.link_standby)
>>   		val |= EDP_PSR_LINK_STANDBY;
>>   
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>> +		val |=  EDP_PSR_TP1_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>   		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP1_TIME_500us;
>>   	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>   	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>   
>>   	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>   	    drm_dp_tps3_supported(intel_dp->dpcd))
>> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
>> *intel_dp)
>>   
>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv-
>>> psr.sink_sync_latency + 1);
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
>> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>> +		val |= EDP_PSR2_TP2_TIME_50us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>> +		val |= EDP_PSR2_TP2_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>   	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>   
>>   	I915_WRITE(EDP_PSR2_CTL, val);
>>   }

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-14  3:32 vathsala nagaraju
  2018-05-15 22:55 ` Puthikorn Voravootivat
@ 2018-05-15 23:03 ` Dhinakaran Pandiyan
  2018-05-16  3:44   ` vathsala nagaraju
  1 sibling, 1 reply; 45+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-15 23:03 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> 
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version
> check
> to change for all the platforms.
> 
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having
> this
> change, limiting this change to gen9_bc and version 209+ to unblock
> google.
> 
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
> 
> bspec 20131
> 
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us.
> v6: Jani
>     Handle default first and then fall through for case 2.
> v7: Rodrigo
>     Apply this change for IS_GEN9_BC and vbt version > 209
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> 
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 46
> +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------
> ------
>  4 files changed, 70 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 57fb3aa..268b059 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index f11bb21..6820658 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4088,10 +4088,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bd..695ca73 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
> drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table-
> >tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table-
> >tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {

Since this is the 'new' mapping, shouldn't this check be

if (version >= 209) {

}
i.e., what versions do BXT, GLK, CFL and CNL have?

Since gen-9 tables can have ambiguous interpretations, I think we can
do this.

if (version >= 209 || (IS_GEN9() && wakeup_time <=3)) {
	// Read this as {0:500, 1:100, 2:2500, 3:0}
} else {
	// Read this as wakeup_time * 100
}

This is assuming all versions => 209 use the new mapping consistently. 

2 and 3 are invalid values in the x*100 us scheme, so we can assume it
really means 2.5 ms and 0.
1 means the same.
0 is a problem, but we can check dpcd 0071h to confirm whether the sink
needs training or not. And it is safer to assume the sink needs
training at interpret is as 500 us.



> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d
> is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +

nit: That's an interesting order, it is neither sorted by the switch
variable nor by wake up time. It is easier to read if you chose one way
or the other IMO.

 
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value
> %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table-
> >tp2_tp3_wakeup_time);
> +		case 2:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table-
> >tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
> psr_table->tp2_tp3_wakeup_time * 100;

> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private
> *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2f..d64f039 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
> *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv-
> >psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-14  3:32 vathsala nagaraju
@ 2018-05-15 22:55 ` Puthikorn Voravootivat
  2018-05-16  3:48   ` vathsala nagaraju
  2018-05-15 23:03 ` Dhinakaran Pandiyan
  1 sibling, 1 reply; 45+ messages in thread
From: Puthikorn Voravootivat @ 2018-05-15 22:55 UTC (permalink / raw)
  To: vathsala nagaraju
  Cc: Puthikorn Voravootivat, intel-gfx, maulik.v.vaghela, Rodrigo Vivi

On Sun, May 13, 2018 at 8:32 PM vathsala nagaraju <
vathsala.nagaraju@intel.com> wrote:

> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.

> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to gen9_bc and version 209+ to unblock
google.

> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.

> bspec 20131

> v2: (Jani and Rodrigo)
>      move the 165 version check to intel_bios.c
> v3: Jani
>      Move the abstraction to intel_bios.
> v4: Jani
>      Rename tp*_wakeup_time to have "us" suffix.
>      For values outside range[0-3],default to max 2500us.
>      Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>      Handle option 2 in default condition.
>      Print oustide range value.
>      For negetive values default to 2500us.
> v6: Jani
>      Handle default first and then fall through for case 2.
> v7: Rodrigo
>      Apply this change for IS_GEN9_BC and vbt version > 209

> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>

> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>   drivers/gpu/drm/i915/intel_bios.c | 46
+++++++++++++++++++++++++++++++++++++--
>   drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
>   4 files changed, 70 insertions(+), 27 deletions(-)

> diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
> index 57fb3aa..268b059 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>                  bool require_aux_wakeup;
>                  int idle_frames;
>                  enum psr_lines_to_wait lines_to_wait;
> -               int tp1_wakeup_time;
> -               int tp2_tp3_wakeup_time;
> +               int tp1_wakeup_time_us;
> +               int tp2_tp3_wakeup_time_us;
>          } psr;

>          struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
> index f11bb21..6820658 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4088,10 +4088,10 @@ enum {
>   #define   EDP_Y_COORDINATE_ENABLE      (1<<25) /* GLK and CNL+ */
>   #define   EDP_MAX_SU_DISABLE_TIME(t)   ((t)<<20)
>   #define   EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500                (0<<8)
> -#define   EDP_PSR2_TP2_TIME_100                (1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500       (2<<8)
> -#define   EDP_PSR2_TP2_TIME_50         (3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us      (0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us      (1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us     (2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us       (3<<8)
>   #define   EDP_PSR2_TP2_TIME_MASK       (3<<8)
>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK        (0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bd..695ca73 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct
drm_i915_private *dev_priv,
>                  break;
>          }

> -       dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -       dev_priv->vbt.psr.tp2_tp3_wakeup_time =
psr_table->tp2_tp3_wakeup_time;
> +       /*
> +        * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +        * Old decimal value is wake up time in multiples of 100 us.
> +        */
> +       if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> +               switch (psr_table->tp1_wakeup_time) {
> +               case 0:
> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +                       break;
> +               case 1:
> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +                       break;
> +               case 3:
> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +                       break;
> +               default:
> +                       DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is
outside range[0-3], defaulting to max value 2500us\n",
> +                                       psr_table->tp1_wakeup_time);
> +               case 2:
> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +                       break;
> +               }
> +
> +               switch (psr_table->tp2_tp3_wakeup_time) {
> +               case 0:
> +                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +                       break;
> +               case 1:
> +                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +                       break;
> +               case 3:
> +                       dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +                       break;
> +               default:
> +                       DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d
is outside range[0-3], defaulting to max value 2500us\n",
> +                                       psr_table->tp2_tp3_wakeup_time);
> +               case 2:
> +                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +               break;
> +               }
> +       } else {
> +               dev_priv->vbt.psr.tp1_wakeup_time_us =
psr_table->tp1_wakeup_time * 100;
> +               dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
psr_table->tp2_tp3_wakeup_time * 100;
> +       }

Quick question:
Why did you write the same thing twice instead of extract to a new function
like this?

dev_priv->vbt.psr.tp1_wakeup_time_us =
vbt_psr_to_us(psr_table->tp1_wakeup_time)
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
vbt_psr_to_us(psr_table->tp2_tp3_wakeup_time)

static int vbt_psr_to_us(int vbt_value) {
    if (bdb->version >= 209 ...) {
       return as {0:500, 1:100, 2:2500, 3:0}
    return vbt_value * 100;
}
>   }

>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2f..d64f039 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
*intel_dp)
>          if (dev_priv->psr.link_standby)
>                  val |= EDP_PSR_LINK_STANDBY;

> -       if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -               val |= EDP_PSR_TP1_TIME_2500us;
> -       else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -               val |= EDP_PSR_TP1_TIME_500us;
> -       else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +       if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +               val |=  EDP_PSR_TP1_TIME_0us;
> +       else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>                  val |= EDP_PSR_TP1_TIME_100us;
> +       else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +               val |= EDP_PSR_TP1_TIME_500us;
>          else
> -               val |= EDP_PSR_TP1_TIME_0us;
> +               val |= EDP_PSR_TP1_TIME_2500us;

> -       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -               val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -               val |= EDP_PSR_TP2_TP3_TIME_500us;
> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +               val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>                  val |= EDP_PSR_TP2_TP3_TIME_100us;
> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +               val |= EDP_PSR_TP2_TP3_TIME_500us;
>          else
> -               val |= EDP_PSR_TP2_TP3_TIME_0us;
> +               val |= EDP_PSR_TP2_TP3_TIME_2500us;

>          if (intel_dp_source_supports_hbr2(intel_dp) &&
>              drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
*intel_dp)

>          val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency +
1);

> -       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -               val |= EDP_PSR2_TP2_TIME_2500;
> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -               val |= EDP_PSR2_TP2_TIME_500;
> -       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -               val |= EDP_PSR2_TP2_TIME_100;
> +       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +           dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +               val |= EDP_PSR2_TP2_TIME_50us;
> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +               val |= EDP_PSR2_TP2_TIME_100us;
> +       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +               val |= EDP_PSR2_TP2_TIME_500us;
>          else
> -               val |= EDP_PSR2_TP2_TIME_50;
> +               val |= EDP_PSR2_TP2_TIME_2500us;

>          I915_WRITE(EDP_PSR2_CTL, val);
>   }
> --
> 1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-14  3:32 vathsala nagaraju
  2018-05-15 22:55 ` Puthikorn Voravootivat
  2018-05-15 23:03 ` Dhinakaran Pandiyan
  0 siblings, 2 replies; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-14  3:32 UTC (permalink / raw)
  To: rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us.
v6: Jani
    Handle default first and then fall through for case 2.
v7: Rodrigo
    Apply this change for IS_GEN9_BC and vbt version > 209

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
 4 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57fb3aa..268b059 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f11bb21..6820658 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4088,10 +4088,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 54270bd..695ca73 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -688,8 +688,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);
+		case 2:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp2_tp3_wakeup_time);
+		case 2:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2f..d64f039 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-03 17:13   ` Nagaraju, Vathsala
@ 2018-05-04 23:13     ` Puthikorn Voravootivat
  0 siblings, 0 replies; 45+ messages in thread
From: Puthikorn Voravootivat @ 2018-05-04 23:13 UTC (permalink / raw)
  To: vathsala nagaraju
  Cc: Puthikorn Voravootivat, intel-gfx, maulik.v.vaghela, Rodrigo Vivi

FYI, Here is the the BDB version of the chip that need this change in
Google Pixelbook.

localhost ~ # uname -p
Intel(R) Core(TM) i5-7Y57 CPU @ 1.20GHz
localhost ~ # dmesg | grep VBT.signature
[    0.298850] VBT signature "$VBT SKYLAKE        ", BDB version 211

localhost ~ #  uname -p
Intel(R) Core(TM) i7-7Y75 CPU @ 1.30GHz
localhost ~ # dmesg | grep VBT.signature
[    0.273325] VBT signature "$VBT SKYLAKE        ", BDB version 211

Best,


On Thu, May 3, 2018 at 10:14 AM Nagaraju, Vathsala <
vathsala.nagaraju@intel.com> wrote:

> Rodrigo,

>          The changes are already in place on kabylake 209+ onwards, So
limiting  this change to only kabylake  and confirmed vbt version for now.
>          RCR is already raised for GOP team to resolve. Once we get the
other platform confirmation, we  can add those platforms too.

> Here is what happen in Skylake VBT description file , this is decimal ,
no wake options.
> [1] $PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples
of 100
> [2] EditNum $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", DEC,
>   Help "This field selects the link training TP2(Training Pattern2) or
TP3(Training Pattern3) time during PSR exit(wake up)\n"
>   "TP2/TP3 wake up time in multiples of 100us"

> Here is what happen in Kaby Lake VBT description file , this is
wakeoptions [0-3]
> [3] $PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples
of 100
> [4] Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:",
&PsrWakeupTimeOptions,
>   Help "This field selects the link training TP2(Training Pattern2) or
TP3(Training Pattern3) time during PSR exit(wake up)\n"
> [5] List &PsrWakeupTimeOptions↵
> Selection 0x00, "500 usec"↵
> Selection 0x01, "100 usec"↵
> Selection 0x02, "2.5 msec"↵
> Selection 0x03, "0 (Skip)"↵
> EndList↵

> Regards,
> Vathsala

> -----Original Message-----
> From: Vivi, Rodrigo
> Sent: Thursday, May 3, 2018 9:15 PM
> To: Nagaraju, Vathsala <vathsala.nagaraju@intel.com>
> Cc: jani.nikula@linux.intel.com; intel-gfx@lists.freedesktop.org;
Puthikorn Voravootivat <puthik@chromium.org>; Vaghela, Maulik V <
maulik.v.vaghela@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: vbt change for psr

> On Thu, May 03, 2018 at 05:06:09PM +0530, vathsala nagaraju wrote:
> > From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> >
> > For psr block #9, the vbt description has moved to options [0-3] for
> > TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> > structure. Since spec does not  mention from which VBT version this
> > change was added to vbt.bsf file, we cannot depend on bdb->version
> > check to change for all the platforms.
> >
> > There is RCR inplace for GOP team to  provide the version number to
> > make generic change. Since Kabylake with bdb version 209 is having
> > this change, limiting this change to kbl and version 209+ to unblock
google.
> >
> > Tested on skl(bdb version 203,without options) and kabylake(bdb
> > version 209,212) having new options.
> >
> > bspec 20131
> >
> > v2: (Jani and Rodrigo)
> >     move the 165 version check to intel_bios.c
> > v3: Jani
> >     Move the abstraction to intel_bios.
> > v4: Jani
> >     Rename tp*_wakeup_time to have "us" suffix.
> >     For values outside range[0-3],default to max 2500us.
> >     Old decimal value was wake up time in multiples of 100us.
> > v5: Jani and Rodrigo
> >     Handle option 2 in default condition.
> >     Print oustide range value.
> >     For negetive values default to 2500us.
> > v6: Jani
> >     Handle default first and then fall through for case 2.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Puthikorn Voravootivat <puthik@chromium.org>
> >
> > Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
> >  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
> >  drivers/gpu/drm/i915/intel_bios.c | 46
> > +++++++++++++++++++++++++++++++++++++--
> >  drivers/gpu/drm/i915/intel_psr.c  | 39
> > +++++++++++++++++----------------
> >  4 files changed, 70 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 6268a51..a189382 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
> >               bool require_aux_wakeup;
> >               int idle_frames;
> >               enum psr_lines_to_wait lines_to_wait;
> > -             int tp1_wakeup_time;
> > -             int tp2_tp3_wakeup_time;
> > +             int tp1_wakeup_time_us;
> > +             int tp2_tp3_wakeup_time_us;
> >       } psr;
> >
> >       struct {
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 197c966..6bbd0b4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4084,10 +4084,10 @@ enum {
> >  #define   EDP_Y_COORDINATE_ENABLE    (1<<25) /* GLK and CNL+ */
> >  #define   EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
> >  #define   EDP_MAX_SU_DISABLE_TIME_MASK       (0x1f<<20)
> > -#define   EDP_PSR2_TP2_TIME_500              (0<<8)
> > -#define   EDP_PSR2_TP2_TIME_100              (1<<8)
> > -#define   EDP_PSR2_TP2_TIME_2500     (2<<8)
> > -#define   EDP_PSR2_TP2_TIME_50               (3<<8)
> > +#define   EDP_PSR2_TP2_TIME_500us    (0<<8)
> > +#define   EDP_PSR2_TP2_TIME_100us    (1<<8)
> > +#define   EDP_PSR2_TP2_TIME_2500us   (2<<8)
> > +#define   EDP_PSR2_TP2_TIME_50us     (3<<8)
> >  #define   EDP_PSR2_TP2_TIME_MASK     (3<<8)
> >  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> >  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK      (0xf<<4)
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > b/drivers/gpu/drm/i915/intel_bios.c
> > index 702d3fa..166f704 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct
drm_i915_private *dev_priv,
> >               break;
> >       }
> >
> > -     dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> > -     dev_priv->vbt.psr.tp2_tp3_wakeup_time =
psr_table->tp2_tp3_wakeup_time;
> > +     /*
> > +      * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> > +      * Old decimal value is wake up time in multiples of 100 us.
> > +      */
> > +     if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {

> Please file a BSpec bug and get that mess cleaned up first before
spreading it here.

> I'm looking to the same 20131 and it says "wake up time in multiples of
100" and VBT version 165

> Ok, I also see on 20131 the mention to:

> "
>   0 = 500 usec
>   1 = 100 usec
>   2 = 2.5 msec
>   3 = 0 usec (Skip TP1)
> "

> But it has absolutely no mention to "209" or "Kabylake" or any other
platform.

> I doubt that it would be for Kabylake and not for Coffelake for instance.


> Thanks,
> Rodrigo.

> > +             switch (psr_table->tp1_wakeup_time) {
> > +             case 0:
> > +                     dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> > +                     break;
> > +             case 1:
> > +                     dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> > +                     break;
> > +             case 3:
> > +                     dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> > +                     break;
> > +             default:
> > +                     DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is
outside range[0-3], defaulting to max value 2500us\n",
> > +                                     psr_table->tp1_wakeup_time);
> > +             case 2:
> > +                     dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> > +                     break;
> > +             }
> > +
> > +             switch (psr_table->tp2_tp3_wakeup_time) {
> > +             case 0:
> > +                     dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> > +                     break;
> > +             case 1:
> > +                     dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> > +                     break;
> > +             case 3:
> > +                     dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> > +                     break;
> > +             default:
> > +                     DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d
is outside range[0-3], \
> > +                                     defaulting to max value
2500us\n", psr_table->tp2_tp3_wakeup_time);
> > +             case 2:
> > +                     dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> > +             break;
> > +             }
> > +     } else {
> > +             dev_priv->vbt.psr.tp1_wakeup_time_us =
psr_table->tp1_wakeup_time * 100;
> > +             dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
psr_table->tp2_tp3_wakeup_time * 100;
> > +     }
> >  }
> >
> >  static void parse_dsi_backlight_ports(struct drm_i915_private
> > *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 6233a32..f03dfba 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp
*intel_dp)
> >       if (dev_priv->psr.link_standby)
> >               val |= EDP_PSR_LINK_STANDBY;
> >
> > -     if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> > -             val |= EDP_PSR_TP1_TIME_2500us;
> > -     else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> > -             val |= EDP_PSR_TP1_TIME_500us;
> > -     else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> > +     if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> > +             val |=  EDP_PSR_TP1_TIME_0us;
> > +     else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> >               val |= EDP_PSR_TP1_TIME_100us;
> > +     else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> > +             val |= EDP_PSR_TP1_TIME_500us;
> >       else
> > -             val |= EDP_PSR_TP1_TIME_0us;
> > +             val |= EDP_PSR_TP1_TIME_2500us;
> >
> > -     if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> > -             val |= EDP_PSR_TP2_TP3_TIME_2500us;
> > -     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > -             val |= EDP_PSR_TP2_TP3_TIME_500us;
> > -     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> > +     if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> > +             val |=  EDP_PSR_TP2_TP3_TIME_0us;
> > +     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> >               val |= EDP_PSR_TP2_TP3_TIME_100us;
> > +     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> > +             val |= EDP_PSR_TP2_TP3_TIME_500us;
> >       else
> > -             val |= EDP_PSR_TP2_TP3_TIME_0us;
> > +             val |= EDP_PSR_TP2_TP3_TIME_2500us;
> >
> >       if (intel_dp_source_supports_hbr2(intel_dp) &&
> >           drm_dp_tps3_supported(intel_dp->dpcd))
> > @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> >
> >       val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency +
> > 1);
> >
> > -     if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> > -             val |= EDP_PSR2_TP2_TIME_2500;
> > -     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > -             val |= EDP_PSR2_TP2_TIME_500;
> > -     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> > -             val |= EDP_PSR2_TP2_TIME_100;
> > +     if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> > +         dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> > +             val |= EDP_PSR2_TP2_TIME_50us;
> > +     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> > +             val |= EDP_PSR2_TP2_TIME_100us;
> > +     else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> > +             val |= EDP_PSR2_TP2_TIME_500us;
> >       else
> > -             val |= EDP_PSR2_TP2_TIME_50;
> > +             val |= EDP_PSR2_TP2_TIME_2500us;
> >
> >       I915_WRITE(EDP_PSR2_CTL, val);
> >  }
> > --
> > 1.9.1
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-03 15:44 ` Rodrigo Vivi
@ 2018-05-03 17:13   ` Nagaraju, Vathsala
  2018-05-04 23:13     ` Puthikorn Voravootivat
  0 siblings, 1 reply; 45+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-03 17:13 UTC (permalink / raw)
  To: Vivi, Rodrigo; +Cc: Puthikorn Voravootivat, intel-gfx, Vaghela, Maulik V

Rodrigo,

	The changes are already in place on kabylake 209+ onwards, So limiting  this change to only kabylake  and confirmed vbt version for now.
	RCR is already raised for GOP team to resolve. Once we get the other platform confirmation, we  can add those platforms too.

Here is what happen in Skylake VBT description file , this is decimal , no wake options.
[1] $PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100
[2] EditNum $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", DEC,
 Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
 "TP2/TP3 wake up time in multiples of 100us"

Here is what happen in Kaby Lake VBT description file , this is wakeoptions [0-3]
[3] $PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100
[4] Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
 Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
[5] List &PsrWakeupTimeOptions↵
Selection 0x00, "500 usec"↵
Selection 0x01, "100 usec"↵
Selection 0x02, "2.5 msec"↵
Selection 0x03, "0 (Skip)"↵
EndList↵	
		
Regards,
Vathsala

-----Original Message-----
From: Vivi, Rodrigo 
Sent: Thursday, May 3, 2018 9:15 PM
To: Nagaraju, Vathsala <vathsala.nagaraju@intel.com>
Cc: jani.nikula@linux.intel.com; intel-gfx@lists.freedesktop.org; Puthikorn Voravootivat <puthik@chromium.org>; Vaghela, Maulik V <maulik.v.vaghela@intel.com>
Subject: Re: [PATCH] drm/i915/psr: vbt change for psr

On Thu, May 03, 2018 at 05:06:09PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> 
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt 
> structure. Since spec does not  mention from which VBT version this 
> change was added to vbt.bsf file, we cannot depend on bdb->version 
> check to change for all the platforms.
> 
> There is RCR inplace for GOP team to  provide the version number to 
> make generic change. Since Kabylake with bdb version 209 is having 
> this change, limiting this change to kbl and version 209+ to unblock google.
> 
> Tested on skl(bdb version 203,without options) and kabylake(bdb 
> version 209,212) having new options.
> 
> bspec 20131
> 
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us.
> v6: Jani
>     Handle default first and then fall through for case 2.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> 
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 46 
> +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 
> +++++++++++++++++----------------
>  4 files changed, 70 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> b/drivers/gpu/drm/i915/i915_drv.h index 6268a51..a189382 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> b/drivers/gpu/drm/i915/i915_reg.h index 197c966..6bbd0b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4084,10 +4084,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..166f704 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {

Please file a BSpec bug and get that mess cleaned up first before spreading it here.

I'm looking to the same 20131 and it says "wake up time in multiples of 100" and VBT version 165

Ok, I also see on 20131 the mention to:

"
 0 = 500 usec
 1 = 100 usec
 2 = 2.5 msec
 3 = 0 usec (Skip TP1)
"

But it has absolutely no mention to "209" or "Kabylake" or any other platform.

I doubt that it would be for Kabylake and not for Coffelake for instance.


Thanks,
Rodrigo.

> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
> +					defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
> +		case 2:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private 
> *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 6233a32..f03dfba 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp 
> *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 
> 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
> --
> 1.9.1
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-03 11:36 vathsala nagaraju
@ 2018-05-03 15:44 ` Rodrigo Vivi
  2018-05-03 17:13   ` Nagaraju, Vathsala
  0 siblings, 1 reply; 45+ messages in thread
From: Rodrigo Vivi @ 2018-05-03 15:44 UTC (permalink / raw)
  To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, Maulik V Vaghela

On Thu, May 03, 2018 at 05:06:09PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> 
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
> 
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
> 
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
> 
> bspec 20131
> 
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us.
> v6: Jani
>     Handle default first and then fall through for case 2.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> 
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
>  4 files changed, 70 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6268a51..a189382 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..6bbd0b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4084,10 +4084,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..166f704 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {

Please file a BSpec bug and get that mess cleaned up first before spreading it here.

I'm looking to the same 20131 and it says "wake up time in multiples of 100" and VBT version 165

Ok, I also see on 20131 the mention to:

"
 0 = 500 usec
 1 = 100 usec
 2 = 2.5 msec
 3 = 0 usec (Skip TP1)
"

But it has absolutely no mention to "209" or "Kabylake" or any other platform.

I doubt that it would be for Kabylake and not for Coffelake for instance.

Thanks,
Rodrigo.

> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +					psr_table->tp1_wakeup_time);
> +		case 2:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
> +					defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
> +		case 2:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6233a32..f03dfba 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
> -- 
> 1.9.1
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-03 11:36 vathsala nagaraju
  2018-05-03 15:44 ` Rodrigo Vivi
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-03 11:36 UTC (permalink / raw)
  To: rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us.
v6: Jani
    Handle default first and then fall through for case 2.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
 4 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6268a51..a189382 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,8 +1077,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..6bbd0b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4084,10 +4084,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 702d3fa..166f704 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+					psr_table->tp1_wakeup_time);
+		case 2:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
+					defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
+		case 2:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6233a32..f03dfba 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-03  9:08 vathsala nagaraju
@ 2018-05-03  9:39 ` Jani Nikula
  0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-05-03  9:39 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Thu, 03 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
>  4 files changed, 70 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6268a51..a189382 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..6bbd0b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4084,10 +4084,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..bb61ad8 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			if (psr_table->tp1_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +						psr_table->tp1_wakeup_time);
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}

		default:
			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", psr_table->tp1_wakeup_time);
                        /* fallthrough */
		case 2:
			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
			break;

> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			if (psr_table->tp2_tp3_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
> +						defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6233a32..f03dfba 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-03  9:08 vathsala nagaraju
  2018-05-03  9:39 ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-03  9:08 UTC (permalink / raw)
  To: rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
 4 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6268a51..a189382 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,8 +1077,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..6bbd0b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4084,10 +4084,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 702d3fa..bb61ad8 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			if (psr_table->tp1_wakeup_time != 2)
+				DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+						psr_table->tp1_wakeup_time);
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			if (psr_table->tp2_tp3_wakeup_time != 2)
+				DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
+						defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6233a32..f03dfba 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-02  9:13 vathsala nagaraju
  2018-05-02 21:15 ` Rodrigo Vivi
@ 2018-05-03  7:07 ` Jani Nikula
  1 sibling, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-05-03  7:07 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 02 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 45 +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 38 ++++++++++++++++-----------------
>  4 files changed, 68 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6268a51..a189382 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..6bbd0b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4084,10 +4084,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..a246b6b 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -687,8 +687,49 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/* new psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		case 2:
> +		default:
> +			if (psr_table->tp1_wakeup_time != 2)

You already have the "!= 2" and "== 2" differentiation above. Use
it. (Hint: fallthrough.)

> +				DRM_DEBUG_KMS("VBT tp1 wakeup time outside range, defaulting to max value 2500us\n");

If you complain about out of range value, please log the value.

> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		case 2:
> +		default:
> +			if (psr_table->tp2_tp3_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp2_tp3  wakeup time outside range, defaulting to max value 2500us\n");
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}

That's the same thing copy-pasted twice. If you don't fix it now, I'm
pretty sure the next person to stumble on this will send a patch to fix
it.

> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6233a32..746c5ac 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 0)

== 0. It should never be < 0, and if it is, go for the longest delay.

> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 0)

Same here.

> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;

So I didn't actually look at bspec now. But the they've got to be
kidding me. They first move away from specifying usecs in the bspec,
because hardware only supports certain values. And this looks like they
didn't take into account the 50 us delay? Really? Ugh.

BR,
Jani.

> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-02 21:15 ` Rodrigo Vivi
  2018-05-03  3:21   ` vathsala nagaraju
@ 2018-05-03  6:59   ` Jani Nikula
  1 sibling, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-05-03  6:59 UTC (permalink / raw)
  To: Rodrigo Vivi, vathsala nagaraju
  Cc: Puthikorn Voravootivat, intel-gfx, Maulik V Vaghela

On Wed, 02 May 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Wed, May 02, 2018 at 02:43:29PM +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> 
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>> 
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
>> 
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>> 
>> bspec 20131
>> 
>> v2: (Jani and Rodrigo)
>>     move the 165 version check to intel_bios.c
>> v3: Jani
>>     Move the abstraction to intel_bios.
>> v4: Jani
>>     Rename tp*_wakeup_time to have "us" suffix.
>>     For values outside range[0-3],default to max 2500us.
>>     Old decimal value was wake up time in multiples of 100us.
>> 
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> 
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>  drivers/gpu/drm/i915/intel_bios.c | 45 +++++++++++++++++++++++++++++++++++++--
>>  drivers/gpu/drm/i915/intel_psr.c  | 38 ++++++++++++++++-----------------
>>  4 files changed, 68 insertions(+), 27 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 6268a51..a189382 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>>  		bool require_aux_wakeup;
>>  		int idle_frames;
>>  		enum psr_lines_to_wait lines_to_wait;
>> -		int tp1_wakeup_time;
>> -		int tp2_tp3_wakeup_time;
>> +		int tp1_wakeup_time_us;
>> +		int tp2_tp3_wakeup_time_us;
>>  	} psr;
>>  
>>  	struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 197c966..6bbd0b4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4084,10 +4084,10 @@ enum {
>>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 702d3fa..a246b6b 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -687,8 +687,49 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>  		break;
>>  	}
>>  
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	/* new psr options 0=500us, 1=100us, 2=2500us, 3=0us
>> +	 * Old decimal value is wake up time in multiples of 100 us.
>> +	 */
>
> Please follow this style with first empty line:
>
> /*
>  * Text here
>  */
>
> Start with capital N on New.
>
>> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
>
> Why are we filtering per platform?
> What about Coffelake? And Geminilake? And Cannonlake? and on?

It's a mess. I hate it, but I guess no can do.

>
> Btw, where is this spec? I just checked predator and it still
> only contains the old multiple of 100 one... :(
>
>> +		switch (psr_table->tp1_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		case 2:
>
> this out of order case is not good imho...
> confusing... but well... 0 -> 2500 -> 100 -> 500 is already confusing by itself
> honestly...
>
>> +		default:
>
> why default is 2? higher?
> I always thought this awkward order was to make the 0 the default with 500
> or at least I was trying to make some sense on that order :/

The spec is silly. IMO they should have stuck to using usecs
directly. If the driver has to do a per platform mapping *anyway*, it's
better to do it from usecs directly than from some platform specific
index values.

Defaulting to longest when out of range is per my instruction. It should
handle the cases where the VBT actually has the usecs/100 value but
should have the new style. Did I mention this is a mess already?

BR,
Jani.

>
>> +			if (psr_table->tp1_wakeup_time != 2)
>> +				DRM_DEBUG_KMS("VBT tp1 wakeup time outside range, defaulting to max value 2500us\n");
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
>> +			break;
>> +		}
>> +
>> +		switch (psr_table->tp2_tp3_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		case 2:
>> +		default:
>> +			if (psr_table->tp2_tp3_wakeup_time != 2)
>> +				DRM_DEBUG_KMS("VBT tp2_tp3  wakeup time outside range, defaulting to max value 2500us\n");
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
>> +		break;
>> +		}
>> +	} else {
>> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
>> +	}
>>  }
>>  
>>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 6233a32..746c5ac 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>  	if (dev_priv->psr.link_standby)
>>  		val |= EDP_PSR_LINK_STANDBY;
>>  
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 0)
>> +		val |=  EDP_PSR_TP1_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>  		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP1_TIME_500us;
>>  	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>  
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>  	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>  
>>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>> @@ -513,14 +513,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  
>>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>  
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>> +		val |= EDP_PSR2_TP2_TIME_50us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>> +		val |= EDP_PSR2_TP2_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>  	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>  
>>  	I915_WRITE(EDP_PSR2_CTL, val);
>>  }
>> -- 
>> 1.9.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-02 21:15 ` Rodrigo Vivi
@ 2018-05-03  3:21   ` vathsala nagaraju
  2018-05-03  6:59   ` Jani Nikula
  1 sibling, 0 replies; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-03  3:21 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: Puthikorn Voravootivat, intel-gfx, Maulik V Vaghela

On Thursday 03 May 2018 02:45 AM, Rodrigo Vivi wrote:
> On Wed, May 02, 2018 at 02:43:29PM +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>      move the 165 version check to intel_bios.c
>> v3: Jani
>>      Move the abstraction to intel_bios.
>> v4: Jani
>>      Rename tp*_wakeup_time to have "us" suffix.
>>      For values outside range[0-3],default to max 2500us.
>>      Old decimal value was wake up time in multiples of 100us.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>   drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>>   drivers/gpu/drm/i915/intel_bios.c | 45 +++++++++++++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_psr.c  | 38 ++++++++++++++++-----------------
>>   4 files changed, 68 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 6268a51..a189382 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>>   		bool require_aux_wakeup;
>>   		int idle_frames;
>>   		enum psr_lines_to_wait lines_to_wait;
>> -		int tp1_wakeup_time;
>> -		int tp2_tp3_wakeup_time;
>> +		int tp1_wakeup_time_us;
>> +		int tp2_tp3_wakeup_time_us;
>>   	} psr;
>>   
>>   	struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 197c966..6bbd0b4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4084,10 +4084,10 @@ enum {
>>   #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>>   #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>>   #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>>   #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 702d3fa..a246b6b 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -687,8 +687,49 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   		break;
>>   	}
>>   
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	/* new psr options 0=500us, 1=100us, 2=2500us, 3=0us
>> +	 * Old decimal value is wake up time in multiples of 100 us.
>> +	 */
> Please follow this style with first empty line:
>
> /*
>   * Text here
>   */
>
> Start with capital N on New.
Thanks, will make the changes.
>
>> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
> Why are we filtering per platform?

What about Coffelake? And Geminilake? And Cannonlake? and on?

Once GOP team confirms the exact versions for other platforms, we will 
add them.
Please check my commit message.
>
> Btw, where is this spec? I just checked predator and it still
> only contains the old multiple of 100 one... :(
please check bspec 20131
>
>> +		switch (psr_table->tp1_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		case 2:
> this out of order case is not good imho...
> confusing... but well... 0 -> 2500 -> 100 -> 500 is already confusing by itself
> honestly...
>
>> +		default:
> why default is 2? higher?
> I always thought this awkward order was to make the 0 the default with 500
> or at least I was trying to make some sense on that order :/
Jani  suggested for 2500 for anything out of range [0-3]. Please check 
the thread https://patchwork.freedesktop.org/patch/217851/ , last 
message from Jani.
Since 2=2500 and outside range = 2500, I have ordered it that way in the 
code.

>
>> +			if (psr_table->tp1_wakeup_time != 2)
>> +				DRM_DEBUG_KMS("VBT tp1 wakeup time outside range, defaulting to max value 2500us\n");
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
>> +			break;
>> +		}
>> +
>> +		switch (psr_table->tp2_tp3_wakeup_time) {
>> +		case 0:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
>> +			break;
>> +		case 1:
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
>> +			break;
>> +		case 3:
>> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
>> +			break;
>> +		case 2:
>> +		default:
>> +			if (psr_table->tp2_tp3_wakeup_time != 2)
>> +				DRM_DEBUG_KMS("VBT tp2_tp3  wakeup time outside range, defaulting to max value 2500us\n");
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
>> +		break;
>> +		}
>> +	} else {
>> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
>> +	}
>>   }
>>   
>>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 6233a32..746c5ac 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>   	if (dev_priv->psr.link_standby)
>>   		val |= EDP_PSR_LINK_STANDBY;
>>   
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 0)
>> +		val |=  EDP_PSR_TP1_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>   		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP1_TIME_500us;
>>   	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>   	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>   
>>   	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>   	    drm_dp_tps3_supported(intel_dp->dpcd))
>> @@ -513,14 +513,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>   
>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
>> +		val |= EDP_PSR2_TP2_TIME_50us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>> +		val |= EDP_PSR2_TP2_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>> +		val |= EDP_PSR2_TP2_TIME_500us;
>>   	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> +		val |= EDP_PSR2_TP2_TIME_2500us;
>>   
>>   	I915_WRITE(EDP_PSR2_CTL, val);
>>   }
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-05-02  9:13 vathsala nagaraju
@ 2018-05-02 21:15 ` Rodrigo Vivi
  2018-05-03  3:21   ` vathsala nagaraju
  2018-05-03  6:59   ` Jani Nikula
  2018-05-03  7:07 ` Jani Nikula
  1 sibling, 2 replies; 45+ messages in thread
From: Rodrigo Vivi @ 2018-05-02 21:15 UTC (permalink / raw)
  To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, Maulik V Vaghela

On Wed, May 02, 2018 at 02:43:29PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> 
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
> 
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
> 
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
> 
> bspec 20131
> 
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> 
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 45 +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 38 ++++++++++++++++-----------------
>  4 files changed, 68 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6268a51..a189382 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..6bbd0b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4084,10 +4084,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..a246b6b 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -687,8 +687,49 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/* new psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */

Please follow this style with first empty line:

/*
 * Text here
 */

Start with capital N on New.

> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {

Why are we filtering per platform?
What about Coffelake? And Geminilake? And Cannonlake? and on?

Btw, where is this spec? I just checked predator and it still
only contains the old multiple of 100 one... :(

> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		case 2:

this out of order case is not good imho...
confusing... but well... 0 -> 2500 -> 100 -> 500 is already confusing by itself
honestly...

> +		default:

why default is 2? higher?
I always thought this awkward order was to make the 0 the default with 500
or at least I was trying to make some sense on that order :/

> +			if (psr_table->tp1_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp1 wakeup time outside range, defaulting to max value 2500us\n");
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}
> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		case 2:
> +		default:
> +			if (psr_table->tp2_tp3_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp2_tp3  wakeup time outside range, defaulting to max value 2500us\n");
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6233a32..746c5ac 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-02  9:13 vathsala nagaraju
  2018-05-02 21:15 ` Rodrigo Vivi
  2018-05-03  7:07 ` Jani Nikula
  0 siblings, 2 replies; 45+ messages in thread
From: vathsala nagaraju @ 2018-05-02  9:13 UTC (permalink / raw)
  To: rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 45 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 38 ++++++++++++++++-----------------
 4 files changed, 68 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6268a51..a189382 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,8 +1077,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..6bbd0b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4084,10 +4084,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 702d3fa..a246b6b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -687,8 +687,49 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/* new psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		case 2:
+		default:
+			if (psr_table->tp1_wakeup_time != 2)
+				DRM_DEBUG_KMS("VBT tp1 wakeup time outside range, defaulting to max value 2500us\n");
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		case 2:
+		default:
+			if (psr_table->tp2_tp3_wakeup_time != 2)
+				DRM_DEBUG_KMS("VBT tp2_tp3  wakeup time outside range, defaulting to max value 2500us\n");
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6233a32..746c5ac 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-04-20  6:30   ` vathsala nagaraju
@ 2018-04-27  7:52     ` Jani Nikula
  0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-04-27  7:52 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Fri, 20 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> On Thursday 19 April 2018 07:05 PM, Jani Nikula wrote:
>> On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>>
>>> For psr block #9, the vbt description has moved to options [0-3] for
>>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>>> structure. Since spec does not  mention from which VBT version this
>>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>>> to change for all the platforms.
>>>
>>> There is RCR inplace for GOP team to  provide the version number
>>> to make generic change. Since Kabylake with bdb version 209 is having this
>>> change, limiting this change to kbl and version 209+ to unblock google.
>> This is an incredible mess.
>>
>>> Tested on skl(bdb version 203,without options) and
>>> kabylake(bdb version 209,212) having new options.
>>>
>>> bspec 20131
>>>
>>> v2: (Jani and Rodrigo)
>>>      move the 165 version check to intel_bios.c
>>> v3: Jani
>>>      move the abstraction to intel_bios
>>>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>>
>>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++---
>>>   drivers/gpu/drm/i915/intel_psr.c  | 26 ++++++++++++-------------
>>>   2 files changed, 50 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>>> index 702d3fa..8913dc8 100644
>>> --- a/drivers/gpu/drm/i915/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>>> @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>   	}
>>>   }
>>>   
>>> +static bool
>>> +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>> +{
>>> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
>>> +		return true;
>>> +	else
>>> +		return false;
>>> +}
>>> +
>>>   static void
>>>   parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>>   {
>>> @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>   		DRM_DEBUG_KMS("No PSR BDB found.\n");
>>>   		return;
>>>   	}
>>> -
>>>   	psr_table = &psr->psr_table[panel_type];
>>>   
>>>   	dev_priv->vbt.psr.full_link = psr_table->full_link;
>>> @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>>   		break;
>>>   	}
>>>   
>>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>>> +	/*  new psr options    old decimal value interpretation
>>> +	 *  0 [500 us]         > 1 [500 us ]
>>> +	 *  1 [100 us]         > 0 [100 us ]
>>> +	 *  2 [2.5 ms]         > 5 [2.5 ms ]
>>> +	 *  3 [0   us]         = 0 [0   us ]
>> The old decimal value stuff was wake up time in multiples of 100 us.
>>
>>> +	 */
>>> +	if (!is_psr_options(dev_priv, bdb)) {
>> You only use is_psr_options here once, please just open code the
>> condition. Also reverse order to not need !something in the condition.
>>
>>> +		if (psr_table->tp1_wakeup_time > 5)
>>> +			dev_priv->vbt.psr.tp1_wakeup_time = 2;
>>> +		else if (psr_table->tp1_wakeup_time > 1)
>>> +			dev_priv->vbt.psr.tp1_wakeup_time = 0;
>>> +		else if (psr_table->tp1_wakeup_time > 0)
>>> +			dev_priv->vbt.psr.tp1_wakeup_time = 1;
>>> +		else
>>> +			dev_priv->vbt.psr.tp1_wakeup_time = 3;
>>> +
>>> +		if (psr_table->tp2_tp3_wakeup_time > 5)
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2;
>>> +		else if (psr_table->tp2_tp3_wakeup_time > 1)
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0;
>>> +		else if (psr_table->tp1_wakeup_time > 0)
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1;
>>> +		else
>>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3;
>>> +	} else {
>>> +		dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>>> +	}
>>>   }
>> Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time
>> to have _us suffix, and actually assign the wakeup time in us
>> there. Hide all the hideous, hideous VBT stuff behind that, and doesn't
>> use magic numbers all over the place.
>>
>> The old format becomes wakeup_time_us = vbt_value * 100. The code should
>> handle mismatches between the value and what the hardware can do (see
>> below).
>>
>> The new format should just be a switch-case mapping values to us,
>> whining about values other than 0..3 and defaulting to max in that case.
> if we don't set anything in SRD_CTL/PSR2_CTL reg for those bits , by 
> default it's 0 [which is 500 us]
> instead of defaulting to max value which is 3[0us], should we just 
> default to 0[500us]

Like I said, if we think the VBT has the new format, and it has values
in range 0..3, map those to corresponding delays in us. 0 -> 500 us, 1
-> 100 us, 2 -> 2500 us, 3 -> 0 us. If the value is not in range 0..3,
*then* default to max i.e. 2500 us.

BR,
Jani.


>>>   
>>>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>> index 69a5b27..95658ad 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>>   	if (dev_priv->psr.link_standby)
>>>   		val |= EDP_PSR_LINK_STANDBY;
>>>   
>>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP1_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>>> +	if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>>>   		val |= EDP_PSR_TP1_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>>>   		val |= EDP_PSR_TP1_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
>>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>>   	else
>>>   		val |= EDP_PSR_TP1_TIME_0us;
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>>> +		val |=  EDP_PSR_TP2_TP3_TIME_500us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>>   	else
>>>   		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> Rewrite these to round up the longer wait:
>>
>>          if (wakeup_time_us == 0)
>> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> 	else if (wakeup_time_us <= 100)
>> 		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> 	else if (wakeup_time_us <= 500)
>> 		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> 	else
>> 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>
>>>   
>>> @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>   
>>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>>   
>>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>> -		val |= EDP_PSR2_TP2_TIME_2500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>>>   		val |= EDP_PSR2_TP2_TIME_500;
>>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>>>   		val |= EDP_PSR2_TP2_TIME_100;
>>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>>> +		val |= EDP_PSR2_TP2_TIME_2500;
>>>   	else
>>>   		val |= EDP_PSR2_TP2_TIME_50;
>> Same here.
>>
>> BR,
>> Jani.
>>
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-04-19 13:35 ` Jani Nikula
@ 2018-04-20  6:30   ` vathsala nagaraju
  2018-04-27  7:52     ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-04-20  6:30 UTC (permalink / raw)
  To: Jani Nikula, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Thursday 19 April 2018 07:05 PM, Jani Nikula wrote:
> On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
> This is an incredible mess.
>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>      move the 165 version check to intel_bios.c
>> v3: Jani
>>      move the abstraction to intel_bios
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++---
>>   drivers/gpu/drm/i915/intel_psr.c  | 26 ++++++++++++-------------
>>   2 files changed, 50 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 702d3fa..8913dc8 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   	}
>>   }
>>   
>> +static bool
>> +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>> +{
>> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
>> +		return true;
>> +	else
>> +		return false;
>> +}
>> +
>>   static void
>>   parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>   {
>> @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   		DRM_DEBUG_KMS("No PSR BDB found.\n");
>>   		return;
>>   	}
>> -
>>   	psr_table = &psr->psr_table[panel_type];
>>   
>>   	dev_priv->vbt.psr.full_link = psr_table->full_link;
>> @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   		break;
>>   	}
>>   
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	/*  new psr options    old decimal value interpretation
>> +	 *  0 [500 us]         > 1 [500 us ]
>> +	 *  1 [100 us]         > 0 [100 us ]
>> +	 *  2 [2.5 ms]         > 5 [2.5 ms ]
>> +	 *  3 [0   us]         = 0 [0   us ]
> The old decimal value stuff was wake up time in multiples of 100 us.
>
>> +	 */
>> +	if (!is_psr_options(dev_priv, bdb)) {
> You only use is_psr_options here once, please just open code the
> condition. Also reverse order to not need !something in the condition.
>
>> +		if (psr_table->tp1_wakeup_time > 5)
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 2;
>> +		else if (psr_table->tp1_wakeup_time > 1)
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 0;
>> +		else if (psr_table->tp1_wakeup_time > 0)
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 1;
>> +		else
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 3;
>> +
>> +		if (psr_table->tp2_tp3_wakeup_time > 5)
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2;
>> +		else if (psr_table->tp2_tp3_wakeup_time > 1)
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0;
>> +		else if (psr_table->tp1_wakeup_time > 0)
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1;
>> +		else
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3;
>> +	} else {
>> +		dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	}
>>   }
> Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time
> to have _us suffix, and actually assign the wakeup time in us
> there. Hide all the hideous, hideous VBT stuff behind that, and doesn't
> use magic numbers all over the place.
>
> The old format becomes wakeup_time_us = vbt_value * 100. The code should
> handle mismatches between the value and what the hardware can do (see
> below).
>
> The new format should just be a switch-case mapping values to us,
> whining about values other than 0..3 and defaulting to max in that case.
if we don't set anything in SRD_CTL/PSR2_CTL reg for those bits , by 
default it's 0 [which is 500 us]
instead of defaulting to max value which is 3[0us], should we just 
default to 0[500us]
>>   
>>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 69a5b27..95658ad 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>   	if (dev_priv->psr.link_standby)
>>   		val |= EDP_PSR_LINK_STANDBY;
>>   
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>>   		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>>   		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>   	else
>>   		val |= EDP_PSR_TP1_TIME_0us;
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_500us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>   	else
>>   		val |= EDP_PSR_TP2_TP3_TIME_0us;
> Rewrite these to round up the longer wait:
>
>          if (wakeup_time_us == 0)
> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
> 	else if (wakeup_time_us <= 100)
> 		val |= EDP_PSR_TP2_TP3_TIME_100us;
> 	else if (wakeup_time_us <= 500)
> 		val |= EDP_PSR_TP2_TP3_TIME_500us;
> 	else
> 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>
>>   
>> @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>   
>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>>   		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>>   		val |= EDP_PSR2_TP2_TIME_100;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +		val |= EDP_PSR2_TP2_TIME_2500;
>>   	else
>>   		val |= EDP_PSR2_TP2_TIME_50;
> Same here.
>
> BR,
> Jani.
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-04-19  7:42 vathsala nagaraju
@ 2018-04-19 13:35 ` Jani Nikula
  2018-04-20  6:30   ` vathsala nagaraju
  0 siblings, 1 reply; 45+ messages in thread
From: Jani Nikula @ 2018-04-19 13:35 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.

This is an incredible mess.

> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     move the abstraction to intel_bios
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/intel_psr.c  | 26 ++++++++++++-------------
>  2 files changed, 50 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..8913dc8 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +static bool
> +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
> +{
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
> +		return true;
> +	else
> +		return false;
> +}
> +
>  static void
>  parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  {
> @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		DRM_DEBUG_KMS("No PSR BDB found.\n");
>  		return;
>  	}
> -
>  	psr_table = &psr->psr_table[panel_type];
>  
>  	dev_priv->vbt.psr.full_link = psr_table->full_link;
> @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*  new psr options    old decimal value interpretation
> +	 *  0 [500 us]         > 1 [500 us ]
> +	 *  1 [100 us]         > 0 [100 us ]
> +	 *  2 [2.5 ms]         > 5 [2.5 ms ]
> +	 *  3 [0   us]         = 0 [0   us ]

The old decimal value stuff was wake up time in multiples of 100 us.

> +	 */
> +	if (!is_psr_options(dev_priv, bdb)) {

You only use is_psr_options here once, please just open code the
condition. Also reverse order to not need !something in the condition.

> +		if (psr_table->tp1_wakeup_time > 5)
> +			dev_priv->vbt.psr.tp1_wakeup_time = 2;
> +		else if (psr_table->tp1_wakeup_time > 1)
> +			dev_priv->vbt.psr.tp1_wakeup_time = 0;
> +		else if (psr_table->tp1_wakeup_time > 0)
> +			dev_priv->vbt.psr.tp1_wakeup_time = 1;
> +		else
> +			dev_priv->vbt.psr.tp1_wakeup_time = 3;
> +
> +		if (psr_table->tp2_tp3_wakeup_time > 5)
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2;
> +		else if (psr_table->tp2_tp3_wakeup_time > 1)
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0;
> +		else if (psr_table->tp1_wakeup_time > 0)
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1;
> +		else
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3;
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	}
>  }

Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time
to have _us suffix, and actually assign the wakeup time in us
there. Hide all the hideous, hideous VBT stuff behind that, and doesn't
use magic numbers all over the place.

The old format becomes wakeup_time_us = vbt_value * 100. The code should
handle mismatches between the value and what the hardware can do (see
below).

The new format should just be a switch-case mapping values to us,
whining about values other than 0..3 and defaulting to max in that case.

>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 69a5b27..95658ad 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>  		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  	else
>  		val |= EDP_PSR_TP1_TIME_0us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_500us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  	else
>  		val |= EDP_PSR_TP2_TP3_TIME_0us;

Rewrite these to round up the longer wait:

        if (wakeup_time_us == 0)
		val |= EDP_PSR_TP2_TP3_TIME_0us;
	else if (wakeup_time_us <= 100)
		val |= EDP_PSR_TP2_TP3_TIME_100us;
	else if (wakeup_time_us <= 500)
		val |= EDP_PSR_TP2_TP3_TIME_500us;
	else
		val |= EDP_PSR_TP2_TP3_TIME_2500us;

>  
> @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>  		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>  		val |= EDP_PSR2_TP2_TIME_100;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> +		val |= EDP_PSR2_TP2_TIME_2500;
>  	else
>  		val |= EDP_PSR2_TP2_TIME_50;

Same here.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-04-19  7:42 vathsala nagaraju
  2018-04-19 13:35 ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-04-19  7:42 UTC (permalink / raw)
  To: rodrigo.vivi, jani.nikula, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    move the abstraction to intel_bios

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_psr.c  | 26 ++++++++++++-------------
 2 files changed, 50 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 702d3fa..8913dc8 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 	}
 }
 
+static bool
+is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
+{
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
+		return true;
+	else
+		return false;
+}
+
 static void
 parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 {
@@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		DRM_DEBUG_KMS("No PSR BDB found.\n");
 		return;
 	}
-
 	psr_table = &psr->psr_table[panel_type];
 
 	dev_priv->vbt.psr.full_link = psr_table->full_link;
@@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*  new psr options    old decimal value interpretation
+	 *  0 [500 us]         > 1 [500 us ]
+	 *  1 [100 us]         > 0 [100 us ]
+	 *  2 [2.5 ms]         > 5 [2.5 ms ]
+	 *  3 [0   us]         = 0 [0   us ]
+	 */
+	if (!is_psr_options(dev_priv, bdb)) {
+		if (psr_table->tp1_wakeup_time > 5)
+			dev_priv->vbt.psr.tp1_wakeup_time = 2;
+		else if (psr_table->tp1_wakeup_time > 1)
+			dev_priv->vbt.psr.tp1_wakeup_time = 0;
+		else if (psr_table->tp1_wakeup_time > 0)
+			dev_priv->vbt.psr.tp1_wakeup_time = 1;
+		else
+			dev_priv->vbt.psr.tp1_wakeup_time = 3;
+
+		if (psr_table->tp2_tp3_wakeup_time > 5)
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2;
+		else if (psr_table->tp2_tp3_wakeup_time > 1)
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0;
+		else if (psr_table->tp1_wakeup_time > 0)
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1;
+		else
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3;
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 69a5b27..95658ad 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
+	if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
 		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
+		val |= EDP_PSR_TP1_TIME_2500us;
 	else
 		val |= EDP_PSR_TP1_TIME_0us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_500us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 	else
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 
@@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
 		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
 		val |= EDP_PSR2_TP2_TIME_100;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+		val |= EDP_PSR2_TP2_TIME_2500;
 	else
 		val |= EDP_PSR2_TP2_TIME_50;
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-04-11 17:57 vathsala nagaraju
@ 2018-04-12  9:26 ` Jani Nikula
  0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-04-12  9:26 UTC (permalink / raw)
  To: vathsala nagaraju, rodrigo.vivi, intel-gfx
  Cc: Puthikorn Voravootivat, Maulik V Vaghela

On Wed, 11 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.

The point was to move the whole abstraction to intel_bios.c, not just
the version check. To not need any is_tp_time_options field.

I think making platform based restrictions on the vbt fields unless
explicitly specified in the vbt bspec is the wrong thing to do.

BR,
Jani.

>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>  drivers/gpu/drm/i915/intel_bios.c |  3 ++
>  drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
>  3 files changed, 61 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b17..6aa6d68 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
>  		enum psr_lines_to_wait lines_to_wait;
>  		int tp1_wakeup_time;
>  		int tp2_tp3_wakeup_time;
> +		int is_tp_time_options;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index c5c7530..08e82e0 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -659,6 +659,9 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
> +		dev_priv->vbt.psr.is_tp_time_options = true;
> +
>  	psr_table = &psr->psr_table[panel_type];
>  
>  	dev_priv->vbt.psr.full_link = psr_table->full_link;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f73..74ed6d0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> -		val |= EDP_PSR_TP1_TIME_100us;
> -	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> -
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR_TP2_TP3_TIME_100us;
> -	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +	if (dev_priv->vbt.psr.is_tp_time_options) {
> +		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
> +			val |= EDP_PSR_TP1_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
> +			val |= EDP_PSR_TP1_TIME_100us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
> +			val |= EDP_PSR_TP1_TIME_2500us;
> +		else
> +			val |= EDP_PSR_TP1_TIME_0us;
> +	} else {
> +		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> +			val |= EDP_PSR_TP1_TIME_2500us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> +			val |= EDP_PSR_TP1_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +			val |= EDP_PSR_TP1_TIME_100us;
> +		else
> +			val |= EDP_PSR_TP1_TIME_0us;
> +	}
>  
> +	if (dev_priv->vbt.psr.is_tp_time_options) {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> +			val |=  EDP_PSR_TP2_TP3_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
> +		else
> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
> +	} else {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> +			val |= EDP_PSR_TP2_TP3_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
> +		else
> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
> +	}
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>  		val |= EDP_PSR_TP1_TP3_SEL;
> @@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	}
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
> -
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> -	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> -
> +	if (dev_priv->vbt.psr.is_tp_time_options) {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> +			val |= EDP_PSR2_TP2_TIME_500;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> +			val |= EDP_PSR2_TP2_TIME_100;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> +			val |= EDP_PSR2_TP2_TIME_2500;
> +		else
> +			val |= EDP_PSR2_TP2_TIME_50;
> +	} else {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> +			val |= EDP_PSR2_TP2_TIME_2500;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> +			val |= EDP_PSR2_TP2_TIME_500;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +			val |= EDP_PSR2_TP2_TIME_100;
> +		else
> +			val |= EDP_PSR2_TP2_TIME_50;
> +	}
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-04-11 17:57 vathsala nagaraju
  2018-04-12  9:26 ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-04-11 17:57 UTC (permalink / raw)
  To: rodrigo.vivi, intel-gfx; +Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c |  3 ++
 drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
 3 files changed, 61 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..6aa6d68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1075,6 +1075,7 @@ struct intel_vbt_data {
 		enum psr_lines_to_wait lines_to_wait;
 		int tp1_wakeup_time;
 		int tp2_tp3_wakeup_time;
+		int is_tp_time_options;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index c5c7530..08e82e0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -659,6 +659,9 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		return;
 	}
 
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
+		dev_priv->vbt.psr.is_tp_time_options = true;
+
 	psr_table = &psr->psr_table[panel_type];
 
 	dev_priv->vbt.psr.full_link = psr_table->full_link;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f73..74ed6d0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
-		val |= EDP_PSR_TP1_TIME_100us;
-	else
-		val |= EDP_PSR_TP1_TIME_0us;
-
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR_TP2_TP3_TIME_100us;
-	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+	if (dev_priv->vbt.psr.is_tp_time_options) {
+		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
+			val |= EDP_PSR_TP1_TIME_500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
+			val |= EDP_PSR_TP1_TIME_100us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
+			val |= EDP_PSR_TP1_TIME_2500us;
+		else
+			val |= EDP_PSR_TP1_TIME_0us;
+	} else {
+		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
+			val |= EDP_PSR_TP1_TIME_2500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
+			val |= EDP_PSR_TP1_TIME_500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+			val |= EDP_PSR_TP1_TIME_100us;
+		else
+			val |= EDP_PSR_TP1_TIME_0us;
+	}
 
+	if (dev_priv->vbt.psr.is_tp_time_options) {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+			val |=  EDP_PSR_TP2_TP3_TIME_500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+			val |= EDP_PSR_TP2_TP3_TIME_100us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+			val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		else
+			val |= EDP_PSR_TP2_TP3_TIME_0us;
+	} else {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+			val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+			val |= EDP_PSR_TP2_TP3_TIME_500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+			val |= EDP_PSR_TP2_TP3_TIME_100us;
+		else
+			val |= EDP_PSR_TP2_TP3_TIME_0us;
+	}
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
 		val |= EDP_PSR_TP1_TP3_SEL;
@@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
-
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
-	else
-		val |= EDP_PSR2_TP2_TIME_50;
-
+	if (dev_priv->vbt.psr.is_tp_time_options) {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+			val |= EDP_PSR2_TP2_TIME_500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+			val |= EDP_PSR2_TP2_TIME_100;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+			val |= EDP_PSR2_TP2_TIME_2500;
+		else
+			val |= EDP_PSR2_TP2_TIME_50;
+	} else {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+			val |= EDP_PSR2_TP2_TIME_2500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+			val |= EDP_PSR2_TP2_TIME_500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+			val |= EDP_PSR2_TP2_TIME_100;
+		else
+			val |= EDP_PSR2_TP2_TIME_50;
+	}
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-04-06 17:41 ` Rodrigo Vivi
@ 2018-04-09 13:57   ` Jani Nikula
  0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2018-04-09 13:57 UTC (permalink / raw)
  To: Rodrigo Vivi, vathsala nagaraju
  Cc: Puthikorn Voravootivat, intel-gfx, Maulik V Vaghela

On Fri, 06 Apr 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> 
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>> 
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
>> 
>> bspec 20131
>> 
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> 
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>>  drivers/gpu/drm/i915/intel_bios.c |  2 +-
>>  drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
>>  3 files changed, 59 insertions(+), 28 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 5373b17..a47be19b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
>>  		enum psr_lines_to_wait lines_to_wait;
>>  		int tp1_wakeup_time;
>>  		int tp2_tp3_wakeup_time;
>> +		int bdb_version;
>
> please keep the vbt stuff inside intel_bios.c
>
> so there at intel_bios.c you parse the vbt and based on the vbt version
> you export in a standard way to intel_psr.c

Exactly! struct intel_vbt_data is supposed to be an abstraction.

BR,
Jani.

>
>>  	} psr;
>>  
>>  	struct {
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index c5c7530..cfefd32 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>  		DRM_DEBUG_KMS("No PSR BDB found.\n");
>>  		return;
>>  	}
>> -
>> +	dev_priv->vbt.psr.bdb_version = bdb->version;
>>  	psr_table = &psr->psr_table[panel_type];
>>  
>>  	dev_priv->vbt.psr.full_link = psr_table->full_link;
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 2d53f73..e470d5e 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>  	if (dev_priv->psr.link_standby)
>>  		val |= EDP_PSR_LINK_STANDBY;
>>  
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> -		val |= EDP_PSR_TP1_TIME_100us;
>> -	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> -
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> -	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>> +			val |= EDP_PSR_TP1_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>> +			val |= EDP_PSR_TP1_TIME_100us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
>> +			val |= EDP_PSR_TP1_TIME_2500us;
>> +		else
>> +			val |= EDP_PSR_TP1_TIME_0us;
>> +	} else {
>> +		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> +			val |= EDP_PSR_TP1_TIME_2500us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> +			val |= EDP_PSR_TP1_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +			val |= EDP_PSR_TP1_TIME_100us;
>> +		else
>> +			val |= EDP_PSR_TP1_TIME_0us;
>> +	}
>>  
>> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +			val |=  EDP_PSR_TP2_TP3_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> +		else
>> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +	} else {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> +			val |= EDP_PSR_TP2_TP3_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +		else
>> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +	}
>>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>>  		val |= EDP_PSR_TP1_TP3_SEL;
>> @@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  	}
>>  
>>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>> -
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> -	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> -
>> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +			val |= EDP_PSR2_TP2_TIME_500;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>> +			val |= EDP_PSR2_TP2_TIME_100;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +			val |= EDP_PSR2_TP2_TIME_2500;
>> +		else
>> +			val |= EDP_PSR2_TP2_TIME_50;
>> +	} else {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> +			val |= EDP_PSR2_TP2_TIME_2500;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> +			val |= EDP_PSR2_TP2_TIME_500;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +			val |= EDP_PSR2_TP2_TIME_100;
>> +		else
>> +			val |= EDP_PSR2_TP2_TIME_50;
>> +	}
>>  	I915_WRITE(EDP_PSR2_CTL, val);
>>  }
>>  
>> -- 
>> 1.9.1
>> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH] drm/i915/psr: vbt change for psr
  2018-04-06 17:28 vathsala nagaraju
@ 2018-04-06 17:41 ` Rodrigo Vivi
  2018-04-09 13:57   ` Jani Nikula
  0 siblings, 1 reply; 45+ messages in thread
From: Rodrigo Vivi @ 2018-04-06 17:41 UTC (permalink / raw)
  To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, Maulik V Vaghela

On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> 
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
> 
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
> 
> bspec 20131
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> 
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>  drivers/gpu/drm/i915/intel_bios.c |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
>  3 files changed, 59 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b17..a47be19b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
>  		enum psr_lines_to_wait lines_to_wait;
>  		int tp1_wakeup_time;
>  		int tp2_tp3_wakeup_time;
> +		int bdb_version;

please keep the vbt stuff inside intel_bios.c

so there at intel_bios.c you parse the vbt and based on the vbt version
you export in a standard way to intel_psr.c

>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index c5c7530..cfefd32 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		DRM_DEBUG_KMS("No PSR BDB found.\n");
>  		return;
>  	}
> -
> +	dev_priv->vbt.psr.bdb_version = bdb->version;
>  	psr_table = &psr->psr_table[panel_type];
>  
>  	dev_priv->vbt.psr.full_link = psr_table->full_link;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f73..e470d5e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> -		val |= EDP_PSR_TP1_TIME_100us;
> -	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> -
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR_TP2_TP3_TIME_100us;
> -	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
> +		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
> +			val |= EDP_PSR_TP1_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
> +			val |= EDP_PSR_TP1_TIME_100us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
> +			val |= EDP_PSR_TP1_TIME_2500us;
> +		else
> +			val |= EDP_PSR_TP1_TIME_0us;
> +	} else {
> +		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> +			val |= EDP_PSR_TP1_TIME_2500us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> +			val |= EDP_PSR_TP1_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +			val |= EDP_PSR_TP1_TIME_100us;
> +		else
> +			val |= EDP_PSR_TP1_TIME_0us;
> +	}
>  
> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> +			val |=  EDP_PSR_TP2_TP3_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
> +		else
> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
> +	} else {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> +			val |= EDP_PSR_TP2_TP3_TIME_500us;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
> +		else
> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
> +	}
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>  		val |= EDP_PSR_TP1_TP3_SEL;
> @@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	}
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
> -
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> -	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> -
> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> +			val |= EDP_PSR2_TP2_TIME_500;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> +			val |= EDP_PSR2_TP2_TIME_100;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> +			val |= EDP_PSR2_TP2_TIME_2500;
> +		else
> +			val |= EDP_PSR2_TP2_TIME_50;
> +	} else {
> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> +			val |= EDP_PSR2_TP2_TIME_2500;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> +			val |= EDP_PSR2_TP2_TIME_500;
> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +			val |= EDP_PSR2_TP2_TIME_100;
> +		else
> +			val |= EDP_PSR2_TP2_TIME_50;
> +	}
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
>  
> -- 
> 1.9.1
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-04-06 17:28 vathsala nagaraju
  2018-04-06 17:41 ` Rodrigo Vivi
  0 siblings, 1 reply; 45+ messages in thread
From: vathsala nagaraju @ 2018-04-06 17:28 UTC (permalink / raw)
  To: rodrigo.vivi, intel-gfx; +Cc: Puthikorn Voravootivat, Maulik V Vaghela

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

bspec 20131

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c |  2 +-
 drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
 3 files changed, 59 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..a47be19b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1075,6 +1075,7 @@ struct intel_vbt_data {
 		enum psr_lines_to_wait lines_to_wait;
 		int tp1_wakeup_time;
 		int tp2_tp3_wakeup_time;
+		int bdb_version;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index c5c7530..cfefd32 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		DRM_DEBUG_KMS("No PSR BDB found.\n");
 		return;
 	}
-
+	dev_priv->vbt.psr.bdb_version = bdb->version;
 	psr_table = &psr->psr_table[panel_type];
 
 	dev_priv->vbt.psr.full_link = psr_table->full_link;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f73..e470d5e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
-		val |= EDP_PSR_TP1_TIME_100us;
-	else
-		val |= EDP_PSR_TP1_TIME_0us;
-
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR_TP2_TP3_TIME_100us;
-	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
+		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
+			val |= EDP_PSR_TP1_TIME_500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
+			val |= EDP_PSR_TP1_TIME_100us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
+			val |= EDP_PSR_TP1_TIME_2500us;
+		else
+			val |= EDP_PSR_TP1_TIME_0us;
+	} else {
+		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
+			val |= EDP_PSR_TP1_TIME_2500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
+			val |= EDP_PSR_TP1_TIME_500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+			val |= EDP_PSR_TP1_TIME_100us;
+		else
+			val |= EDP_PSR_TP1_TIME_0us;
+	}
 
+	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+			val |=  EDP_PSR_TP2_TP3_TIME_500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+			val |= EDP_PSR_TP2_TP3_TIME_100us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+			val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		else
+			val |= EDP_PSR_TP2_TP3_TIME_0us;
+	} else {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+			val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+			val |= EDP_PSR_TP2_TP3_TIME_500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+			val |= EDP_PSR_TP2_TP3_TIME_100us;
+		else
+			val |= EDP_PSR_TP2_TP3_TIME_0us;
+	}
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
 		val |= EDP_PSR_TP1_TP3_SEL;
@@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
-
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
-	else
-		val |= EDP_PSR2_TP2_TIME_50;
-
+	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+			val |= EDP_PSR2_TP2_TIME_500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+			val |= EDP_PSR2_TP2_TIME_100;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+			val |= EDP_PSR2_TP2_TIME_2500;
+		else
+			val |= EDP_PSR2_TP2_TIME_50;
+	} else {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+			val |= EDP_PSR2_TP2_TIME_2500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+			val |= EDP_PSR2_TP2_TIME_500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+			val |= EDP_PSR2_TP2_TIME_100;
+		else
+			val |= EDP_PSR2_TP2_TIME_50;
+	}
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 45+ messages in thread

end of thread, other threads:[~2018-05-24 13:00 UTC | newest]

Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-23  3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
2018-05-23  3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
2018-05-23  3:45 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
2018-05-23 12:55   ` Nagaraju, Vathsala
2018-05-23 13:10     ` Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2018-05-22  9:27 vathsala nagaraju
2018-05-22 12:46 ` Jani Nikula
2018-05-24 13:04   ` Jani Nikula
2018-05-18  8:55 vathsala nagaraju
2018-05-18  9:31 ` Jani Nikula
2018-05-22  4:48   ` Nagaraju, Vathsala
2018-05-22  8:05     ` Jani Nikula
2018-05-22  8:36       ` Nagaraju, Vathsala
2018-05-14  3:32 vathsala nagaraju
2018-05-15 22:55 ` Puthikorn Voravootivat
2018-05-16  3:48   ` vathsala nagaraju
2018-05-15 23:03 ` Dhinakaran Pandiyan
2018-05-16  3:44   ` vathsala nagaraju
2018-05-16  8:08     ` Jani Nikula
2018-05-16 17:44       ` Dhinakaran Pandiyan
2018-05-17  8:02         ` Jani Nikula
2018-05-17 20:12           ` Dhinakaran Pandiyan
2018-05-16  8:13     ` Jani Nikula
2018-05-16 22:04     ` Dhinakaran Pandiyan
2018-05-03 11:36 vathsala nagaraju
2018-05-03 15:44 ` Rodrigo Vivi
2018-05-03 17:13   ` Nagaraju, Vathsala
2018-05-04 23:13     ` Puthikorn Voravootivat
2018-05-03  9:08 vathsala nagaraju
2018-05-03  9:39 ` Jani Nikula
2018-05-02  9:13 vathsala nagaraju
2018-05-02 21:15 ` Rodrigo Vivi
2018-05-03  3:21   ` vathsala nagaraju
2018-05-03  6:59   ` Jani Nikula
2018-05-03  7:07 ` Jani Nikula
2018-04-19  7:42 vathsala nagaraju
2018-04-19 13:35 ` Jani Nikula
2018-04-20  6:30   ` vathsala nagaraju
2018-04-27  7:52     ` Jani Nikula
2018-04-11 17:57 vathsala nagaraju
2018-04-12  9:26 ` Jani Nikula
2018-04-06 17:28 vathsala nagaraju
2018-04-06 17:41 ` Rodrigo Vivi
2018-04-09 13:57   ` Jani Nikula

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.