From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DAF6E95A67 for ; Sun, 8 Oct 2023 22:49:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 1ACD6C433C9; Sun, 8 Oct 2023 22:49:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED42CC433C8; Sun, 8 Oct 2023 22:49:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696805345; bh=q6irQmc/ar88/WyLaaYVx14j01aGQa7xgLmo/8bprj8=; h=Date:Subject:To:List-Id:Cc:References:From:In-Reply-To:From; b=hPUUdcq3+V/SLFk0UE932qjJ42u0MlaA9EPleyYD7Jq+dMounHe07LeY0VdzteZBw X5wxf0KssB6GOJZgdFSk8ck5DsXzlZIB9E27o6Wn69Tcx/L8NiZn0pgar5wyW1Zqek E1jFaBw+aR/uYaS15V55JaaO0KvbGzkESZsLP+2qs0N7y39kQu1p7ZxWhT8C+zUr7P gJv1vplV3jcc55x5esq9luxoTKXTJprPpKYMH1YB4wPIeUHUBh1QcUL9l5sAm2nKff OwAmZ84/7aMGQiQJ5AxFJayxEIHey4E6SJjjc3DLmQVXs7s2lhPm9YF/QwXzyuandJ u+39E9D+Yo3cg== Message-ID: Date: Mon, 9 Oct 2023 07:48:59 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices Content-Language: en-US To: Peter Griffin , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com List-Id: Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org References: <20231005155618.700312-1-peter.griffin@linaro.org> <20231005155618.700312-10-peter.griffin@linaro.org> From: Chanwoo Choi In-Reply-To: <20231005155618.700312-10-peter.griffin@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 23. 10. 6. 00:56, Peter Griffin wrote: > CMU_TOP geneerates clocks for all the other CMU units. Add clock s/geneerates/generates > indices for those PLLs, muxes, dividers and gates. > > Signed-off-by: Peter Griffin > --- > include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++ > 1 file changed, 204 insertions(+) > create mode 100644 include/dt-bindings/clock/gs101.h > > diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h > new file mode 100644 > index 000000000000..d1e216a33aeb > --- /dev/null > +++ b/include/dt-bindings/clock/gs101.h > @@ -0,0 +1,204 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin > + * > + * Device Tree binding constants for Google gs101 clock controller. > + */ > + > +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > + > +/* CMU_TOP PLL*/ > +#define CLK_FOUT_SHARED0_PLL 1 > +#define CLK_FOUT_SHARED1_PLL 2 > +#define CLK_FOUT_SHARED2_PLL 3 > +#define CLK_FOUT_SHARED3_PLL 4 > +#define CLK_FOUT_SPARE_PLL 5 > + > +/* CMU_TOP MUX*/ > +#define CLK_MOUT_SHARED0_PLL 6 > +#define CLK_MOUT_SHARED1_PLL 7 > +#define CLK_MOUT_SHARED2_PLL 8 > +#define CLK_MOUT_SHARED3_PLL 9 > +#define CLK_MOUT_SPARE_PLL 10 > +#define CLK_MOUT_BUS0_BUS 11 > +#define CLK_MOUT_CMU_BOOST 12 > +#define CLK_MOUT_BUS1_BUS 13 > +#define CLK_MOUT_BUS2_BUS 14 > +#define CLK_MOUT_CORE_BUS 15 > +#define CLK_MOUT_EH_BUS 16 > +#define CLK_MOUT_CPUCL2_SWITCH 17 > +#define CLK_MOUT_CPUCL1_SWITCH 18 > +#define CLK_MOUT_CPUCL0_SWITCH 19 > +#define CLK_MOUT_CPUCL0_DBG 20 > +#define CLK_MOUT_CMU_HPM 21 > +#define CLK_MOUT_G3D_SWITCH 22 > +#define CLK_MOUT_G3D_GLB 23 > +#define CLK_MOUT_DPU_BUS 24 > +#define CLK_MOUT_DISP_BUS 25 > +#define CLK_MOUT_G2D_G2D 26 > +#define CLK_MOUT_G2D_MSCL 27 > +#define CLK_MOUT_HSI0_USB31DRD 28 > +#define CLK_MOUT_HSI0_BUS 29 > +#define CLK_MOUT_HSI0_DPGTC 30 > +#define CLK_MOUT_HSI0_USBDPDGB 31 > +#define CLK_MOUT_HSI1_BUS 32 > +#define CLK_MOUT_HSI1_PCIE 33 > +#define CLK_MOUT_HSI2_BUS 34 > +#define CLK_MOUT_HSI2_PCIE 35 > +#define CLK_MOUT_HSI2_UFS_EMBD 36 > +#define CLK_MOUT_HSI2_MMC_CARD 37 > +#define CLK_MOUT_CSIS 38 > +#define CLK_MOUT_PDP_BUS 39 > +#define CLK_MOUT_PDP_VRA 40 > +#define CLK_MOUT_IPP_BUS 41 > +#define CLK_MOUT_G3AA 42 > +#define CLK_MOUT_ITP 43 > +#define CLK_MOUT_DNS_BUS 44 > +#define CLK_MOUT_TNR_BUS 45 > +#define CLK_MOUT_MCSC_ITSC 46 > +#define CLK_MOUT_MCSC_MCSC 47 > +#define CLK_MOUT_GDC_SCSC 48 > +#define CLK_MOUT_GDC_GDC0 49 > +#define CLK_MOUT_GDC_GDC1 50 > +#define CLK_MOUT_MFC_MFC 51 > +#define CLK_MOUT_MIF_SWITCH 52 > +#define CLK_MOUT_MIF_BUS 53 > +#define CLK_MOUT_MISC_BUS 54 > +#define CLK_MOUT_MISC_SSS 55 > +#define CLK_MOUT_PERIC0_IP 56 > +#define CLK_MOUT_PERIC0_BUS 57 > +#define CLK_MOUT_PERIC1_IP 58 > +#define CLK_MOUT_PERIC1_BUS 59 > +#define CLK_MOUT_TPU_TPU 60 > +#define CLK_MOUT_TPU_TPUCTL 61 > +#define CLK_MOUT_TPU_BUS 62 > +#define CLK_MOUT_TPU_UART 63 > +#define CLK_MOUT_TPU_HPM 64 > +#define CLK_MOUT_BO_BUS 65 > +#define CLK_MOUT_G3D_BUSD 66 > + > +/* CMU_TOP Dividers*/ > +#define CLK_DOUT_SHARED0_DIV3 67 > +#define CLK_DOUT_SHARED0_DIV2 68 > +#define CLK_DOUT_SHARED0_DIV4 69 > +#define CLK_DOUT_SHARED0_DIV5 70 > +#define CLK_DOUT_SHARED1_DIV3 71 > +#define CLK_DOUT_SHARED1_DIV2 72 > +#define CLK_DOUT_SHARED1_DIV4 73 > +#define CLK_DOUT_SHARED2_DIV2 74 > +#define CLK_DOUT_SHARED3_DIV2 75 > +#define CLK_DOUT_BUS0_BUS 76 > +#define CLK_DOUT_CMU_BOOST 77 > +#define CLK_DOUT_BUS1_BUS 78 > +#define CLK_DOUT_BUS2_BUS 79 > +#define CLK_DOUT_CORE_BUS 80 > +#define CLK_DOUT_EH_BUS 81 > +#define CLK_DOUT_CPUCL2_SWITCH 82 > +#define CLK_DOUT_CPUCL1_SWITCH 83 > +#define CLK_DOUT_CPUCL0_SWITCH 84 > +#define CLK_DOUT_CPUCL0_DBG 85 > +#define CLK_DOUT_CMU_HPM 86 > +#define CLK_DOUT_G3D_SWITCH 87 > +#define CLK_DOUT_G3D_GLB 88 > +#define CLK_DOUT_DPU_BUS 89 > +#define CLK_DOUT_DISP_BUS 90 > +#define CLK_DOUT_G2D_G2D 91 > +#define CLK_DOUT_G2D_MSCL 92 > +#define CLK_DOUT_HSI0_USB31DRD 93 > +#define CLK_DOUT_HSI0_BUS 94 > +#define CLK_DOUT_HSI0_DPGTC 95 > +#define CLK_DOUT_HSI0_USBDPDGB 96 > +#define CLK_DOUT_HSI1_BUS 97 > +#define CLK_DOUT_HSI1_PCIE 98 > +#define CLK_DOUT_HSI2_BUS 100 > +#define CLK_DOUT_HSI2_PCIE 101 > +#define CLK_DOUT_HSI2_UFS_EMBD 102 > +#define CLK_DOUT_HSI2_MMC_CARD 103 > +#define CLK_DOUT_CSIS 104 > +#define CLK_DOUT_PDP_BUS 105 > +#define CLK_DOUT_PDP_VRA 106 > +#define CLK_DOUT_IPP_BUS 107 > +#define CLK_DOUT_G3AA 108 > +#define CLK_DOUT_ITP 109 > +#define CLK_DOUT_DNS_BUS 110 > +#define CLK_DOUT_TNR_BUS 111 > +#define CLK_DOUT_MCSC_ITSC 112 > +#define CLK_DOUT_MCSC_MCSC 113 > +#define CLK_DOUT_GDC_SCSC 114 > +#define CLK_DOUT_GDC_GDC0 115 > +#define CLK_DOUT_GDC_GDC1 116 > +#define CLK_DOUT_MFC_MFC 117 > +#define CLK_DOUT_MIF_BUS 118 > +#define CLK_DOUT_MISC_BUS 119 > +#define CLK_DOUT_MISC_SSS 120 > +#define CLK_DOUT_PERIC0_BUS 121 > +#define CLK_DOUT_PERIC0_IP 122 > +#define CLK_DOUT_PERIC1_BUS 123 > +#define CLK_DOUT_PERIC1_IP 124 > +#define CLK_DOUT_TPU_TPU 125 > +#define CLK_DOUT_TPU_TPUCTL 126 > +#define CLK_DOUT_TPU_BUS 127 > +#define CLK_DOUT_TPU_UART 128 > +#define CLK_DOUT_TPU_HPM 129 > +#define CLK_DOUT_BO_BUS 130 > + > +/* CMU_TOP Gates*/ > +#define CLK_GOUT_BUS0_BUS 131 > +#define CLK_GOUT_BUS1_BUS 132 > +#define CLK_GOUT_BUS2_BUS 133 > +#define CLK_GOUT_CORE_BUS 134 > +#define CLK_GOUT_EH_BUS 135 > +#define CLK_GOUT_CPUCL2_SWITCH 136 > +#define CLK_GOUT_CPUCL1_SWITCH 137 > +#define CLK_GOUT_CPUCL0_SWITCH 138 > +#define CLK_GOUT_CPUCL0_DBG 139 > +#define CLK_GOUT_CMU_HPM 140 > +#define CLK_GOUT_G3D_SWITCH 141 > +#define CLK_GOUT_G3D_GLB 142 > +#define CLK_GOUT_DPU_BUS 143 > +#define CLK_GOUT_DISP_BUS 144 > +#define CLK_GOUT_G2D_G2D 145 > +#define CLK_GOUT_G2D_MSCL 146 > +#define CLK_GOUT_HSI0_USB31DRD 147 > +#define CLK_GOUT_HSI0_BUS 148 > +#define CLK_GOUT_HSI0_DPGTC 149 > +#define CLK_GOUT_HSI0_USBDPDGB 150 > +#define CLK_GOUT_HSI1_BUS 151 > +#define CLK_GOUT_HSI1_PCIE 152 > +#define CLK_GOUT_HSI2_BUS 153 > +#define CLK_GOUT_HSI2_PCIE 154 > +#define CLK_GOUT_HSI2_UFS_EMBD 155 > +#define CLK_GOUT_HSI2_MMC_CARD 156 > +#define CLK_GOUT_CSIS 157 > +#define CLK_GOUT_PDP_BUS 158 > +#define CLK_GOUT_PDP_VRA 159 > +#define CLK_GOUT_IPP_BUS 160 > +#define CLK_GOUT_G3AA 161 > +#define CLK_GOUT_ITP 162 > +#define CLK_GOUT_DNS_BUS 163 > +#define CLK_GOUT_TNR_BUS 164 > +#define CLK_GOUT_MCSC_ITSC 165 > +#define CLK_GOUT_MCSC_MCSC 166 > +#define CLK_GOUT_GDC_SCSC 167 > +#define CLK_GOUT_GDC_GDC0 168 > +#define CLK_GOUT_GDC_GDC1 169 > +#define CLK_GOUT_MFC_MFC 170 > +#define CLK_GOUT_MIF_SWITCH 171 > +#define CLK_GOUT_MIF_BUS 172 > +#define CLK_GOUT_MISC_BUS 173 > +#define CLK_GOUT_MISC_SSS 174 > +#define CLK_GOUT_PERIC0_BUS 175 > +#define CLK_GOUT_PERIC0_IP 176 > +#define CLK_GOUT_PERIC1_BUS 177 > +#define CLK_GOUT_PERIC1_IP 178 > +#define CLK_GOUT_TPU_TPU 179 > +#define CLK_GOUT_TPU_TPUCTL 180 > +#define CLK_GOUT_TPU_BUS 181 > +#define CLK_GOUT_TPU_UART 182 > +#define CLK_GOUT_TPU_HPM 183 > +#define CLK_GOUT_BO_BUS 184 > +#define CLK_GOUT_CMU_BOOST 185 > + > +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ -- Best Regards, Samsung Electronics Chanwoo Choi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43100E95A8E for ; Sun, 8 Oct 2023 22:49:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: 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(Postfix) with ESMTP id E520CCE0A11; Sun, 8 Oct 2023 22:49:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED42CC433C8; Sun, 8 Oct 2023 22:49:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696805345; bh=q6irQmc/ar88/WyLaaYVx14j01aGQa7xgLmo/8bprj8=; h=Date:Subject:To:List-Id:Cc:References:From:In-Reply-To:From; b=hPUUdcq3+V/SLFk0UE932qjJ42u0MlaA9EPleyYD7Jq+dMounHe07LeY0VdzteZBw X5wxf0KssB6GOJZgdFSk8ck5DsXzlZIB9E27o6Wn69Tcx/L8NiZn0pgar5wyW1Zqek E1jFaBw+aR/uYaS15V55JaaO0KvbGzkESZsLP+2qs0N7y39kQu1p7ZxWhT8C+zUr7P gJv1vplV3jcc55x5esq9luxoTKXTJprPpKYMH1YB4wPIeUHUBh1QcUL9l5sAm2nKff OwAmZ84/7aMGQiQJ5AxFJayxEIHey4E6SJjjc3DLmQVXs7s2lhPm9YF/QwXzyuandJ u+39E9D+Yo3cg== Message-ID: Date: Mon, 9 Oct 2023 07:48:59 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices Content-Language: en-US To: Peter Griffin , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org References: <20231005155618.700312-1-peter.griffin@linaro.org> <20231005155618.700312-10-peter.griffin@linaro.org> From: Chanwoo Choi In-Reply-To: <20231005155618.700312-10-peter.griffin@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231008_154908_783839_5268D012 X-CRM114-Status: GOOD ( 13.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 23. 10. 6. 00:56, Peter Griffin wrote: > CMU_TOP geneerates clocks for all the other CMU units. Add clock s/geneerates/generates > indices for those PLLs, muxes, dividers and gates. > > Signed-off-by: Peter Griffin > --- > include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++ > 1 file changed, 204 insertions(+) > create mode 100644 include/dt-bindings/clock/gs101.h > > diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h > new file mode 100644 > index 000000000000..d1e216a33aeb > --- /dev/null > +++ b/include/dt-bindings/clock/gs101.h > @@ -0,0 +1,204 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin > + * > + * Device Tree binding constants for Google gs101 clock controller. > + */ > + > +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > + > +/* CMU_TOP PLL*/ > +#define CLK_FOUT_SHARED0_PLL 1 > +#define CLK_FOUT_SHARED1_PLL 2 > +#define CLK_FOUT_SHARED2_PLL 3 > +#define CLK_FOUT_SHARED3_PLL 4 > +#define CLK_FOUT_SPARE_PLL 5 > + > +/* CMU_TOP MUX*/ > +#define CLK_MOUT_SHARED0_PLL 6 > +#define CLK_MOUT_SHARED1_PLL 7 > +#define CLK_MOUT_SHARED2_PLL 8 > +#define CLK_MOUT_SHARED3_PLL 9 > +#define CLK_MOUT_SPARE_PLL 10 > +#define CLK_MOUT_BUS0_BUS 11 > +#define CLK_MOUT_CMU_BOOST 12 > +#define CLK_MOUT_BUS1_BUS 13 > +#define CLK_MOUT_BUS2_BUS 14 > +#define CLK_MOUT_CORE_BUS 15 > +#define CLK_MOUT_EH_BUS 16 > +#define CLK_MOUT_CPUCL2_SWITCH 17 > +#define CLK_MOUT_CPUCL1_SWITCH 18 > +#define CLK_MOUT_CPUCL0_SWITCH 19 > +#define CLK_MOUT_CPUCL0_DBG 20 > +#define CLK_MOUT_CMU_HPM 21 > +#define CLK_MOUT_G3D_SWITCH 22 > +#define CLK_MOUT_G3D_GLB 23 > +#define CLK_MOUT_DPU_BUS 24 > +#define CLK_MOUT_DISP_BUS 25 > +#define CLK_MOUT_G2D_G2D 26 > +#define CLK_MOUT_G2D_MSCL 27 > +#define CLK_MOUT_HSI0_USB31DRD 28 > +#define CLK_MOUT_HSI0_BUS 29 > +#define CLK_MOUT_HSI0_DPGTC 30 > +#define CLK_MOUT_HSI0_USBDPDGB 31 > +#define CLK_MOUT_HSI1_BUS 32 > +#define CLK_MOUT_HSI1_PCIE 33 > +#define CLK_MOUT_HSI2_BUS 34 > +#define CLK_MOUT_HSI2_PCIE 35 > +#define CLK_MOUT_HSI2_UFS_EMBD 36 > +#define CLK_MOUT_HSI2_MMC_CARD 37 > +#define CLK_MOUT_CSIS 38 > +#define CLK_MOUT_PDP_BUS 39 > +#define CLK_MOUT_PDP_VRA 40 > +#define CLK_MOUT_IPP_BUS 41 > +#define CLK_MOUT_G3AA 42 > +#define CLK_MOUT_ITP 43 > +#define CLK_MOUT_DNS_BUS 44 > +#define CLK_MOUT_TNR_BUS 45 > +#define CLK_MOUT_MCSC_ITSC 46 > +#define CLK_MOUT_MCSC_MCSC 47 > +#define CLK_MOUT_GDC_SCSC 48 > +#define CLK_MOUT_GDC_GDC0 49 > +#define CLK_MOUT_GDC_GDC1 50 > +#define CLK_MOUT_MFC_MFC 51 > +#define CLK_MOUT_MIF_SWITCH 52 > +#define CLK_MOUT_MIF_BUS 53 > +#define CLK_MOUT_MISC_BUS 54 > +#define CLK_MOUT_MISC_SSS 55 > +#define CLK_MOUT_PERIC0_IP 56 > +#define CLK_MOUT_PERIC0_BUS 57 > +#define CLK_MOUT_PERIC1_IP 58 > +#define CLK_MOUT_PERIC1_BUS 59 > +#define CLK_MOUT_TPU_TPU 60 > +#define CLK_MOUT_TPU_TPUCTL 61 > +#define CLK_MOUT_TPU_BUS 62 > +#define CLK_MOUT_TPU_UART 63 > +#define CLK_MOUT_TPU_HPM 64 > +#define CLK_MOUT_BO_BUS 65 > +#define CLK_MOUT_G3D_BUSD 66 > + > +/* CMU_TOP Dividers*/ > +#define CLK_DOUT_SHARED0_DIV3 67 > +#define CLK_DOUT_SHARED0_DIV2 68 > +#define CLK_DOUT_SHARED0_DIV4 69 > +#define CLK_DOUT_SHARED0_DIV5 70 > +#define CLK_DOUT_SHARED1_DIV3 71 > +#define CLK_DOUT_SHARED1_DIV2 72 > +#define CLK_DOUT_SHARED1_DIV4 73 > +#define CLK_DOUT_SHARED2_DIV2 74 > +#define CLK_DOUT_SHARED3_DIV2 75 > +#define CLK_DOUT_BUS0_BUS 76 > +#define CLK_DOUT_CMU_BOOST 77 > +#define CLK_DOUT_BUS1_BUS 78 > +#define CLK_DOUT_BUS2_BUS 79 > +#define CLK_DOUT_CORE_BUS 80 > +#define CLK_DOUT_EH_BUS 81 > +#define CLK_DOUT_CPUCL2_SWITCH 82 > +#define CLK_DOUT_CPUCL1_SWITCH 83 > +#define CLK_DOUT_CPUCL0_SWITCH 84 > +#define CLK_DOUT_CPUCL0_DBG 85 > +#define CLK_DOUT_CMU_HPM 86 > +#define CLK_DOUT_G3D_SWITCH 87 > +#define CLK_DOUT_G3D_GLB 88 > +#define CLK_DOUT_DPU_BUS 89 > +#define CLK_DOUT_DISP_BUS 90 > +#define CLK_DOUT_G2D_G2D 91 > +#define CLK_DOUT_G2D_MSCL 92 > +#define CLK_DOUT_HSI0_USB31DRD 93 > +#define CLK_DOUT_HSI0_BUS 94 > +#define CLK_DOUT_HSI0_DPGTC 95 > +#define CLK_DOUT_HSI0_USBDPDGB 96 > +#define CLK_DOUT_HSI1_BUS 97 > +#define CLK_DOUT_HSI1_PCIE 98 > +#define CLK_DOUT_HSI2_BUS 100 > +#define CLK_DOUT_HSI2_PCIE 101 > +#define CLK_DOUT_HSI2_UFS_EMBD 102 > +#define CLK_DOUT_HSI2_MMC_CARD 103 > +#define CLK_DOUT_CSIS 104 > +#define CLK_DOUT_PDP_BUS 105 > +#define CLK_DOUT_PDP_VRA 106 > +#define CLK_DOUT_IPP_BUS 107 > +#define CLK_DOUT_G3AA 108 > +#define CLK_DOUT_ITP 109 > +#define CLK_DOUT_DNS_BUS 110 > +#define CLK_DOUT_TNR_BUS 111 > +#define CLK_DOUT_MCSC_ITSC 112 > +#define CLK_DOUT_MCSC_MCSC 113 > +#define CLK_DOUT_GDC_SCSC 114 > +#define CLK_DOUT_GDC_GDC0 115 > +#define CLK_DOUT_GDC_GDC1 116 > +#define CLK_DOUT_MFC_MFC 117 > +#define CLK_DOUT_MIF_BUS 118 > +#define CLK_DOUT_MISC_BUS 119 > +#define CLK_DOUT_MISC_SSS 120 > +#define CLK_DOUT_PERIC0_BUS 121 > +#define CLK_DOUT_PERIC0_IP 122 > +#define CLK_DOUT_PERIC1_BUS 123 > +#define CLK_DOUT_PERIC1_IP 124 > +#define CLK_DOUT_TPU_TPU 125 > +#define CLK_DOUT_TPU_TPUCTL 126 > +#define CLK_DOUT_TPU_BUS 127 > +#define CLK_DOUT_TPU_UART 128 > +#define CLK_DOUT_TPU_HPM 129 > +#define CLK_DOUT_BO_BUS 130 > + > +/* CMU_TOP Gates*/ > +#define CLK_GOUT_BUS0_BUS 131 > +#define CLK_GOUT_BUS1_BUS 132 > +#define CLK_GOUT_BUS2_BUS 133 > +#define CLK_GOUT_CORE_BUS 134 > +#define CLK_GOUT_EH_BUS 135 > +#define CLK_GOUT_CPUCL2_SWITCH 136 > +#define CLK_GOUT_CPUCL1_SWITCH 137 > +#define CLK_GOUT_CPUCL0_SWITCH 138 > +#define CLK_GOUT_CPUCL0_DBG 139 > +#define CLK_GOUT_CMU_HPM 140 > +#define CLK_GOUT_G3D_SWITCH 141 > +#define CLK_GOUT_G3D_GLB 142 > +#define CLK_GOUT_DPU_BUS 143 > +#define CLK_GOUT_DISP_BUS 144 > +#define CLK_GOUT_G2D_G2D 145 > +#define CLK_GOUT_G2D_MSCL 146 > +#define CLK_GOUT_HSI0_USB31DRD 147 > +#define CLK_GOUT_HSI0_BUS 148 > +#define CLK_GOUT_HSI0_DPGTC 149 > +#define CLK_GOUT_HSI0_USBDPDGB 150 > +#define CLK_GOUT_HSI1_BUS 151 > +#define CLK_GOUT_HSI1_PCIE 152 > +#define CLK_GOUT_HSI2_BUS 153 > +#define CLK_GOUT_HSI2_PCIE 154 > +#define CLK_GOUT_HSI2_UFS_EMBD 155 > +#define CLK_GOUT_HSI2_MMC_CARD 156 > +#define CLK_GOUT_CSIS 157 > +#define CLK_GOUT_PDP_BUS 158 > +#define CLK_GOUT_PDP_VRA 159 > +#define CLK_GOUT_IPP_BUS 160 > +#define CLK_GOUT_G3AA 161 > +#define CLK_GOUT_ITP 162 > +#define CLK_GOUT_DNS_BUS 163 > +#define CLK_GOUT_TNR_BUS 164 > +#define CLK_GOUT_MCSC_ITSC 165 > +#define CLK_GOUT_MCSC_MCSC 166 > +#define CLK_GOUT_GDC_SCSC 167 > +#define CLK_GOUT_GDC_GDC0 168 > +#define CLK_GOUT_GDC_GDC1 169 > +#define CLK_GOUT_MFC_MFC 170 > +#define CLK_GOUT_MIF_SWITCH 171 > +#define CLK_GOUT_MIF_BUS 172 > +#define CLK_GOUT_MISC_BUS 173 > +#define CLK_GOUT_MISC_SSS 174 > +#define CLK_GOUT_PERIC0_BUS 175 > +#define CLK_GOUT_PERIC0_IP 176 > +#define CLK_GOUT_PERIC1_BUS 177 > +#define CLK_GOUT_PERIC1_IP 178 > +#define CLK_GOUT_TPU_TPU 179 > +#define CLK_GOUT_TPU_TPUCTL 180 > +#define CLK_GOUT_TPU_BUS 181 > +#define CLK_GOUT_TPU_UART 182 > +#define CLK_GOUT_TPU_HPM 183 > +#define CLK_GOUT_BO_BUS 184 > +#define CLK_GOUT_CMU_BOOST 185 > + > +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ -- Best Regards, Samsung Electronics Chanwoo Choi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel