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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 25/03/2019 16:16, Anup Patel wrote: > 1G mappings will give better performance compared 2M mappings. > > This will be very useful for performance hungry system with lot of RAM. > > This patch selects 1G or 2M mapping at runtime based on load address > alignment. > > Regards, > Anup > Not always the case. In general, if set-associative or direct mapped TLBs are used, then either 1) separate TLBs are used for different granularities. Usually very few entries will be there for 1G mappings. E.g. Intel CPU's D-TLB has a separate array of 1G page TLB which is only 4 entries. 2) a smaller-granularity PTE is "faked" by page walker and inserted into the TLB. E.g. Intel CPU's I-TLB can't hold 1G entry at all. In either cases the performance won't differ by much. In fact if 1) is used there are cases where performance can be negatively impacted by using larger pages. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv