Hi Ben,

Thanks for your patch! Perhaps something to improve:

[auto build test WARNING on 53989fad1286e652ea3655ae3367ba698da8d2ff]

url:    https://github.com/0day-ci/linux/commits/Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
base:   53989fad1286e652ea3655ae3367ba698da8d2ff
config: x86_64-randconfig-c007-20211118 (https://download.01.org/0day-ci/archive/20211128/202111280254.IoqCZcvv-lkp@intel.com/config)
reproduce (this is a W=1 build):
         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
         chmod +x ~/bin/make.cross
         # https://github.com/0day-ci/linux/commit/cfdf51e15fc8229a494ee59d05bc7459ab5eecd8
         git remote add linux-review https://github.com/0day-ci/linux
         git fetch --no-tags linux-review Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
         git checkout cfdf51e15fc8229a494ee59d05bc7459ab5eecd8
         # save the config file to linux build tree
         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 clang-analyzer

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


clang-analyzer warnings: (new ones prefixed by >>)

 >> drivers/cxl/pci.c:483:3: warning: Value stored to 'size' is never read [clang-analyzer-deadcode.DeadStores]
                    size |= temp & CXL_DVSEC_PCIE_DEVICE_MEM_SIZE_LOW_MASK;
                    ^       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

vim +/size +483 drivers/cxl/pci.c

1d5a4159074bde Ben Widawsky 2021-04-07  454
cfdf51e15fc822 Ben Widawsky 2021-11-19  455  #define CDPD(cxlds, which)                                                     \
cfdf51e15fc822 Ben Widawsky 2021-11-19  456  	cxlds->device_dvsec + CXL_DVSEC_PCIE_DEVICE_##which##_OFFSET
cfdf51e15fc822 Ben Widawsky 2021-11-19  457
cfdf51e15fc822 Ben Widawsky 2021-11-19  458  #define CDPDR(cxlds, which, sorb, lohi)                                        \
cfdf51e15fc822 Ben Widawsky 2021-11-19  459  	cxlds->device_dvsec +                                                  \
cfdf51e15fc822 Ben Widawsky 2021-11-19  460  		CXL_DVSEC_PCIE_DEVICE_RANGE_##sorb##_##lohi##_OFFSET(which)
cfdf51e15fc822 Ben Widawsky 2021-11-19  461
cfdf51e15fc822 Ben Widawsky 2021-11-19  462  static int wait_for_valid(struct cxl_dev_state *cxlds)
cfdf51e15fc822 Ben Widawsky 2021-11-19  463  {
cfdf51e15fc822 Ben Widawsky 2021-11-19  464  	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
cfdf51e15fc822 Ben Widawsky 2021-11-19  465  	const unsigned long timeout = jiffies + HZ;
cfdf51e15fc822 Ben Widawsky 2021-11-19  466  	bool valid;
cfdf51e15fc822 Ben Widawsky 2021-11-19  467
cfdf51e15fc822 Ben Widawsky 2021-11-19  468  	do {
cfdf51e15fc822 Ben Widawsky 2021-11-19  469  		u64 size;
cfdf51e15fc822 Ben Widawsky 2021-11-19  470  		u32 temp;
cfdf51e15fc822 Ben Widawsky 2021-11-19  471  		int rc;
cfdf51e15fc822 Ben Widawsky 2021-11-19  472
cfdf51e15fc822 Ben Widawsky 2021-11-19  473  		rc = pci_read_config_dword(pdev, CDPDR(cxlds, 0, SIZE, HIGH),
cfdf51e15fc822 Ben Widawsky 2021-11-19  474  					   &temp);
cfdf51e15fc822 Ben Widawsky 2021-11-19  475  		if (rc)
cfdf51e15fc822 Ben Widawsky 2021-11-19  476  			return -ENXIO;
cfdf51e15fc822 Ben Widawsky 2021-11-19  477  		size = (u64)temp << 32;
cfdf51e15fc822 Ben Widawsky 2021-11-19  478
cfdf51e15fc822 Ben Widawsky 2021-11-19  479  		rc = pci_read_config_dword(pdev, CDPDR(cxlds, 0, SIZE, LOW),
cfdf51e15fc822 Ben Widawsky 2021-11-19  480  					   &temp);
cfdf51e15fc822 Ben Widawsky 2021-11-19  481  		if (rc)
cfdf51e15fc822 Ben Widawsky 2021-11-19  482  			return -ENXIO;
cfdf51e15fc822 Ben Widawsky 2021-11-19 @483  		size |= temp & CXL_DVSEC_PCIE_DEVICE_MEM_SIZE_LOW_MASK;
cfdf51e15fc822 Ben Widawsky 2021-11-19  484
cfdf51e15fc822 Ben Widawsky 2021-11-19  485  		/*
cfdf51e15fc822 Ben Widawsky 2021-11-19  486  		 * Memory_Info_Valid: When set, indicates that the CXL Range 1
cfdf51e15fc822 Ben Widawsky 2021-11-19  487  		 * Size high and Size Low registers are valid. Must be set
cfdf51e15fc822 Ben Widawsky 2021-11-19  488  		 * within 1 second of deassertion of reset to CXL device.
cfdf51e15fc822 Ben Widawsky 2021-11-19  489  		 */
cfdf51e15fc822 Ben Widawsky 2021-11-19  490  		valid = FIELD_GET(CXL_DVSEC_PCIE_DEVICE_MEM_INFO_VALID, temp);
cfdf51e15fc822 Ben Widawsky 2021-11-19  491  		if (valid)
cfdf51e15fc822 Ben Widawsky 2021-11-19  492  			break;
cfdf51e15fc822 Ben Widawsky 2021-11-19  493  		cpu_relax();
cfdf51e15fc822 Ben Widawsky 2021-11-19  494  	} while (!time_after(jiffies, timeout));
cfdf51e15fc822 Ben Widawsky 2021-11-19  495
cfdf51e15fc822 Ben Widawsky 2021-11-19  496  	return valid ? 0 : -ETIMEDOUT;
cfdf51e15fc822 Ben Widawsky 2021-11-19  497  }
cfdf51e15fc822 Ben Widawsky 2021-11-19  498

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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org