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pr=C Message-ID: Date: Wed, 23 Nov 2022 10:51:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [XEN v3 12/12] xen/Arm: GICv3: Enable GICv3 for AArch32 Content-Language: en-US To: Ayan Kumar Halder , CC: , , , , , , References: <20221111141739.2872-1-ayan.kumar.halder@amd.com> <20221111141739.2872-13-ayan.kumar.halder@amd.com> From: Michal Orzel In-Reply-To: <20221111141739.2872-13-ayan.kumar.halder@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EA:EE_|CH2PR12MB4921:EE_ X-MS-Office365-Filtering-Correlation-Id: 756163dc-0db6-485e-2cac-08dacd384c62 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kq5URaEP1VD5puEP0LBHlyC40py7iyr6ZueXK1nYRDapJ6bKfi0buQUWE4nwTPgBS0NGx0WRmQzgsjRnPyxdESDy9HDSlFYzX1/gPzNFozPiqLCycam/O9MWrDRNdT3+y2iZzctgZIsmkxWciw7Dv7za8XTm2VlFGXpGe7H3e6mg3Tyae7u/qEbWeSUMr+cnWfPOv7Vg6uPjXUMQeSxhOFfzsXsjgwBdU9NAGkPoLzWuAbwZyUmWtYN67QuzmWQYayrF7H4MzLuWLr7UE/Iq5uIbq/vSZpPejdCLpDDQTD8a3iacLSNhjfZHDI2d2v0E6aAThi05lJZVjI5g/jK+6ERinv7oTr9b9TMM+/5UZ3zgYM9w/rhAezo0iBuklfz0wINgB6Tww5/nDfaMycPRTdgOyjGBGmoiEA+kge1lQzAzppPYqzG4cQTk7rlOxFPpOKsVD7XWNKQdeXnWrZ2OF+eIM9lfcRtvDvZ3XRQ7upCGlS7NI8YOWI8OlEkj/2eHk9BxO5ImZDZREGXjyx9OlWaM6JqGx2rW9fhmXSq/JV+9HHhahcnAOrwVXOZg+NZU59qHi7qKEalYszXcv6Tfns6KrtC1CWzGRd9QKyA6SqY+NZfivYCCdXuKh8ukFyxBwkx4OLwLLMiOuYKZ1aYBSyepMJWrQwwxMakYP4m7IfDJyCUetBtMVTs/DRtCG7DI8ftcVn4iigQRBp03XkomsOJRj5V3SOGWzIa0sNy16bySO1hPptk0TqdmDL+FLVX0Iz52IiQX4H9wbbxuEiRWeA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(39860400002)(376002)(396003)(451199015)(46966006)(36840700001)(40470700004)(2906002)(36860700001)(31686004)(2616005)(70586007)(70206006)(53546011)(41300700001)(36756003)(82310400005)(31696002)(86362001)(40480700001)(110136005)(83380400001)(356005)(54906003)(4326008)(426003)(82740400003)(81166007)(47076005)(8936002)(8676002)(6666004)(5660300002)(186003)(44832011)(16576012)(26005)(336012)(316002)(40460700003)(478600001)(36900700001)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2022 09:51:30.8617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 756163dc-0db6-485e-2cac-08dacd384c62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4921 Hi Ayan, On 11/11/2022 15:17, Ayan Kumar Halder wrote: > One can now use GICv3 on AArch32 systems. However, ITS is not supported. > The reason being currently we are trying to validate GICv3 on an AArch32_v8R > system. Refer ARM DDI 0568A.c ID110520, B1.3.1, > "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not > implement LPI support." > > By default GICv3 is disabled on AArch32 and enabled on AArch64. > > Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported. > > Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel with one remark... > --- > > Changed from :- > v1 - 1. Remove "ARM_64 || ARM_32" as it is always true. > 2. Updated SUPPORT.md. > > v2 - 1. GICv3 is enabled by default only on ARM_64. > 2. Updated SUPPORT.md. > > SUPPORT.md | 7 +++++++ > xen/arch/arm/Kconfig | 9 +++++---- > xen/arch/arm/include/asm/cpufeature.h | 1 + > 3 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/SUPPORT.md b/SUPPORT.md > index ab71464cf6..3f16d83191 100644 > --- a/SUPPORT.md > +++ b/SUPPORT.md > @@ -82,6 +82,13 @@ Extension to the GICv3 interrupt controller to support MSI. > > Status: Experimental > > +### ARM/GICv3 ... For me this section should go before the section ARM/GICv3 ITS. The reason being ITS is an extension and your section being generic should be listed before listing extension. ~Michal