From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:27800 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726959AbgFJOvV (ORCPT ); Wed, 10 Jun 2020 10:51:21 -0400 Subject: Re: [kvm-unit-tests PATCH v8 09/12] s390x: Library resources for CSS tests References: <1591603981-16879-1-git-send-email-pmorel@linux.ibm.com> <1591603981-16879-10-git-send-email-pmorel@linux.ibm.com> <17e5ccdd-f2b2-00bd-4ee2-c0a0b78a669a@linux.ibm.com> From: Thomas Huth Message-ID: Date: Wed, 10 Jun 2020 16:51:10 +0200 MIME-Version: 1.0 In-Reply-To: <17e5ccdd-f2b2-00bd-4ee2-c0a0b78a669a@linux.ibm.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-s390-owner@vger.kernel.org List-ID: To: Pierre Morel , kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, cohuck@redhat.com On 09/06/2020 17.01, Pierre Morel wrote: > > > On 2020-06-09 09:09, Thomas Huth wrote: >> On 08/06/2020 10.12, Pierre Morel wrote: >>> Provide some definitions and library routines that can be used by > > ...snip... > >>> +static inline int ssch(unsigned long schid, struct orb *addr) >>> +{ >>> +    register long long reg1 asm("1") = schid; >>> +    int cc; >>> + >>> +    asm volatile( >>> +        "    ssch    0(%2)\n" >>> +        "    ipm    %0\n" >>> +        "    srl    %0,28\n" >>> +        : "=d" (cc) >>> +        : "d" (reg1), "a" (addr), "m" (*addr) >> >> Hmm... What's the "m" (*addr) here good for? %3 is not used in the >> assembly code? > > addr is %2 > "m" (*addr) means memory pointed by addr is read > >> >>> +        : "cc", "memory"); >> >> Why "memory" ? Can this instruction also change the orb? > > The orb not but this instruction modifies memory as follow: > orb -> ccw -> data > > The CCW can be a READ or a WRITE instruction and the data my be anywhere > in memory (<2G) > > A compiler memory barrier is need to avoid write instructions started > before the SSCH instruction to occur after for a write > and memory read made after the instruction to be executed before for a > read. Ok, makes sense now, thanks! >>> +static inline int msch(unsigned long schid, struct schib *addr) >>> +{ >>> +    register unsigned long reg1 asm ("1") = schid; >>> +    int cc; >>> + >>> +    asm volatile( >>> +        "    msch    0(%3)\n" >>> +        "    ipm    %0\n" >>> +        "    srl    %0,28" >>> +        : "=d" (cc), "=m" (*addr) >>> +        : "d" (reg1), "a" (addr) >> >> I'm not an expert with these IO instructions, but this looks wrong to me >> ... Is MSCH reading or writing the SCHIB data? > > MSCH is reading the SCHIB data in memory. So if it is reading, you don't need the "=m" (*addr) in the output list, do you? You should rather use "m" (*addr) in the input list instead? Thomas