From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5EC9C4338F for ; Thu, 29 Jul 2021 20:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB7CC60F4B for ; Thu, 29 Jul 2021 20:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232672AbhG2U24 (ORCPT ); Thu, 29 Jul 2021 16:28:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229707AbhG2U24 (ORCPT ); Thu, 29 Jul 2021 16:28:56 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 593C9C061765 for ; Thu, 29 Jul 2021 13:28:52 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id o7-20020a05600c5107b0290257f956e02dso1211937wms.1 for ; Thu, 29 Jul 2021 13:28:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=yjvy0nNjdoVdeBRrNfPDRD8M9hukWpC6XSosKuNv5ME=; b=uXQbJc9YN7jcauyWcxa/AhQHH/ohDJah+P0h3TjE+ye9WEGAKdpNOiKwp67zax537M F43p5oywXQXzW7asCsVSZPRdoUPuNWn65XyxofHmG7aWxMGp+tJIyLgWAxAsx0xX4+BP 83Mv2s4tjdzEoYFWep02aUKE+e0dh7ik6Pl6EJrAobwEdsQ2e0XYKw7xZ6NrHw42FtBb 4KGArkAiSRGW1h0aCCjkK3PUpAakI9OvAOvzm8rg27FRIaYu+kLYVv7wp7HIrkpm3e6H lMm+UbmOX7hCOrlUJ1tRpU1ILGxcun833XNajyZNblK46IgBhP0Y8bxu0l5k15NUag+l n9Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=yjvy0nNjdoVdeBRrNfPDRD8M9hukWpC6XSosKuNv5ME=; b=DmlhavgWMI4JwvB+wmSu/1IIddJJQIWZ0pCKssVLiq1WlryFBqztfgbyppuJZLy3+a ewy4wqR3f3c/Y9GS/t7absIHbke5CiA1Gn1J6efnoQMDRFVYaSQockQZZXWzuFeSXSLn nw+1fKo5d8cfWZgIy05aFpk7YLZ0f2mOEuTh+gMxEo1ECD//2mQFyz4qwxWTC15DtaN9 PQ911ONlZvx24crqMeuwAOYI/L6ZjsJ0uIg0ntgOQFKe5RC/2MNadIYfEP0ckUpYzvP5 IhNJW995H7zyF9nt/6UW7jyMPzjUOui765mjJMpNTw8RLcDr4VhL8D7NwO8RHfTUeoGN h+dQ== X-Gm-Message-State: AOAM530ecZy5ZlFOzynEufPPo0fGl3bvagADQ35ZniWJLlvDUfBaLG16 CCjFV+lEa87lZvW3k6tDuqkrgQ== X-Google-Smtp-Source: ABdhPJzkzIH6AZrxd5zBBNCDr+3o/XoHDyD63OWg5X4bm6XBxl9fD1BIEF0IQ1s/N/Tdsj+GfXWN5w== X-Received: by 2002:a05:600c:19d3:: with SMTP id u19mr224549wmq.115.1627590530830; Thu, 29 Jul 2021 13:28:50 -0700 (PDT) Received: from [192.168.1.12] (host-80-41-121-59.as13285.net. [80.41.121.59]) by smtp.gmail.com with ESMTPSA id v6sm4474677wru.50.2021.07.29.13.28.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jul 2021 13:28:50 -0700 (PDT) Subject: Re: [PATCH] drm/msm: Disable frequency clamping on a630 To: Rob Clark Cc: dri-devel , freedreno , linux-arm-msm , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Jonathan Marek , Sai Prakash Ranjan , Bjorn Andersson , Sharat Masetty , Akhil P Oommen , open list , Stephen Boyd References: <20210729183942.2839925-1-robdclark@gmail.com> <1a38a590-a64e-58ef-1bbf-0ae49c004d05@linaro.org> From: Caleb Connolly Message-ID: Date: Thu, 29 Jul 2021 21:28:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 29/07/2021 21:24, Rob Clark wrote: > On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly > wrote: >> >> Hi Rob, >> >> I've done some more testing! It looks like before that patch ("drm/msm: Devfreq tuning") the GPU would never get above >> the second frequency in the OPP table (342MHz) (at least, not in glxgears). With the patch applied it would more >> aggressively jump up to the max frequency which seems to be unstable at the default regulator voltages. > > *ohh*, yeah, ok, that would explain it > >> Hacking the pm8005 s1 regulator (which provides VDD_GFX) up to 0.988v (instead of the stock 0.516v) makes the GPU stable >> at the higher frequencies. >> >> Applying this patch reverts the behaviour, and the GPU never goes above 342MHz in glxgears, losing ~30% performance in >> glxgear. >> >> I think (?) that enabling CPR support would be the proper solution to this - that would ensure that the regulators run >> at the voltage the hardware needs to be stable. >> >> Is hacking the voltage higher (although ideally not quite that high) an acceptable short term solution until we have >> CPR? Or would it be safer to just not make use of the higher frequencies on a630 for now? >> > > tbh, I'm not sure about the regulator stuff and CPR.. Bjorn is already > on CC and I added sboyd, maybe one of them knows better. > > In the short term, removing the higher problematic OPPs from dts might > be a better option than this patch (which I'm dropping), since there > is nothing stopping other workloads from hitting higher OPPs. Oh yeah that sounds like a more sensible workaround than mine 😅. > > I'm slightly curious why I didn't have problems at higher OPPs on my > c630 laptop (sdm850) Perhaps you won the sillicon lottery - iirc sdm850 is binned for higher clocks as is out of the factory. Would it be best to drop the OPPs for all devices? Or just those affected? I guess it's possible another c630 might crash where yours doesn't? > > BR, > -R > >> >> On 29/07/2021 19:39, Rob Clark wrote: >>> From: Rob Clark >>> >>> The more frequent frequency transitions resulting from clamping freq to >>> minimum when the GPU is idle seems to be causing some issue with the bus >>> getting voted off when it should be on. (An enable racing with an async >>> disable?) This might be a problem outside of the GPU, as I can't >>> reproduce this on a618 which uses the same GMU fw and same mechanism to >>> communicate with GMU to set opp. For now, just revert to previous >>> devfreq behavior on a630 until the issue is understood. >>> >>> Reported-by: Caleb Connolly >>> Fixes: 9bc95570175a ("drm/msm: Devfreq tuning") >>> Signed-off-by: Rob Clark >>> --- >>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ >>> drivers/gpu/drm/msm/msm_gpu.h | 2 ++ >>> drivers/gpu/drm/msm/msm_gpu_devfreq.c | 12 ++++++++++++ >>> 3 files changed, 17 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>> index 748665232d29..9fd08b413010 100644 >>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>> @@ -945,6 +945,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, >>> pm_runtime_use_autosuspend(dev); >>> pm_runtime_enable(dev); >>> >>> + if (adreno_is_a630(adreno_gpu)) >>> + gpu->devfreq.disable_freq_clamping = true; >>> + >>> return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, >>> adreno_gpu->info->name, &adreno_gpu_config); >>> } >>> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h >>> index 0e4b45bff2e6..7e11b667f939 100644 >>> --- a/drivers/gpu/drm/msm/msm_gpu.h >>> +++ b/drivers/gpu/drm/msm/msm_gpu.h >>> @@ -112,6 +112,8 @@ struct msm_gpu_devfreq { >>> * it is inactive. >>> */ >>> unsigned long idle_freq; >>> + >>> + bool disable_freq_clamping; >>> }; >>> >>> struct msm_gpu { >>> diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c >>> index 0a1ee20296a2..a832af436251 100644 >>> --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c >>> +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c >>> @@ -94,6 +94,12 @@ void msm_devfreq_init(struct msm_gpu *gpu) >>> if (!gpu->funcs->gpu_busy) >>> return; >>> >>> + /* Revert to previous polling interval if we aren't using freq clamping >>> + * to preserve previous behavior >>> + */ >>> + if (gpu->devfreq.disable_freq_clamping) >>> + msm_devfreq_profile.polling_ms = 10; >>> + >>> msm_devfreq_profile.initial_freq = gpu->fast_rate; >>> >>> /* >>> @@ -151,6 +157,9 @@ void msm_devfreq_active(struct msm_gpu *gpu) >>> unsigned int idle_time; >>> unsigned long target_freq = df->idle_freq; >>> >>> + if (gpu->devfreq.disable_freq_clamping) >>> + return; >>> + >>> /* >>> * Hold devfreq lock to synchronize with get_dev_status()/ >>> * target() callbacks >>> @@ -186,6 +195,9 @@ void msm_devfreq_idle(struct msm_gpu *gpu) >>> struct msm_gpu_devfreq *df = &gpu->devfreq; >>> unsigned long idle_freq, target_freq = 0; >>> >>> + if (gpu->devfreq.disable_freq_clamping) >>> + return; >>> + >>> /* >>> * Hold devfreq lock to synchronize with get_dev_status()/ >>> * target() callbacks >>> >> >> -- >> Kind Regards, >> Caleb (they/them) -- Kind Regards, Caleb (they/them) From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC163C432BE for ; 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[80.41.121.59]) by smtp.gmail.com with ESMTPSA id v6sm4474677wru.50.2021.07.29.13.28.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jul 2021 13:28:50 -0700 (PDT) Subject: Re: [PATCH] drm/msm: Disable frequency clamping on a630 To: Rob Clark References: <20210729183942.2839925-1-robdclark@gmail.com> <1a38a590-a64e-58ef-1bbf-0ae49c004d05@linaro.org> From: Caleb Connolly Message-ID: Date: Thu, 29 Jul 2021 21:28:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , freedreno , Sai Prakash Ranjan , Jonathan Marek , David Airlie , linux-arm-msm , Sharat Masetty , Akhil P Oommen , dri-devel , Jordan Crouse , Stephen Boyd , Bjorn Andersson , Sean Paul , open list Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 29/07/2021 21:24, Rob Clark wrote: > On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly > wrote: >> >> Hi Rob, >> >> I've done some more testing! It looks like before that patch ("drm/msm: Devfreq tuning") the GPU would never get above >> the second frequency in the OPP table (342MHz) (at least, not in glxgears). With the patch applied it would more >> aggressively jump up to the max frequency which seems to be unstable at the default regulator voltages. > > *ohh*, yeah, ok, that would explain it > >> Hacking the pm8005 s1 regulator (which provides VDD_GFX) up to 0.988v (instead of the stock 0.516v) makes the GPU stable >> at the higher frequencies. >> >> Applying this patch reverts the behaviour, and the GPU never goes above 342MHz in glxgears, losing ~30% performance in >> glxgear. >> >> I think (?) that enabling CPR support would be the proper solution to this - that would ensure that the regulators run >> at the voltage the hardware needs to be stable. >> >> Is hacking the voltage higher (although ideally not quite that high) an acceptable short term solution until we have >> CPR? Or would it be safer to just not make use of the higher frequencies on a630 for now? >> > > tbh, I'm not sure about the regulator stuff and CPR.. Bjorn is already > on CC and I added sboyd, maybe one of them knows better. > > In the short term, removing the higher problematic OPPs from dts might > be a better option than this patch (which I'm dropping), since there > is nothing stopping other workloads from hitting higher OPPs. Oh yeah that sounds like a more sensible workaround than mine 😅. > > I'm slightly curious why I didn't have problems at higher OPPs on my > c630 laptop (sdm850) Perhaps you won the sillicon lottery - iirc sdm850 is binned for higher clocks as is out of the factory. Would it be best to drop the OPPs for all devices? Or just those affected? I guess it's possible another c630 might crash where yours doesn't? > > BR, > -R > >> >> On 29/07/2021 19:39, Rob Clark wrote: >>> From: Rob Clark >>> >>> The more frequent frequency transitions resulting from clamping freq to >>> minimum when the GPU is idle seems to be causing some issue with the bus >>> getting voted off when it should be on. (An enable racing with an async >>> disable?) This might be a problem outside of the GPU, as I can't >>> reproduce this on a618 which uses the same GMU fw and same mechanism to >>> communicate with GMU to set opp. For now, just revert to previous >>> devfreq behavior on a630 until the issue is understood. >>> >>> Reported-by: Caleb Connolly >>> Fixes: 9bc95570175a ("drm/msm: Devfreq tuning") >>> Signed-off-by: Rob Clark >>> --- >>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ >>> drivers/gpu/drm/msm/msm_gpu.h | 2 ++ >>> drivers/gpu/drm/msm/msm_gpu_devfreq.c | 12 ++++++++++++ >>> 3 files changed, 17 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>> index 748665232d29..9fd08b413010 100644 >>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>> @@ -945,6 +945,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, >>> pm_runtime_use_autosuspend(dev); >>> pm_runtime_enable(dev); >>> >>> + if (adreno_is_a630(adreno_gpu)) >>> + gpu->devfreq.disable_freq_clamping = true; >>> + >>> return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, >>> adreno_gpu->info->name, &adreno_gpu_config); >>> } >>> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h >>> index 0e4b45bff2e6..7e11b667f939 100644 >>> --- a/drivers/gpu/drm/msm/msm_gpu.h >>> +++ b/drivers/gpu/drm/msm/msm_gpu.h >>> @@ -112,6 +112,8 @@ struct msm_gpu_devfreq { >>> * it is inactive. >>> */ >>> unsigned long idle_freq; >>> + >>> + bool disable_freq_clamping; >>> }; >>> >>> struct msm_gpu { >>> diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c >>> index 0a1ee20296a2..a832af436251 100644 >>> --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c >>> +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c >>> @@ -94,6 +94,12 @@ void msm_devfreq_init(struct msm_gpu *gpu) >>> if (!gpu->funcs->gpu_busy) >>> return; >>> >>> + /* Revert to previous polling interval if we aren't using freq clamping >>> + * to preserve previous behavior >>> + */ >>> + if (gpu->devfreq.disable_freq_clamping) >>> + msm_devfreq_profile.polling_ms = 10; >>> + >>> msm_devfreq_profile.initial_freq = gpu->fast_rate; >>> >>> /* >>> @@ -151,6 +157,9 @@ void msm_devfreq_active(struct msm_gpu *gpu) >>> unsigned int idle_time; >>> unsigned long target_freq = df->idle_freq; >>> >>> + if (gpu->devfreq.disable_freq_clamping) >>> + return; >>> + >>> /* >>> * Hold devfreq lock to synchronize with get_dev_status()/ >>> * target() callbacks >>> @@ -186,6 +195,9 @@ void msm_devfreq_idle(struct msm_gpu *gpu) >>> struct msm_gpu_devfreq *df = &gpu->devfreq; >>> unsigned long idle_freq, target_freq = 0; >>> >>> + if (gpu->devfreq.disable_freq_clamping) >>> + return; >>> + >>> /* >>> * Hold devfreq lock to synchronize with get_dev_status()/ >>> * target() callbacks >>> >> >> -- >> Kind Regards, >> Caleb (they/them) -- Kind Regards, Caleb (they/them)