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From: petrcvekcz@gmail.com
To: hauke@hauke-m.de, john@phrozen.org
Cc: Petr Cvek <petrcvekcz@gmail.com>,
	linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org,
	pakahmar@hotmail.com
Subject: [PATCH v1 1/7] MIPS: lantiq: Move macro directly to iomem function
Date: Sat,  8 Jun 2019 22:48:04 +0200	[thread overview]
Message-ID: <e3ef5e9ca51ae3169b42d8da5b2f9c623ba53278.1560024463.git.petrcvekcz@gmail.com> (raw)
In-Reply-To: <cover.1560024463.git.petrcvekcz@gmail.com>

From: Petr Cvek <petrcvekcz@gmail.com>

Using the variable as a temporary holder for the macro of the register
offset value is not necessary. Move it directly to the IOMEM read/write
call.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
---
 arch/mips/lantiq/irq.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 6549499eb202..fb3e1cc2cf6b 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -77,44 +77,42 @@ int ltq_eiu_get_irq(int exin)
 
 void ltq_disable_irq(struct irq_data *d)
 {
-	u32 ier = LTQ_ICU_IM0_IER;
 	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 	int im = offset / INT_NUM_IM_OFFSET;
 
 	offset %= INT_NUM_IM_OFFSET;
-	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
+	ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset),
+		    LTQ_ICU_IM0_IER);
 }
 
 void ltq_mask_and_ack_irq(struct irq_data *d)
 {
-	u32 ier = LTQ_ICU_IM0_IER;
-	u32 isr = LTQ_ICU_IM0_ISR;
 	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 	int im = offset / INT_NUM_IM_OFFSET;
 
 	offset %= INT_NUM_IM_OFFSET;
-	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
-	ltq_icu_w32(im, BIT(offset), isr);
+	ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset),
+		    LTQ_ICU_IM0_IER);
+	ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR);
 }
 
 static void ltq_ack_irq(struct irq_data *d)
 {
-	u32 isr = LTQ_ICU_IM0_ISR;
 	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 	int im = offset / INT_NUM_IM_OFFSET;
 
 	offset %= INT_NUM_IM_OFFSET;
-	ltq_icu_w32(im, BIT(offset), isr);
+	ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR);
 }
 
 void ltq_enable_irq(struct irq_data *d)
 {
-	u32 ier = LTQ_ICU_IM0_IER;
 	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 	int im = offset / INT_NUM_IM_OFFSET;
 
 	offset %= INT_NUM_IM_OFFSET;
-	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
+	ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset),
+		    LTQ_ICU_IM0_IER);
 }
 
 static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
-- 
2.21.0


  reply	other threads:[~2019-06-08 20:48 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-08 20:48 [PATCH v1 0/7] MIPS: lantiq: irq: Various fixes, add SMP support petrcvekcz
2019-06-08 20:48 ` petrcvekcz [this message]
2019-06-08 20:48 ` [PATCH v1 2/7] MIPS: lantiq: Change variables to the same type as the source petrcvekcz
2019-06-08 20:48 ` [PATCH v1 3/7] MIPS: lantiq: Fix attributes of of_device_id structure petrcvekcz
2019-06-08 20:48 ` [PATCH v1 4/7] MIPS: lantiq: Remove unused macros petrcvekcz
2019-06-08 20:48 ` [PATCH v1 5/7] MIPS: lantiq: Fix bitfield masking petrcvekcz
2019-06-08 20:48 ` [PATCH v1 6/7] MIPS: lantiq: Shorten register names, remove unused macros petrcvekcz
2019-06-08 20:48 ` [PATCH v1 7/7] MIPS: lantiq: Add SMP support for lantiq interrupt controller petrcvekcz
2019-06-09  6:42   ` Hauke Mehrtens
2019-06-09 10:12     ` Petr Cvek

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