All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v9 2/7] target/ppc: replace __builtin_ffssl() by the equivalent ctz routines
Date: Tue, 18 Dec 2018 09:07:47 +0100	[thread overview]
Message-ID: <e441c825-ed91-0c36-f319-9e1a473ff2cb@kaod.org> (raw)
In-Reply-To: <20181218022339.GD23604@umbus.fritz.box>

On 12/18/18 3:23 AM, David Gibson wrote:
> On Mon, Dec 17, 2018 at 11:34:40PM +0100, Cédric Le Goater wrote:
>> And remove the intermediate MASK_TO_LSH macro which does not add any value.
>>
>> This fixes a compile breakage on windows.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> 
> It's an improvement over what's there, but it still leaves macros
> whose primary use would be for guest registers, but are typed
> according to host values, which doesn't make much sense.
> 
> I think instead we should redefine your BE64 / BE32 variants in terms
> of the existing extract*() and deposit*() primitives, and get rid of
> the GETFIELD / SETFIELD macros.

I will get rid of the GETFIELD/SETFIELD macros and rewrite the BE64/BE32 
variants but I won't use the extract*() and deposit*(). I prefer to keep
the same pattern, which is similar to shpc_get/set_status(). I will make 
the code clearer with static inlines. 

I don't really like the names also. what about xive_(get/set)_field(32/64) ?  

C.
 
>> ---
>>  target/ppc/cpu.h | 15 +++++++++------
>>  1 file changed, 9 insertions(+), 6 deletions(-)
>>
>> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
>> index 527181c0f09f..f4ef4f214564 100644
>> --- a/target/ppc/cpu.h
>> +++ b/target/ppc/cpu.h
>> @@ -78,18 +78,21 @@
>>                                   PPC_BIT32(bs))
>>  #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
>>  
>> +/*
>> + * OPAL PPC bitmask field manipulation, used in XIVE, PHB3 and PHB4
>> + */
>>  #if HOST_LONG_BITS == 32
>> -# define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
>> +#  define GETFIELD(m, v)        (((v) & (m)) >> ctz32(m))
>> +#  define SETFIELD(m, v, val)                                   \
>> +    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz32(m)) & (m)))
>>  #elif HOST_LONG_BITS == 64
>> -# define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>> +#  define GETFIELD(m, v)        (((v) & (m)) >> ctz64(m))
>> +#  define SETFIELD(m, v, val)                                   \
>> +    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz64(m)) & (m)))
>>  #else
>>  # error Unknown sizeof long
>>  #endif
>>  
>> -#define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>> -#define SETFIELD(m, v, val)                             \
>> -        (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
>> -
>>  /*****************************************************************************/
>>  /* Exception vectors definitions                                             */
>>  enum {
> 

  reply	other threads:[~2018-12-18  8:08 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-17 22:34 [Qemu-devel] [PATCH v9 0/7] ppc: support for the XIVE interrupt controller (POWER9) Cédric Le Goater
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 1/7] target/ppc: fix the PPC_BIT definitions Cédric Le Goater
2018-12-18  2:13   ` David Gibson
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 2/7] target/ppc: replace __builtin_ffssl() by the equivalent ctz routines Cédric Le Goater
2018-12-18  2:23   ` David Gibson
2018-12-18  8:07     ` Cédric Le Goater [this message]
2018-12-18  9:36       ` David Gibson
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 3/7] spapr/xive: fix compilation breakage on windows Cédric Le Goater
2018-12-18  2:26   ` David Gibson
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 4/7] spapr: add an extra OV5 field to the sPAPR IRQ backend Cédric Le Goater
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 5/7] spapr: introduce an 'ic-mode' machine option Cédric Le Goater
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 6/7] spapr: change default CPU type to POWER9 Cédric Le Goater
2018-12-18  4:04   ` David Gibson
2018-12-17 22:34 ` [Qemu-devel] [PATCH v9 7/7] MAINTAINERS: PPC: add a XIVE section Cédric Le Goater
2018-12-18  4:11 ` [Qemu-devel] [PATCH v9 0/7] ppc: support for the XIVE interrupt controller (POWER9) David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e441c825-ed91-0c36-f319-9e1a473ff2cb@kaod.org \
    --to=clg@kaod.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.