* [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled
@ 2022-04-27 9:01 Damien Hedde
2022-04-27 15:39 ` Richard Henderson
2022-04-28 12:39 ` Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Damien Hedde @ 2022-04-27 9:01 UTC (permalink / raw)
To: qemu-devel
Cc: Damien Hedde, Peter Maydell, open list:ARM TCG CPUs, richard.henderson
As of now, cryptographic instructions ISAR fields are never cleared so
we can end up with a cpu with cryptographic instructions but no
floating-point/neon instructions which is not a possible configuration
according to ARM specifications.
In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
+ no support
+ cortex-a57/a72: cryptographic extension is optional,
floating-point/neon is not.
+ cortex-a53: crytographic extension is optional as well as
floationg-point/neon. But cryptographic requires
floating-point/neon support.
Therefore we can safely clear the ISAR fields when neon is disabled.
Note that other arm cpus seem to follow this. For example cortex-a55 is
like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
v2: also clear SHA3 / SM3 / SM4 (Richard)
---
target/arm/cpu.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e3f8215203..e46a766d77 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1587,6 +1587,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_NEON);
t = cpu->isar.id_aa64isar0;
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
cpu->isar.id_aa64isar0 = t;
@@ -1601,6 +1607,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->isar.id_aa64pfr0 = t;
u = cpu->isar.id_isar5;
+ u = FIELD_DP32(u, ID_ISAR5, AES, 0);
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
cpu->isar.id_isar5 = u;
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled
2022-04-27 9:01 [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled Damien Hedde
@ 2022-04-27 15:39 ` Richard Henderson
2022-04-28 12:39 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2022-04-27 15:39 UTC (permalink / raw)
To: Damien Hedde, qemu-devel; +Cc: Peter Maydell, open list:ARM TCG CPUs
On 4/27/22 02:01, Damien Hedde wrote:
> As of now, cryptographic instructions ISAR fields are never cleared so
> we can end up with a cpu with cryptographic instructions but no
> floating-point/neon instructions which is not a possible configuration
> according to ARM specifications.
>
> In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
> + no support
> + cortex-a57/a72: cryptographic extension is optional,
> floating-point/neon is not.
> + cortex-a53: crytographic extension is optional as well as
> floationg-point/neon. But cryptographic requires
> floating-point/neon support.
>
> Therefore we can safely clear the ISAR fields when neon is disabled.
>
> Note that other arm cpus seem to follow this. For example cortex-a55 is
> like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
>
> Signed-off-by: Damien Hedde<damien.hedde@greensocs.com>
> ---
>
> v2: also clear SHA3 / SM3 / SM4 (Richard)
> ---
> target/arm/cpu.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled
2022-04-27 9:01 [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled Damien Hedde
2022-04-27 15:39 ` Richard Henderson
@ 2022-04-28 12:39 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2022-04-28 12:39 UTC (permalink / raw)
To: Damien Hedde; +Cc: open list:ARM TCG CPUs, richard.henderson, qemu-devel
On Wed, 27 Apr 2022 at 10:01, Damien Hedde <damien.hedde@greensocs.com> wrote:
>
> As of now, cryptographic instructions ISAR fields are never cleared so
> we can end up with a cpu with cryptographic instructions but no
> floating-point/neon instructions which is not a possible configuration
> according to ARM specifications.
>
> In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
> + no support
> + cortex-a57/a72: cryptographic extension is optional,
> floating-point/neon is not.
> + cortex-a53: crytographic extension is optional as well as
> floationg-point/neon. But cryptographic requires
> floating-point/neon support.
>
> Therefore we can safely clear the ISAR fields when neon is disabled.
>
> Note that other arm cpus seem to follow this. For example cortex-a55 is
> like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
>
> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
> ---
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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