From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gRpej-0002D3-2b for qemu-devel@nongnu.org; Tue, 27 Nov 2018 21:32:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gRpee-0002h3-R1 for qemu-devel@nongnu.org; Tue, 27 Nov 2018 21:32:48 -0500 Message-ID: From: Benjamin Herrenschmidt Date: Wed, 28 Nov 2018 13:32:21 +1100 In-Reply-To: <20181128001324.GS2251@umbus.fritz.box> References: <20181116105729.23240-1-clg@kaod.org> <20181116105729.23240-10-clg@kaod.org> <20181128001324.GS2251@umbus.fritz.box> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , =?ISO-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote: > Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size? Shouldn't be a problem as long as it fits in an int, no ? Cheers, Ben.