From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752105AbdJDP6w (ORCPT ); Wed, 4 Oct 2017 11:58:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54622 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751225AbdJDP6s (ORCPT ); Wed, 4 Oct 2017 11:58:48 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 195567F408 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jpoimboe@redhat.com From: Josh Poimboeuf To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, Juergen Gross , Andy Lutomirski , Linus Torvalds , Sasha Levin , live-patching@vger.kernel.org, Jiri Slaby , Ingo Molnar , "H. Peter Anvin" , Peter Zijlstra , Mike Galbraith , Chris Wright , Alok Kataria , Rusty Russell , virtualization@lists.linux-foundation.org, Boris Ostrovsky , xen-devel@lists.xenproject.org, Thomas Gleixner , Borislav Petkov Subject: [PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros Date: Wed, 4 Oct 2017 10:58:24 -0500 Message-Id: In-Reply-To: References: X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Wed, 04 Oct 2017 15:58:48 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the hard-coded native patch assembly code strings to macros to facilitate sharing common code between 32-bit and 64-bit. These macros will also be used by a future patch which requires the GCC extended asm syntax of two '%' characters instead of one when specifying a register name. Signed-off-by: Josh Poimboeuf --- arch/x86/include/asm/special_insns.h | 24 ++++++++++++++++++++++++ arch/x86/kernel/paravirt_patch_32.c | 21 +++++++++++---------- arch/x86/kernel/paravirt_patch_64.c | 29 +++++++++++++++-------------- 3 files changed, 50 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index ac402c6fc24b..0549c5f2c1b3 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -6,6 +6,30 @@ #include +#ifdef CONFIG_X86_64 +# define _REG_ARG1 "%rdi" +# define NATIVE_IDENTITY_32 "mov %edi, %eax" +# define NATIVE_USERGS_SYSRET64 "swapgs; sysretq" +#else +# define _REG_ARG1 "%eax" +#endif + +#define _REG_RET "%" _ASM_AX + +#define NATIVE_ZERO "xor " _REG_ARG1 ", " _REG_ARG1 +#define NATIVE_IDENTITY "mov " _REG_ARG1 ", " _REG_RET +#define NATIVE_SAVE_FL "pushf; pop " _REG_RET +#define NATIVE_RESTORE_FL "push " _REG_ARG1 "; popf" +#define NATIVE_IRQ_DISABLE "cli" +#define NATIVE_IRQ_ENABLE "sti" +#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET +#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET +#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3" +#define NATIVE_FLUSH_TLB_SINGLE "invlpg (" _REG_ARG1 ")" +#define NATIVE_SWAPGS "swapgs" +#define NATIVE_IRET "iret" +#define NATIVE_QUEUED_SPIN_UNLOCK "movb $0, (" _REG_ARG1 ")" + /* * Volatile isn't enough to prevent the compiler from reordering the * read/write functions for the control registers and messing everything up. diff --git a/arch/x86/kernel/paravirt_patch_32.c b/arch/x86/kernel/paravirt_patch_32.c index 553acbbb4d32..c9c6106ae714 100644 --- a/arch/x86/kernel/paravirt_patch_32.c +++ b/arch/x86/kernel/paravirt_patch_32.c @@ -1,17 +1,18 @@ #include +#include -DEF_NATIVE(pv_irq_ops, irq_disable, "cli"); -DEF_NATIVE(pv_irq_ops, irq_enable, "sti"); -DEF_NATIVE(pv_irq_ops, restore_fl, "push %eax; popf"); -DEF_NATIVE(pv_irq_ops, save_fl, "pushf; pop %eax"); -DEF_NATIVE(pv_cpu_ops, iret, "iret"); -DEF_NATIVE(pv_mmu_ops, read_cr2, "mov %cr2, %eax"); -DEF_NATIVE(pv_mmu_ops, write_cr3, "mov %eax, %cr3"); -DEF_NATIVE(pv_mmu_ops, read_cr3, "mov %cr3, %eax"); +DEF_NATIVE(pv_irq_ops, save_fl, NATIVE_SAVE_FL); +DEF_NATIVE(pv_irq_ops, restore_fl, NATIVE_RESTORE_FL); +DEF_NATIVE(pv_irq_ops, irq_disable, NATIVE_IRQ_DISABLE); +DEF_NATIVE(pv_irq_ops, irq_enable, NATIVE_IRQ_ENABLE); +DEF_NATIVE(pv_cpu_ops, iret, NATIVE_IRET); +DEF_NATIVE(pv_mmu_ops, read_cr2, NATIVE_READ_CR2); +DEF_NATIVE(pv_mmu_ops, read_cr3, NATIVE_READ_CR3); +DEF_NATIVE(pv_mmu_ops, write_cr3, NATIVE_WRITE_CR3); #if defined(CONFIG_PARAVIRT_SPINLOCKS) -DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%eax)"); -DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %eax, %eax"); +DEF_NATIVE(pv_lock_ops, queued_spin_unlock, NATIVE_QUEUED_SPIN_UNLOCK); +DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, NATIVE_ZERO); #endif unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len) diff --git a/arch/x86/kernel/paravirt_patch_64.c b/arch/x86/kernel/paravirt_patch_64.c index 0a1ba3f80cbf..0aa232edd670 100644 --- a/arch/x86/kernel/paravirt_patch_64.c +++ b/arch/x86/kernel/paravirt_patch_64.c @@ -1,25 +1,26 @@ #include #include +#include #include -DEF_NATIVE(pv_irq_ops, irq_disable, "cli"); -DEF_NATIVE(pv_irq_ops, irq_enable, "sti"); -DEF_NATIVE(pv_irq_ops, restore_fl, "pushq %rdi; popfq"); -DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax"); -DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax"); -DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax"); -DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3"); -DEF_NATIVE(pv_mmu_ops, flush_tlb_single, "invlpg (%rdi)"); +DEF_NATIVE(pv_irq_ops, save_fl, NATIVE_SAVE_FL); +DEF_NATIVE(pv_irq_ops, restore_fl, NATIVE_RESTORE_FL); +DEF_NATIVE(pv_irq_ops, irq_disable, NATIVE_IRQ_DISABLE); +DEF_NATIVE(pv_irq_ops, irq_enable, NATIVE_IRQ_ENABLE); +DEF_NATIVE(pv_mmu_ops, read_cr2, NATIVE_READ_CR2); +DEF_NATIVE(pv_mmu_ops, read_cr3, NATIVE_READ_CR3); +DEF_NATIVE(pv_mmu_ops, write_cr3, NATIVE_WRITE_CR3); +DEF_NATIVE(pv_mmu_ops, flush_tlb_single, NATIVE_FLUSH_TLB_SINGLE); -DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq"); -DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs"); +DEF_NATIVE(pv_cpu_ops, usergs_sysret64, NATIVE_USERGS_SYSRET64); +DEF_NATIVE(pv_cpu_ops, swapgs, NATIVE_SWAPGS); -DEF_NATIVE(, mov32, "mov %edi, %eax"); -DEF_NATIVE(, mov64, "mov %rdi, %rax"); +DEF_NATIVE(, mov32, NATIVE_IDENTITY_32); +DEF_NATIVE(, mov64, NATIVE_IDENTITY); #if defined(CONFIG_PARAVIRT_SPINLOCKS) -DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%rdi)"); -DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %rax, %rax"); +DEF_NATIVE(pv_lock_ops, queued_spin_unlock, NATIVE_QUEUED_SPIN_UNLOCK); +DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, NATIVE_ZERO); #endif unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len) -- 2.13.6 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josh Poimboeuf Subject: [PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros Date: Wed, 4 Oct 2017 10:58:24 -0500 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dzm4R-0008Sh-Kv for xen-devel@lists.xenproject.org; Wed, 04 Oct 2017 15:58:51 +0000 In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: x86@kernel.org Cc: Juergen Gross , Rusty Russell , xen-devel@lists.xenproject.org, Peter Zijlstra , Jiri Slaby , Boris Ostrovsky , Mike Galbraith , linux-kernel@vger.kernel.org, Sasha Levin , Chris Wright , Thomas Gleixner , Andy Lutomirski , "H. Peter Anvin" , Borislav Petkov , live-patching@vger.kernel.org, Alok Kataria , virtualization@lists.linux-foundation.org, Linus Torvalds , Ingo Molnar List-Id: xen-devel@lists.xenproject.org Q29udmVydCB0aGUgaGFyZC1jb2RlZCBuYXRpdmUgcGF0Y2ggYXNzZW1ibHkgY29kZSBzdHJpbmdz IHRvIG1hY3JvcyB0bwpmYWNpbGl0YXRlIHNoYXJpbmcgY29tbW9uIGNvZGUgYmV0d2VlbiAzMi1i aXQgYW5kIDY0LWJpdC4KClRoZXNlIG1hY3JvcyB3aWxsIGFsc28gYmUgdXNlZCBieSBhIGZ1dHVy ZSBwYXRjaCB3aGljaCByZXF1aXJlcyB0aGUgR0NDCmV4dGVuZGVkIGFzbSBzeW50YXggb2YgdHdv ICclJyBjaGFyYWN0ZXJzIGluc3RlYWQgb2Ygb25lIHdoZW4gc3BlY2lmeWluZwphIHJlZ2lzdGVy IG5hbWUuCgpTaWduZWQtb2ZmLWJ5OiBKb3NoIFBvaW1ib2V1ZiA8anBvaW1ib2VAcmVkaGF0LmNv bT4KLS0tCiBhcmNoL3g4Ni9pbmNsdWRlL2FzbS9zcGVjaWFsX2luc25zLmggfCAyNCArKysrKysr KysrKysrKysrKysrKysrKysKIGFyY2gveDg2L2tlcm5lbC9wYXJhdmlydF9wYXRjaF8zMi5jICB8 IDIxICsrKysrKysrKysrLS0tLS0tLS0tLQogYXJjaC94ODYva2VybmVsL3BhcmF2aXJ0X3BhdGNo XzY0LmMgIHwgMjkgKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tLS0KIDMgZmlsZXMgY2hhbmdl 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