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From: Nick Kossifidis <mick@ics.forth.gr>
To: Gary Guo <gary@garyguo.net>
Cc: linux-riscv@lists.infradead.org
Subject: Re: [PATCH] riscv: enable TIME CSR in U mode
Date: Thu, 04 Mar 2021 19:35:00 +0200	[thread overview]
Message-ID: <e50f40a65f10e40c8d601791c0856cc6@mailhost.ics.forth.gr> (raw)
In-Reply-To: <20210216221208.2860-1-gary@garyguo.net>

Στις 2021-02-17 00:12, Gary Guo έγραψε:
> After ad5d112 we let the user mode to use rdtime directly for time
> access. This works if the hardware does not implement the TIME CSR
> and traps to the firmware. The spec however does allow a hardware
> implementation to redirect the CSR access to the memory-mapped MTIME
> CSR, and if this is performed it will check {M,S}COUNTEREN CSR to
> see if it is allowed.
> 
> To prevent unhandled illegal instruction fault on these platforms,
> we can request these CSRs to be enabled in U-mode. For platforms
> that does not support the TIME CSR to MTIME CSR conversion, they
> will hardwire corresponding bit in COUNTEREN to zero and this would
> be a no-op.
> 
> Signed-off-by: Gary Guo <gary@garyguo.net>
> ---
>  arch/riscv/kernel/head.S | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 0a4e81b8dc79..5a7a62190342 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -190,6 +190,9 @@ ENTRY(_start_kernel)
>  .align 2
>  pmp_done:
> 
> +	/* Allow user-mode to access time CSR */
> +	csrw, CSR_MCOUNTEREN, 2
> +
>  	/*
>  	 * The hartid in a0 is expected later on, and we have no firmware
>  	 * to hand it to us.
> @@ -197,6 +200,9 @@ pmp_done:
>  	csrr a0, CSR_MHARTID
>  #endif /* CONFIG_RISCV_M_MODE */
> 
> +	/* Allow user-mode to access time CSR */
> +	csrw CSR_SCOUNTEREN, 2
> +
>  	/* Load the global pointer */
>  .option push
>  .option norelax

Shouldn't we use csrrs here to preserve current settings from the 
firmware ? Also OpenSBI at this point sets both MCOUNTEREN/SCOUNTEREN to 
-1, does anyone else modify that value ?

Regards,
Nick

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  reply	other threads:[~2021-03-04 17:35 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-16 22:12 [PATCH] riscv: enable TIME CSR in U mode Gary Guo
2021-03-04 17:35 ` Nick Kossifidis [this message]
2021-03-16  6:24   ` Gary Guo
2021-03-16 20:52     ` Nick Kossifidis
2021-03-17  2:50       ` Atish Patra

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