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envelope-from=fei2.wu@intel.com; helo=mga17.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/23/2023 11:53 PM, Richard Henderson wrote: > On 3/22/23 19:44, Fei Wu wrote: >> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, >> this assumption won't last as we are about to add more mmu_idx. >> >> Signed-off-by: Fei Wu >> --- >>   target/riscv/cpu.h                             | 1 - >>   target/riscv/cpu_helper.c                      | 2 +- >>   target/riscv/insn_trans/trans_privileged.c.inc | 2 +- >>   target/riscv/insn_trans/trans_xthead.c.inc     | 7 +------ >>   target/riscv/translate.c                       | 3 +++ >>   5 files changed, 6 insertions(+), 9 deletions(-) >> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 638e47c75a..66f7e3d1ba 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -623,7 +623,6 @@ G_NORETURN void >> riscv_raise_exception(CPURISCVState *env, >>   target_ulong riscv_cpu_get_fflags(CPURISCVState *env); >>   void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); >>   -#define TB_FLAGS_PRIV_MMU_MASK                3 >>   #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2) >>   #define TB_FLAGS_MSTATUS_FS MSTATUS_FS >>   #define TB_FLAGS_MSTATUS_VS MSTATUS_VS >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index f88c503cf4..76e1b0100e 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -762,7 +762,7 @@ static int get_physical_address(CPURISCVState >> *env, hwaddr *physical, >>        * (riscv_cpu_do_interrupt) is correct */ >>       MemTxResult res; >>       MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; >> -    int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; >> +    int mode = env->priv; > > This is incorrect.  You must map back from mmu_idx to priv. > Recall the semantics of MPRV. > The following code (~20 lines below) takes MPRV into consideration: if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode = get_field(env->hstatus, HSTATUS_SPVP); } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); } } I think it's the same logic as the original one. >> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc >> b/target/riscv/insn_trans/trans_xthead.c.inc >> index df504c3f2c..adfb53cb4c 100644 >> --- a/target/riscv/insn_trans/trans_xthead.c.inc >> +++ b/target/riscv/insn_trans/trans_xthead.c.inc >> @@ -265,12 +265,7 @@ static bool trans_th_tst(DisasContext *ctx, >> arg_th_tst *a) >>     static inline int priv_level(DisasContext *ctx) >>   { >> -#ifdef CONFIG_USER_ONLY >> -    return PRV_U; >> -#else >> -     /* Priv level is part of mem_idx. */ >> -    return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; >> -#endif >> +    return ctx->priv; >>   } > > I guess we aren't expecting optimization to remove dead system code? > That would be the only reason to keep the ifdef. > > This function should be hoisted to translate.c, or simply replaced by > the field access. > I only want to replace mem_idx to priv here, Zhiwei might decide how to adjust the code further. Thanks, Fei. >> @@ -1162,8 +1163,10 @@ static void >> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) >>       } else { >>           ctx->virt_enabled = false; >>       } >> +    ctx->priv = env->priv; > > Incorrect, as Zhiwei pointed out. > I gave you the changes required to TB_FLAGS... > > > r~