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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id o11-20020ac2434b000000b004cc9ddce3adsm209176lfl.82.2023.01.11.13.08.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 13:08:14 -0800 (PST) Message-ID: Date: Wed, 11 Jan 2023 22:08:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 09/13] clk: qcom: cpu-8996: fix PLL configuration sequence Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20230111192004.2509750-1-dmitry.baryshkov@linaro.org> <20230111192004.2509750-10-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230111192004.2509750-10-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11.01.2023 20:20, Dmitry Baryshkov wrote: > Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux) > before PLL configuration. Switch them to the ACD afterwards. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/clk-cpu-8996.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c > index 571ed52b3026..47c58bb5f21a 100644 > --- a/drivers/clk/qcom/clk-cpu-8996.c > +++ b/drivers/clk/qcom/clk-cpu-8996.c > @@ -432,13 +432,27 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, > { > int i, ret; > > + /* Select GPLL0 for 300MHz for the both clusters */ superfluous 'the' > + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc); > + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc); > + > + /* Ensure write goes through before PLLs are reconfigured */ > + udelay(5); Is this value based on n clock cycles, or 'good enough'? > + > clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); > clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); > clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); > > + /* Wait for PLL(s) to lock */ > + udelay(50); Weird indentation Maybe wait_for_pll_enable_lock() to be super sure? > + > qcom_cpu_clk_msm8996_acd_init(regmap); > > + /* Switch clusters to use the ACD leg */ > + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2); > + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2); > + No delays here? Konrad > for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { > ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); > if (ret)