From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dalon L Westergreen Date: Fri, 08 Feb 2019 12:28:07 -0800 Subject: [U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM In-Reply-To: <20190207212309.27559-1-simon.k.r.goldschmidt@gmail.com> References: <20190207212309.27559-1-simon.k.r.goldschmidt@gmail.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote: > To clean up reset handling for socfpga gen5, let's move the code snippet > taking the DDR controller out of reset from SPL to the DDR driver. > > While at it, port the ddr driver to UCLASS_RAM and use dts. > > Signed-off-by: Simon Goldschmidt > --- > > This is an RFC to show what the SDRAM driver moved to DM (UCLASS_RAM) would > look like. It's RFC both because Dinh did not seem too fond of changing the > register address of the SDR in devicetree to include what the undocumented > registers 'sequencer.c' uses as well as because of my observed code growth. > > Basically, I want to move this to UCLASS_RAM and I want to read the reset > property for SDR from devicetree. What remains RFC is: do we want/need to > read the base address from devicetree, or can we live with it being hard- > coded (and maybe sanity-checked during probe)? > My 2 cents, i love the idea of moving all of the socfgpa sdram code to DM. Looking at the code, i would suggest that we should handle the case where there is no HPS sdram controller, and instead an FPGA based controller is used. Although not common, it is a use case i have seen repeatedly. --dalon > Note that converting sequencer.c from hard-coded address to pointers read > from devicetree and passed around to every function increased code size by > ~700 bytes. Not too much, but enough to stop my socrates board working > (yes, the SPL size check does not work :-( - I'll work on that). > > Also note that this is an integrated patch for SoCrates to show what it > would look like. In the series I prepared, it's better separated and all > boards are adjusted. > > (And yes, checkpatch warnings/errors are fully ignored in this RFC...) > > Any comments? > --- > arch/arm/Kconfig | 2 + > arch/arm/dts/socfpga.dtsi | 5 +- > .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 8 + > .../mach-socfpga/include/mach/sdram_gen5.h | 4 - > arch/arm/mach-socfpga/spl_gen5.c | 37 +- > drivers/ddr/altera/Kconfig | 1 + > drivers/ddr/altera/sdram_gen5.c | 133 ++- > drivers/ddr/altera/sequencer.c | 958 +++++++++--------- > drivers/ddr/altera/sequencer.h | 28 +- > 9 files changed, 653 insertions(+), 523 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index f0edb10003..20ccd70f10 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -815,12 +815,14 @@ config ARCH_SOCFPGA > select DM_SERIAL > select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select OF_CONTROL > + select RAM if TARGET_SOCFPGA_GEN5 > select SPL_DM_RESET if DM_RESET > select SPL_DM_SERIAL > select SPL_LIBCOMMON_SUPPORT > select SPL_LIBGENERIC_SUPPORT > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > select SPL_OF_CONTROL > + select SPL_RAM if TARGET_SOCFPGA_GEN5 > select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 > select SPL_SERIAL_SUPPORT > select SPL_WATCHDOG_SUPPORT > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi > index 2458d6707d..88d02c2b1a 100644 > --- a/arch/arm/dts/socfpga.dtsi > +++ b/arch/arm/dts/socfpga.dtsi > @@ -783,9 +783,10 @@ > reg = <0xfffec000 0x100>; > }; > > - sdr: sdr at ffc25000 { > + sdr: sdr at ffc20000 { > compatible = "altr,sdr-ctl", "syscon"; > - reg = <0xffc25000 0x1000>; > + reg = <0xffc20000 0x6000>; > + resets = <&rst SDR_RESET>; > }; > > sdramedac { > diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi > b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi > index 31bd1dba0f..ffe5a0edfe 100644 > --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi > +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi > @@ -21,6 +21,14 @@ > status = "disabled"; > }; > > +&rst { > + u-boot,dm-pre-reloc; > +}; > + > +&sdr { > + u-boot,dm-pre-reloc; > +}; > + > &mmc { > u-boot,dm-pre-reloc; > }; > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach- > socfpga/include/mach/sdram_gen5.h > index a238d5d17f..c41208591a 100644 > --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h > +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h > @@ -7,10 +7,6 @@ > > #ifndef __ASSEMBLY__ > > -unsigned long sdram_calculate_size(void); > -int sdram_mmr_init_full(unsigned int sdr_phy_reg); > -int sdram_calibration_full(void); > - > const struct socfpga_sdram_config *socfpga_get_sdram_config(void); > > void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); > diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach- > socfpga/spl_gen5.c > index 4c9f7997be..7c266dd46e 100644 > --- a/arch/arm/mach-socfpga/spl_gen5.c > +++ b/arch/arm/mach-socfpga/spl_gen5.c > @@ -20,6 +20,7 @@ > #include > #include > #include > +#include > > DECLARE_GLOBAL_DATA_PTR; > > @@ -66,9 +67,9 @@ u32 spl_boot_mode(const u32 boot_device) > void board_init_f(ulong dummy) > { > const struct cm_config *cm_default_cfg = cm_get_default_config(); > - unsigned long sdram_size; > unsigned long reg; > int ret; > + struct udevice *dev; > > /* > * First C code to run. Clear fake OCRAM ECC first as SBE > @@ -98,7 +99,6 @@ void board_init_f(ulong dummy) > socfpga_bridges_reset(1); > } > > - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); > socfpga_per_reset(SOCFPGA_RESET(UART0), 0); > socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); > > @@ -142,29 +142,24 @@ void board_init_f(ulong dummy) > hang(); > } > > - /* enable console uart printing */ > - preloader_console_init(); > - > - if (sdram_mmr_init_full(0xffffffff) != 0) { > - puts("SDRAM init failed.\n"); > - hang(); > - } > - > - debug("SDRAM: Calibrating PHY\n"); > - /* SDRAM calibration */ > - if (sdram_calibration_full() == 0) { > - puts("SDRAM calibration failed.\n"); > - hang(); > + debug("checking UCLASS_RESET\n"); > + ret = uclass_get_device(UCLASS_RESET, 0, &dev); > + if (ret) { > + debug("Reset init failed: %d\n", ret); > + return; > } > + debug("UCLASS_RESET OK\n"); > > - sdram_size = sdram_calculate_size(); > - debug("SDRAM: %ld MiB\n", sdram_size >> 20); > + /* enable console uart printing */ > + preloader_console_init(); > > - /* Sanity check ensure correct SDRAM size specified */ > - if (get_ram_size(0, sdram_size) != sdram_size) { > - puts("SDRAM size check failed!\n"); > - hang(); > + debug("checking UCLASS_RAM\n"); > + ret = uclass_get_device(UCLASS_RAM, 0, &dev); > + if (ret) { > + debug("DRAM init failed: %d\n", ret); > + return; > } > + debug("UCLASS_RAM OK\n"); > > if (!socfpga_is_booting_from_fpga()) > socfpga_bridges_reset(1); > diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig > index 2b28a97f6e..7370d4133a 100644 > --- a/drivers/ddr/altera/Kconfig > +++ b/drivers/ddr/altera/Kconfig > @@ -1,5 +1,6 @@ > config ALTERA_SDRAM > bool "SoCFPGA DDR SDRAM driver" > + depends on RAM > depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > help > Enable DDR SDRAM controller for the SoCFPGA devices. > diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c > index 821060459c..ff1b130614 100644 > --- a/drivers/ddr/altera/sdram_gen5.c > +++ b/drivers/ddr/altera/sdram_gen5.c > @@ -3,14 +3,21 @@ > * Copyright Altera Corporation (C) 2014-2015 > */ > #include > +#include > #include > #include > +#include > #include > #include > +#include > #include > #include > #include > > +#include "sequencer.h" > + > +#ifdef CONFIG_SPL_BUILD > + > struct sdram_prot_rule { > u32 sdram_start; /* SDRAM start address */ > u32 sdram_end; /* SDRAM end address */ > @@ -26,8 +33,8 @@ struct sdram_prot_rule { > > static struct socfpga_system_manager *sysmgr_regs = > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > -static struct socfpga_sdr_ctrl *sdr_ctrl = > - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; > + > +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); > > /** > * get_errata_rows() - Up the number of DRAM rows to cover entire address > space > @@ -104,7 +111,8 @@ static int get_errata_rows(const struct > socfpga_sdram_config *cfg) > } > > /* SDRAM protection rules vary from 0-19, a total of 20 rules. */ > -static void sdram_set_rule(struct sdram_prot_rule *prule) > +static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl, > + struct sdram_prot_rule *prule) > { > u32 lo_addr_bits; > u32 hi_addr_bits; > @@ -141,7 +149,8 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) > writel(0, &sdr_ctrl->prot_rule_rdwr); > } > > -static void sdram_get_rule(struct sdram_prot_rule *prule) > +static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl, > + struct sdram_prot_rule *prule) > { > u32 addr; > u32 id; > @@ -172,7 +181,8 @@ static void sdram_get_rule(struct sdram_prot_rule *prule) > } > > static void > -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) > +sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl, > + const u32 sdram_start, const u32 sdram_end) > { > struct sdram_prot_rule rule; > int rules; > @@ -185,7 +195,7 @@ sdram_set_protection_config(const u32 sdram_start, const > u32 sdram_end) > > for (rules = 0; rules < 20; rules++) { > rule.rule = rules; > - sdram_set_rule(&rule); > + sdram_set_rule(sdr_ctrl, &rule); > } > > /* new rule: accept SDRAM */ > @@ -200,13 +210,13 @@ sdram_set_protection_config(const u32 sdram_start, const > u32 sdram_end) > rule.rule = 0; > > /* set new rule */ > - sdram_set_rule(&rule); > + sdram_set_rule(sdr_ctrl, &rule); > > /* default rule: reject everything */ > writel(0x3ff, &sdr_ctrl->protport_default); > } > > -static void sdram_dump_protection_config(void) > +static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl) > { > struct sdram_prot_rule rule; > int rules; > @@ -216,7 +226,7 @@ static void sdram_dump_protection_config(void) > > for (rules = 0; rules < 20; rules++) { > rule.rule = rules; > - sdram_get_rule(&rule); > + sdram_get_rule(sdr_ctrl, &rule); > debug("Rule %d, rules ...\n", rules); > debug(" sdram start %x\n", rule.sdram_start); > debug(" sdram end %x\n", rule.sdram_end); > @@ -322,7 +332,8 @@ static u32 sdr_get_addr_rw(const struct > socfpga_sdram_config *cfg) > * > * This function loads the register values into the SDRAM controller block. > */ > -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) > +static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, > + const struct socfpga_sdram_config *cfg) > { > const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); > const u32 dram_addrw = sdr_get_addr_rw(cfg); > @@ -426,7 +437,8 @@ static void sdr_load_regs(const struct > socfpga_sdram_config *cfg) > * > * Initialize the SDRAM MMR. > */ > -int sdram_mmr_init_full(unsigned int sdr_phy_reg) > +int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, > + unsigned int sdr_phy_reg) > { > const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); > const unsigned int rows = > @@ -434,9 +446,12 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) > SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; > int ret; > > + /* release DDR from reset */ > + socfpga_per_reset(SOCFPGA_RESET(SDR), 0); > + > writel(rows, &sysmgr_regs->iswgrp_handoff[4]); > > - sdr_load_regs(cfg); > + sdr_load_regs(sdr_ctrl, cfg); > > /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ > writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); > @@ -459,9 +474,9 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) > SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, > 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); > > - sdram_set_protection_config(0, sdram_calculate_size() - 1); > + sdram_set_protection_config(sdr_ctrl, 0, sdram_calculate_size(sdr_ctrl) > - 1); > > - sdram_dump_protection_config(); > + sdram_dump_protection_config(sdr_ctrl); > > return 0; > } > @@ -472,7 +487,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) > * Calculate SDRAM device size based on SDRAM controller parameters. > * Size is specified in bytes. > */ > -unsigned long sdram_calculate_size(void) > +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) > { > unsigned long temp; > unsigned long row, bank, col, cs, width; > @@ -534,3 +549,91 @@ unsigned long sdram_calculate_size(void) > > return temp; > } > + > +struct altera_gen5_sdram_priv > +{ > + struct ram_info info; > +}; > + > +struct altera_gen5_sdram_platdata > +{ > + struct socfpga_sdr *sdr; > +}; > + > +static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev) > +{ > + struct altera_gen5_sdram_platdata *plat = dev->platdata; > + > + plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0); > + if (!plat->sdr) > + return -ENODEV; > + > + return 0; > +} > + > +static int altera_gen5_sdram_probe(struct udevice *dev) > +{ > + unsigned long sdram_size; > + struct altera_gen5_sdram_platdata *plat = dev->platdata; > + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); > + struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl; > + > + puts("altera_gen5_sdram_probe\n"); > + if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) { > + puts("SDRAM init failed.\n"); > + hang(); > + } > + > + debug("SDRAM: Calibrating PHY\n"); > + /* SDRAM calibration */ > + if (sdram_calibration_full(plat->sdr) == 0) { > + puts("SDRAM calibration failed.\n"); > + hang(); > + } > + > + sdram_size = sdram_calculate_size(sdr_ctrl); > + debug("SDRAM: %ld MiB\n", sdram_size >> 20); > + > + /* Sanity check ensure correct SDRAM size specified */ > + if (get_ram_size(0, sdram_size) != sdram_size) { > + puts("SDRAM size check failed!\n"); > + hang(); > + } > + > + priv->info.base = 0; > + priv->info.size = sdram_size; > + > + return 0; > +} > + > +static int altera_gen5_sdram_get_info(struct udevice *dev, struct ram_info > *info) > +{ > + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); > + > + info->base = priv->info.base; > + info->size = priv->info.size; > + > + return 0; > +} > + > +static struct ram_ops altera_gen5_sdram_ops = { > + .get_info = altera_gen5_sdram_get_info, > +}; > + > +static const struct udevice_id altera_gen5_sdram_ids[] = { > + { .compatible = "altr,sdr-ctl" }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(altera_gen5_sdram) = { > + .name = "altr_sdr_ctl", > + .id = UCLASS_RAM, > + .of_match = altera_gen5_sdram_ids, > + .ops = &altera_gen5_sdram_ops, > + .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata, > + .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata), > + .probe = altera_gen5_sdram_probe, > + .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv), > +}; > + > +#endif /* CONFIG_SPL_BUILD */ > diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c > index 5e7a943b68..02ee2a0bd8 100644 > --- a/drivers/ddr/altera/sequencer.c > +++ b/drivers/ddr/altera/sequencer.c > @@ -9,7 +9,7 @@ > #include > #include "sequencer.h" > > -static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = > +/*static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = > (struct socfpga_sdr_rw_load_manager *) > (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); > static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = > @@ -28,7 +28,7 @@ static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = > static struct socfpga_data_mgr *data_mgr = > (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS; > static struct socfpga_sdr_ctrl *sdr_ctrl = > - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; > + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;*/ > > const struct socfpga_sdram_rw_mgr_config *rwcfg; > const struct socfpga_sdram_io_config *iocfg; > @@ -89,20 +89,20 @@ static void set_failing_group_stage(u32 group, u32 stage, > } > } > > -static void reg_file_set_group(u16 set_group) > +static void reg_file_set_group(struct socfpga_sdr *sdr, u16 set_group) > { > - clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16); > + clrsetbits_le32(&sdr->sdr_reg_file.cur_stage, 0xffff0000, set_group << > 16); > } > > -static void reg_file_set_stage(u8 set_stage) > +static void reg_file_set_stage(struct socfpga_sdr *sdr, u8 set_stage) > { > - clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff); > + clrsetbits_le32(&sdr->sdr_reg_file.cur_stage, 0xffff, set_stage & 0xff); > } > > -static void reg_file_set_sub_stage(u8 set_sub_stage) > +static void reg_file_set_sub_stage(struct socfpga_sdr *sdr, u8 set_sub_stage) > { > set_sub_stage &= 0xff; > - clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8); > + clrsetbits_le32(&sdr->sdr_reg_file.cur_stage, 0xff00, set_sub_stage << > 8); > } > > /** > @@ -110,7 +110,7 @@ static void reg_file_set_sub_stage(u8 set_sub_stage) > * > * Initialize PHY Manager. > */ > -static void phy_mgr_initialize(void) > +static void phy_mgr_initialize(struct socfpga_sdr *sdr) > { > u32 ratio; > > @@ -121,15 +121,15 @@ static void phy_mgr_initialize(void) > * 0: AFI Mux Select > * 1: DDIO Mux Select > */ > - writel(0x3, &phy_mgr_cfg->mux_sel); > + writel(0x3, &sdr->phy_mgr_cfg.mux_sel); > > /* USER memory clock is not stable we begin initialization */ > - writel(0, &phy_mgr_cfg->reset_mem_stbl); > + writel(0, &sdr->phy_mgr_cfg.reset_mem_stbl); > > /* USER calibration status all set to zero */ > - writel(0, &phy_mgr_cfg->cal_status); > + writel(0, &sdr->phy_mgr_cfg.cal_status); > > - writel(0, &phy_mgr_cfg->cal_debug_info); > + writel(0, &sdr->phy_mgr_cfg.cal_debug_info); > > /* Init params only if we do NOT skip calibration. */ > if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) > @@ -150,7 +150,7 @@ static void phy_mgr_initialize(void) > * > * Set Rank and ODT mask (On-Die Termination). > */ > -static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) > +static void set_rank_and_odt_mask(struct socfpga_sdr *sdr, const u32 rank, > const u32 odt_mode) > { > u32 odt_mask_0 = 0; > u32 odt_mask_1 = 0; > @@ -243,7 +243,7 @@ static void set_rank_and_odt_mask(const u32 rank, const > u32 odt_mode) > cs_and_odt_mask = (0xFF & ~(1 << rank)) | > ((0xFF & odt_mask_0) << 8) | > ((0xFF & odt_mask_1) << 16); > - writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(cs_and_odt_mask, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); > } > > @@ -255,9 +255,9 @@ static void set_rank_and_odt_mask(const u32 rank, const > u32 odt_mode) > * > * This function sets the SCC Manager (Scan Chain Control Manager) register. > */ > -static void scc_mgr_set(u32 off, u32 grp, u32 val) > +static void scc_mgr_set(struct socfpga_sdr *sdr, u32 off, u32 grp, u32 val) > { > - writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2)); > + writel(val, (void*)sdr + off + (grp << 2)); > } > > /** > @@ -265,7 +265,7 @@ static void scc_mgr_set(u32 off, u32 grp, u32 val) > * > * Initialize SCC Manager registers. > */ > -static void scc_mgr_initialize(void) > +static void scc_mgr_initialize(struct socfpga_sdr *sdr) > { > /* > * Clear register file for HPS. 16 (2^4) is the size of the > @@ -278,88 +278,88 @@ static void scc_mgr_initialize(void) > for (i = 0; i < 16; i++) { > debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n", > __func__, __LINE__, i); > - scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0); > + scc_mgr_set(sdr, SCC_MGR_HHP_RFILE_OFFSET, i, 0); > } > } > > -static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase) > +static void scc_mgr_set_dqdqs_output_phase(struct socfpga_sdr *sdr, u32 > write_group, u32 phase) > { > - scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase); > + scc_mgr_set(sdr, SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase); > } > > -static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay) > +static void scc_mgr_set_dqs_bus_in_delay(struct socfpga_sdr *sdr, u32 > read_group, u32 delay) > { > - scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay); > + scc_mgr_set(sdr, SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay); > } > > -static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase) > +static void scc_mgr_set_dqs_en_phase(struct socfpga_sdr *sdr, u32 read_group, > u32 phase) > { > - scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase); > + scc_mgr_set(sdr, SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase); > } > > -static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay) > +static void scc_mgr_set_dqs_en_delay(struct socfpga_sdr *sdr, u32 read_group, > u32 delay) > { > - scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay); > + scc_mgr_set(sdr, SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay); > } > > -static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) > +static void scc_mgr_set_dq_in_delay(struct socfpga_sdr *sdr, u32 dq_in_group, > u32 delay) > { > - scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); > + scc_mgr_set(sdr, SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); > } > > -static void scc_mgr_set_dqs_io_in_delay(u32 delay) > +static void scc_mgr_set_dqs_io_in_delay(struct socfpga_sdr *sdr, u32 delay) > { > - scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, > + scc_mgr_set(sdr, SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg- > >mem_dq_per_write_dqs, > delay); > } > > -static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay) > +static void scc_mgr_set_dm_in_delay(struct socfpga_sdr *sdr, u32 dm, u32 > delay) > { > - scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, > + scc_mgr_set(sdr, SCC_MGR_IO_IN_DELAY_OFFSET, > rwcfg->mem_dq_per_write_dqs + 1 + dm, > delay); > } > > -static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay) > +static void scc_mgr_set_dq_out1_delay(struct socfpga_sdr *sdr, u32 > dq_in_group, u32 delay) > { > - scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay); > + scc_mgr_set(sdr, SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay); > } > > -static void scc_mgr_set_dqs_out1_delay(u32 delay) > +static void scc_mgr_set_dqs_out1_delay(struct socfpga_sdr *sdr, u32 delay) > { > - scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, > + scc_mgr_set(sdr, SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg- > >mem_dq_per_write_dqs, > delay); > } > > -static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay) > +static void scc_mgr_set_dm_out1_delay(struct socfpga_sdr *sdr, u32 dm, u32 > delay) > { > - scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, > + scc_mgr_set(sdr, SCC_MGR_IO_OUT1_DELAY_OFFSET, > rwcfg->mem_dq_per_write_dqs + 1 + dm, > delay); > } > > /* load up dqs config settings */ > -static void scc_mgr_load_dqs(u32 dqs) > +static void scc_mgr_load_dqs(struct socfpga_sdr *sdr, u32 dqs) > { > - writel(dqs, &sdr_scc_mgr->dqs_ena); > + writel(dqs, &sdr->sdr_scc_mgr.dqs_ena); > } > > /* load up dqs io config settings */ > -static void scc_mgr_load_dqs_io(void) > +static void scc_mgr_load_dqs_io(struct socfpga_sdr *sdr) > { > - writel(0, &sdr_scc_mgr->dqs_io_ena); > + writel(0, &sdr->sdr_scc_mgr.dqs_io_ena); > } > > /* load up dq config settings */ > -static void scc_mgr_load_dq(u32 dq_in_group) > +static void scc_mgr_load_dq(struct socfpga_sdr *sdr, u32 dq_in_group) > { > - writel(dq_in_group, &sdr_scc_mgr->dq_ena); > + writel(dq_in_group, &sdr->sdr_scc_mgr.dq_ena); > } > > /* load up dm config settings */ > -static void scc_mgr_load_dm(u32 dm) > +static void scc_mgr_load_dm(struct socfpga_sdr *sdr, u32 dm) > { > - writel(dm, &sdr_scc_mgr->dm_ena); > + writel(dm, &sdr->sdr_scc_mgr.dm_ena); > } > > /** > @@ -372,23 +372,23 @@ static void scc_mgr_load_dm(u32 dm) > * This function sets the SCC Manager (Scan Chain Control Manager) register > * and optionally triggers the SCC update for all ranks. > */ > -static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 > val, > +static void scc_mgr_set_all_ranks(struct socfpga_sdr *sdr, const u32 off, > const u32 grp, const u32 val, > const int update) > { > u32 r; > > for (r = 0; r < rwcfg->mem_number_of_ranks; > r += NUM_RANKS_PER_SHADOW_REG) { > - scc_mgr_set(off, grp, val); > + scc_mgr_set(sdr, off, grp, val); > > if (update || (r == 0)) { > - writel(grp, &sdr_scc_mgr->dqs_ena); > - writel(0, &sdr_scc_mgr->update); > + writel(grp, &sdr->sdr_scc_mgr.dqs_ena); > + writel(0, &sdr->sdr_scc_mgr.update); > } > } > } > > -static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) > +static void scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdr *sdr, u32 > read_group, u32 phase) > { > /* > * USER although the h/w doesn't support different phases per > @@ -398,11 +398,11 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(u32 > read_group, u32 phase) > * for efficiency, the scan chain update should occur only > * once to sr0. > */ > - scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET, > + scc_mgr_set_all_ranks(sdr, SCC_MGR_DQS_EN_PHASE_OFFSET, > read_group, phase, 0); > } > > -static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, > +static void scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdr *sdr, > u32 write_group, > u32 phase) > { > /* > @@ -413,11 +413,11 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 > write_group, > * for efficiency, the scan chain update should occur only > * once to sr0. > */ > - scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, > + scc_mgr_set_all_ranks(sdr, SCC_MGR_DQDQS_OUT_PHASE_OFFSET, > write_group, phase, 0); > } > > -static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, > +static void scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdr *sdr, u32 > read_group, > u32 delay) > { > /* > @@ -428,7 +428,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 > read_group, > * select_shadow_regs_for_update with update_scan_chains > * set to 0. > */ > - scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET, > + scc_mgr_set_all_ranks(sdr, SCC_MGR_DQS_EN_DELAY_OFFSET, > read_group, delay, 1); > } > > @@ -439,7 +439,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 > read_group, > * > * This function sets the OCT output delay in SCC manager. > */ > -static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 > delay) > +static void scc_mgr_set_oct_out1_delay(struct socfpga_sdr *sdr, const u32 > write_group, const u32 delay) > { > const int ratio = rwcfg->mem_if_read_dqs_width / > rwcfg->mem_if_write_dqs_width; > @@ -453,7 +453,7 @@ static void scc_mgr_set_oct_out1_delay(const u32 > write_group, const u32 delay) > * the setting must be set multiple times. > */ > for (i = 0; i < ratio; i++) > - scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay); > + scc_mgr_set(sdr, SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, > delay); > } > > /** > @@ -461,7 +461,7 @@ static void scc_mgr_set_oct_out1_delay(const u32 > write_group, const u32 delay) > * > * Load the fixed setting in the SCC manager HHP extras. > */ > -static void scc_mgr_set_hhp_extras(void) > +static void scc_mgr_set_hhp_extras(struct socfpga_sdr *sdr) > { > /* > * Load the fixed setting in the SCC manager > @@ -474,7 +474,7 @@ static void scc_mgr_set_hhp_extras(void) > */ > const u32 value = (0 << 8) | (0 << 7) | (1 << 5) | > (1 << 2) | (1 << 1) | (1 << 0); > - const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | > + const u32 addr = (u32)sdr | > SCC_MGR_HHP_GLOBALS_OFFSET | > SCC_MGR_HHP_EXTRAS_OFFSET; > > @@ -490,7 +490,7 @@ static void scc_mgr_set_hhp_extras(void) > * > * Zero all DQS config. > */ > -static void scc_mgr_zero_all(void) > +static void scc_mgr_zero_all(struct socfpga_sdr *sdr) > { > int i, r; > > @@ -506,21 +506,21 @@ static void scc_mgr_zero_all(void) > * but there's no harm updating them several times, so > * let's keep the code simple. > */ > - scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve); > - scc_mgr_set_dqs_en_phase(i, 0); > - scc_mgr_set_dqs_en_delay(i, 0); > + scc_mgr_set_dqs_bus_in_delay(sdr, i, iocfg- > >dqs_in_reserve); > + scc_mgr_set_dqs_en_phase(sdr, i, 0); > + scc_mgr_set_dqs_en_delay(sdr, i, 0); > } > > for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { > - scc_mgr_set_dqdqs_output_phase(i, 0); > + scc_mgr_set_dqdqs_output_phase(sdr, i, 0); > /* Arria V/Cyclone V don't have out2. */ > - scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve); > + scc_mgr_set_oct_out1_delay(sdr, i, iocfg- > >dqs_out_reserve); > } > } > > /* Multicast to all DQS group enables. */ > - writel(0xff, &sdr_scc_mgr->dqs_ena); > - writel(0, &sdr_scc_mgr->update); > + writel(0xff, &sdr->sdr_scc_mgr.dqs_ena); > + writel(0, &sdr->sdr_scc_mgr.update); > } > > /** > @@ -529,20 +529,20 @@ static void scc_mgr_zero_all(void) > * > * Set bypass mode and trigger SCC update. > */ > -static void scc_set_bypass_mode(const u32 write_group) > +static void scc_set_bypass_mode(struct socfpga_sdr *sdr, const u32 > write_group) > { > /* Multicast to all DQ enables. */ > - writel(0xff, &sdr_scc_mgr->dq_ena); > - writel(0xff, &sdr_scc_mgr->dm_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dq_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dm_ena); > > /* Update current DQS IO enable. */ > - writel(0, &sdr_scc_mgr->dqs_io_ena); > + writel(0, &sdr->sdr_scc_mgr.dqs_io_ena); > > /* Update the DQS logic. */ > - writel(write_group, &sdr_scc_mgr->dqs_ena); > + writel(write_group, &sdr->sdr_scc_mgr.dqs_ena); > > /* Hit update. */ > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > } > > /** > @@ -551,7 +551,7 @@ static void scc_set_bypass_mode(const u32 write_group) > * > * Load DQS settings for Write Group, do not trigger SCC update. > */ > -static void scc_mgr_load_dqs_for_write_group(const u32 write_group) > +static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdr *sdr, const > u32 write_group) > { > const int ratio = rwcfg->mem_if_read_dqs_width / > rwcfg->mem_if_write_dqs_width; > @@ -565,7 +565,7 @@ static void scc_mgr_load_dqs_for_write_group(const u32 > write_group) > * the setting must be set multiple times. > */ > for (i = 0; i < ratio; i++) > - writel(base + i, &sdr_scc_mgr->dqs_ena); > + writel(base + i, &sdr->sdr_scc_mgr.dqs_ena); > } > > /** > @@ -573,7 +573,7 @@ static void scc_mgr_load_dqs_for_write_group(const u32 > write_group) > * > * Zero DQ, DM, DQS and OCT configs for a group. > */ > -static void scc_mgr_zero_group(const u32 write_group, const int out_only) > +static void scc_mgr_zero_group(struct socfpga_sdr *sdr, const u32 > write_group, const int out_only) > { > int i, r; > > @@ -581,38 +581,38 @@ static void scc_mgr_zero_group(const u32 write_group, > const int out_only) > r += NUM_RANKS_PER_SHADOW_REG) { > /* Zero all DQ config settings. */ > for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { > - scc_mgr_set_dq_out1_delay(i, 0); > + scc_mgr_set_dq_out1_delay(sdr, i, 0); > if (!out_only) > - scc_mgr_set_dq_in_delay(i, 0); > + scc_mgr_set_dq_in_delay(sdr, i, 0); > } > > /* Multicast to all DQ enables. */ > - writel(0xff, &sdr_scc_mgr->dq_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dq_ena); > > /* Zero all DM config settings. */ > for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { > if (!out_only) > - scc_mgr_set_dm_in_delay(i, 0); > - scc_mgr_set_dm_out1_delay(i, 0); > + scc_mgr_set_dm_in_delay(sdr, i, 0); > + scc_mgr_set_dm_out1_delay(sdr, i, 0); > } > > /* Multicast to all DM enables. */ > - writel(0xff, &sdr_scc_mgr->dm_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dm_ena); > > /* Zero all DQS IO settings. */ > if (!out_only) > - scc_mgr_set_dqs_io_in_delay(0); > + scc_mgr_set_dqs_io_in_delay(sdr, 0); > > /* Arria V/Cyclone V don't have out2. */ > - scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve); > - scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve); > - scc_mgr_load_dqs_for_write_group(write_group); > + scc_mgr_set_dqs_out1_delay(sdr, iocfg->dqs_out_reserve); > + scc_mgr_set_oct_out1_delay(sdr, write_group, iocfg- > >dqs_out_reserve); > + scc_mgr_load_dqs_for_write_group(sdr, write_group); > > /* Multicast to all DQS IO enables (only 1 in total). */ > - writel(0, &sdr_scc_mgr->dqs_io_ena); > + writel(0, &sdr->sdr_scc_mgr.dqs_io_ena); > > /* Hit update to zero everything. */ > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > } > } > > @@ -620,13 +620,13 @@ static void scc_mgr_zero_group(const u32 write_group, > const int out_only) > * apply and load a particular input delay for the DQ pins in a group > * group_bgn is the index of the first dq pin (in the write group) > */ > -static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay) > +static void scc_mgr_apply_group_dq_in_delay(struct socfpga_sdr *sdr, u32 > group_bgn, u32 delay) > { > u32 i, p; > > for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { > - scc_mgr_set_dq_in_delay(p, delay); > - scc_mgr_load_dq(p); > + scc_mgr_set_dq_in_delay(sdr, p, delay); > + scc_mgr_load_dq(sdr, p); > } > } > > @@ -636,37 +636,37 @@ static void scc_mgr_apply_group_dq_in_delay(u32 > group_bgn, u32 delay) > * > * Apply and load a particular output delay for the DQ pins in a group. > */ > -static void scc_mgr_apply_group_dq_out1_delay(const u32 delay) > +static void scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdr *sdr, const > u32 delay) > { > int i; > > for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { > - scc_mgr_set_dq_out1_delay(i, delay); > - scc_mgr_load_dq(i); > + scc_mgr_set_dq_out1_delay(sdr, i, delay); > + scc_mgr_load_dq(sdr, i); > } > } > > /* apply and load a particular output delay for the DM pins in a group */ > -static void scc_mgr_apply_group_dm_out1_delay(u32 delay1) > +static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdr *sdr, u32 > delay1) > { > u32 i; > > for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { > - scc_mgr_set_dm_out1_delay(i, delay1); > - scc_mgr_load_dm(i); > + scc_mgr_set_dm_out1_delay(sdr, i, delay1); > + scc_mgr_load_dm(sdr, i); > } > } > > > /* apply and load delay on both DQS and OCT out1 */ > -static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group, > +static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdr *sdr, > u32 write_group, > u32 delay) > { > - scc_mgr_set_dqs_out1_delay(delay); > - scc_mgr_load_dqs_io(); > + scc_mgr_set_dqs_out1_delay(sdr, delay); > + scc_mgr_load_dqs_io(sdr); > > - scc_mgr_set_oct_out1_delay(write_group, delay); > - scc_mgr_load_dqs_for_write_group(write_group); > + scc_mgr_set_oct_out1_delay(sdr, write_group, delay); > + scc_mgr_load_dqs_for_write_group(sdr, write_group); > } > > /** > @@ -676,18 +676,18 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 > write_group, > * > * Apply a delay to the entire output side: DQ, DM, DQS, OCT. > */ > -static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, > +static void scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdr *sdr, > const u32 write_group, > const u32 delay) > { > u32 i, new_delay; > > /* DQ shift */ > for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) > - scc_mgr_load_dq(i); > + scc_mgr_load_dq(sdr, i); > > /* DM shift */ > for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) > - scc_mgr_load_dm(i); > + scc_mgr_load_dm(sdr, i); > > /* DQS shift */ > new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay; > @@ -698,10 +698,10 @@ static void scc_mgr_apply_group_all_out_delay_add(const > u32 write_group, > iocfg->io_out2_delay_max, > new_delay - iocfg->io_out2_delay_max); > new_delay -= iocfg->io_out2_delay_max; > - scc_mgr_set_dqs_out1_delay(new_delay); > + scc_mgr_set_dqs_out1_delay(sdr, new_delay); > } > > - scc_mgr_load_dqs_io(); > + scc_mgr_load_dqs_io(sdr); > > /* OCT shift */ > new_delay = READ_SCC_OCT_OUT2_DELAY + delay; > @@ -712,10 +712,10 @@ static void scc_mgr_apply_group_all_out_delay_add(const > u32 write_group, > new_delay, iocfg->io_out2_delay_max, > new_delay - iocfg->io_out2_delay_max); > new_delay -= iocfg->io_out2_delay_max; > - scc_mgr_set_oct_out1_delay(write_group, new_delay); > + scc_mgr_set_oct_out1_delay(sdr, write_group, new_delay); > } > > - scc_mgr_load_dqs_for_write_group(write_group); > + scc_mgr_load_dqs_for_write_group(sdr, write_group); > } > > /** > @@ -726,15 +726,15 @@ static void scc_mgr_apply_group_all_out_delay_add(const > u32 write_group, > * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks. > */ > static void > -scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, > +scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdr *sdr, > const u32 write_group, > const u32 delay) > { > int r; > > for (r = 0; r < rwcfg->mem_number_of_ranks; > r += NUM_RANKS_PER_SHADOW_REG) { > - scc_mgr_apply_group_all_out_delay_add(write_group, delay); > - writel(0, &sdr_scc_mgr->update); > + scc_mgr_apply_group_all_out_delay_add(sdr, write_group, delay); > + writel(0, &sdr->sdr_scc_mgr.update); > } > } > > @@ -744,15 +744,15 @@ scc_mgr_apply_group_all_out_delay_add_all_ranks(const > u32 write_group, > * Optimization used to recover some slots in ddr3 inst_rom could be > * applied to other protocols if we wanted to > */ > -static void set_jump_as_return(void) > +static void set_jump_as_return(struct socfpga_sdr *sdr) > { > /* > * To save space, we replace return with jump to special shared > * RETURN instruction so we set the counter to large value so that > * we always jump. > */ > - writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0); > - writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + writel(0xff, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > + writel(rwcfg->rreturn, &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > } > > /** > @@ -761,7 +761,7 @@ static void set_jump_as_return(void) > * > * Delay for N memory clocks. > */ > -static void delay_for_n_mem_clocks(const u32 clocks) > +static void delay_for_n_mem_clocks(struct socfpga_sdr *sdr, const u32 clocks) > { > u32 afi_clocks; > u16 c_loop; > @@ -805,29 +805,29 @@ static void delay_for_n_mem_clocks(const u32 clocks) > */ > if (afi_clocks < 0x100) { > writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), > - &sdr_rw_load_mgr_regs->load_cntr1); > + &sdr->sdr_rw_load_mgr_regs.load_cntr1); > > writel(rwcfg->idle_loop1, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > > - writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(rwcfg->idle_loop1, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET); > } else { > writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), > - &sdr_rw_load_mgr_regs->load_cntr0); > + &sdr->sdr_rw_load_mgr_regs.load_cntr0); > > writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), > - &sdr_rw_load_mgr_regs->load_cntr1); > + &sdr->sdr_rw_load_mgr_regs.load_cntr1); > > writel(rwcfg->idle_loop2, > - &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > > writel(rwcfg->idle_loop2, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > > do { > writel(rwcfg->idle_loop2, > - SDR_PHYGRP_RWMGRGRP_ADDRESS | > + ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET); > } while (c_loop-- != 0); > } > @@ -843,23 +843,23 @@ static void delay_for_n_mem_clocks(const u32 clocks) > * > * Load instruction registers. > */ > -static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 > jump) > +static void rw_mgr_mem_init_load_regs(struct socfpga_sdr *sdr, u32 cntr0, u32 > cntr1, u32 cntr2, u32 jump) > { > - u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | > + u32 grpaddr = ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET; > > /* Load counters */ > writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0), > - &sdr_rw_load_mgr_regs->load_cntr0); > + &sdr->sdr_rw_load_mgr_regs.load_cntr0); > writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1), > - &sdr_rw_load_mgr_regs->load_cntr1); > + &sdr->sdr_rw_load_mgr_regs.load_cntr1); > writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2), > - &sdr_rw_load_mgr_regs->load_cntr2); > + &sdr->sdr_rw_load_mgr_regs.load_cntr2); > > /* Load jump address */ > - writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0); > - writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1); > - writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + writel(jump, &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > + writel(jump, &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > + writel(jump, &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > > /* Execute count instruction */ > writel(jump, grpaddr); > @@ -873,16 +873,16 @@ static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 > cntr1, u32 cntr2, u32 jump) > * > * Load user calibration values and optionally precharge the banks. > */ > -static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, > +static void rw_mgr_mem_load_user(struct socfpga_sdr *sdr, const u32 fin1, > const u32 fin2, > const int precharge) > { > - u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | > + u32 grpaddr = ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET; > u32 r; > > for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { > /* set rank */ > - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); > + set_rank_and_odt_mask(sdr, r, RW_MGR_ODT_MODE_OFF); > > /* precharge all banks ... */ > if (precharge) > @@ -893,38 +893,38 @@ static void rw_mgr_mem_load_user(const u32 fin1, const > u32 fin2, > * mirrorring is on > */ > if ((rwcfg->mem_address_mirroring >> r) & 0x1) { > - set_jump_as_return(); > + set_jump_as_return(sdr); > writel(rwcfg->mrs2_mirr, grpaddr); > - delay_for_n_mem_clocks(4); > - set_jump_as_return(); > + delay_for_n_mem_clocks(sdr, 4); > + set_jump_as_return(sdr); > writel(rwcfg->mrs3_mirr, grpaddr); > - delay_for_n_mem_clocks(4); > - set_jump_as_return(); > + delay_for_n_mem_clocks(sdr, 4); > + set_jump_as_return(sdr); > writel(rwcfg->mrs1_mirr, grpaddr); > - delay_for_n_mem_clocks(4); > - set_jump_as_return(); > + delay_for_n_mem_clocks(sdr, 4); > + set_jump_as_return(sdr); > writel(fin1, grpaddr); > } else { > - set_jump_as_return(); > + set_jump_as_return(sdr); > writel(rwcfg->mrs2, grpaddr); > - delay_for_n_mem_clocks(4); > - set_jump_as_return(); > + delay_for_n_mem_clocks(sdr, 4); > + set_jump_as_return(sdr); > writel(rwcfg->mrs3, grpaddr); > - delay_for_n_mem_clocks(4); > - set_jump_as_return(); > + delay_for_n_mem_clocks(sdr, 4); > + set_jump_as_return(sdr); > writel(rwcfg->mrs1, grpaddr); > - set_jump_as_return(); > + set_jump_as_return(sdr); > writel(fin2, grpaddr); > } > > if (precharge) > continue; > > - set_jump_as_return(); > + set_jump_as_return(sdr); > writel(rwcfg->zqcl, grpaddr); > > /* tZQinit = tDLLK = 512 ck cycles */ > - delay_for_n_mem_clocks(512); > + delay_for_n_mem_clocks(sdr, 512); > } > } > > @@ -933,12 +933,12 @@ static void rw_mgr_mem_load_user(const u32 fin1, const > u32 fin2, > * > * Initialize RW Manager. > */ > -static void rw_mgr_mem_initialize(void) > +static void rw_mgr_mem_initialize(struct socfpga_sdr *sdr) > { > debug("%s:%d\n", __func__, __LINE__); > > /* The reset / cke part of initialization is broadcasted to all ranks */ > - writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(RW_MGR_RANK_ALL, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); > > /* > @@ -964,13 +964,13 @@ static void rw_mgr_mem_initialize(void) > * One possible solution is n = 0 , a = 256 , b = 106 => a = FF, > * b = 6A > */ > - rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, > + rw_mgr_mem_init_load_regs(sdr, misccfg->tinit_cntr0_val, > misccfg->tinit_cntr1_val, > misccfg->tinit_cntr2_val, > rwcfg->init_reset_0_cke_0); > > /* Indicate that memory is stable. */ > - writel(1, &phy_mgr_cfg->reset_mem_stbl); > + writel(1, &sdr->phy_mgr_cfg.reset_mem_stbl); > > /* > * transition the RESET to high > @@ -986,7 +986,7 @@ static void rw_mgr_mem_initialize(void) > * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, > * b = FF > */ > - rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, > + rw_mgr_mem_init_load_regs(sdr, misccfg->treset_cntr0_val, > misccfg->treset_cntr1_val, > misccfg->treset_cntr2_val, > rwcfg->init_reset_1_cke_0); > @@ -994,9 +994,9 @@ static void rw_mgr_mem_initialize(void) > /* Bring up clock enable. */ > > /* tXRP < 250 ck cycles */ > - delay_for_n_mem_clocks(250); > + delay_for_n_mem_clocks(sdr, 250); > > - rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset, > + rw_mgr_mem_load_user(sdr, rwcfg->mrs0_dll_reset_mirr, rwcfg- > >mrs0_dll_reset, > 0); > } > > @@ -1006,9 +1006,9 @@ static void rw_mgr_mem_initialize(void) > * At the end of calibration we have to program the user settings in > * and hand off the memory to the user. > */ > -static void rw_mgr_mem_handoff(void) > +static void rw_mgr_mem_handoff(struct socfpga_sdr *sdr) > { > - rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); > + rw_mgr_mem_load_user(sdr, rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); > /* > * Need to wait tMOD (12CK or 15ns) time before issuing other > * commands, but we will have plenty of NIOS cycles before actual > @@ -1024,7 +1024,7 @@ static void rw_mgr_mem_handoff(void) > * Issue write test command. Two variants are provided, one that just tests > * a write pattern and another that tests datamask functionality. > */ > -static void rw_mgr_mem_calibrate_write_test_issue(u32 group, > +static void rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdr *sdr, > u32 group, > u32 test_dm) > { > const u32 quick_write_mode = > @@ -1068,21 +1068,21 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 > group, > * instruction that sends out the data. We set the counter to a > * large number so that the jump is always taken. > */ > - writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2); > + writel(0xFF, &sdr->sdr_rw_load_mgr_regs.load_cntr2); > > /* CNTR 3 - Not used */ > if (test_dm) { > mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; > writel(rwcfg->lfsr_wr_rd_dm_bank_0_data, > - &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, > - &sdr_rw_load_jump_mgr_regs->load_jump_add3); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add3); > } else { > mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; > writel(rwcfg->lfsr_wr_rd_bank_0_data, > - &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > writel(rwcfg->lfsr_wr_rd_bank_0_nop, > - &sdr_rw_load_jump_mgr_regs->load_jump_add3); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add3); > } > } else if (rw_wl_nop_cycles == 0) { > /* > @@ -1090,17 +1090,17 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 > group, > * to the DQS enable instruction. We set the counter to a large > * number so that the jump is always taken. > */ > - writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2); > + writel(0xFF, &sdr->sdr_rw_load_mgr_regs.load_cntr2); > > /* CNTR 3 - Not used */ > if (test_dm) { > mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; > writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs, > - &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > } else { > mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; > writel(rwcfg->lfsr_wr_rd_bank_0_dqs, > - &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > } > } else { > /* > @@ -1108,50 +1108,50 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 > group, > * and NOT take the jump. So we set the counter to 0. The jump > * address doesn't count. > */ > - writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2); > - writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + writel(0x0, &sdr->sdr_rw_load_mgr_regs.load_cntr2); > + writel(0x0, &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > > /* > * CNTR 3 - Set the nop counter to the number of cycles we > * need to loop for, minus 1. > */ > - writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3); > + writel(rw_wl_nop_cycles - 1, &sdr- > >sdr_rw_load_mgr_regs.load_cntr3); > if (test_dm) { > mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; > writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, > - &sdr_rw_load_jump_mgr_regs->load_jump_add3); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add3); > } else { > mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; > writel(rwcfg->lfsr_wr_rd_bank_0_nop, > - &sdr_rw_load_jump_mgr_regs->load_jump_add3); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add3); > } > } > > - writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(0, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RESET_READ_DATAPATH_OFFSET); > > if (quick_write_mode) > - writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x08, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > else > - writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x40, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > > - writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + writel(mcc_instruction, &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > > /* > * CNTR 1 - This is used to ensure enough time elapses > * for read data to come back. > */ > - writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1); > + writel(0x30, &sdr->sdr_rw_load_mgr_regs.load_cntr1); > > if (test_dm) { > writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > } else { > writel(rwcfg->lfsr_wr_rd_bank_0_wait, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > } > > - writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(mcc_instruction, (((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET) + > (group << 2)); > } > @@ -1168,7 +1168,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 > group, > * Test writes, can check for a single bit pass or multiple bit pass. > */ > static int > -rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, > +rw_mgr_mem_calibrate_write_test(struct socfpga_sdr *sdr, const u32 rank_bgn, > const u32 write_group, > const u32 use_dm, const u32 all_correct, > u32 *bit_chk, const u32 all_ranks) > { > @@ -1186,20 +1186,20 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, > const u32 write_group, > > for (r = rank_bgn; r < rank_end; r++) { > /* Set rank */ > - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); > + set_rank_and_odt_mask(sdr, r, RW_MGR_ODT_MODE_READ_WRITE); > > tmp_bit_chk = 0; > for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1; > vg >= 0; vg--) { > /* Reset the FIFOs to get pointers to known state. */ > - writel(0, &phy_mgr_cmd->fifo_reset); > + writel(0, &sdr->phy_mgr_cmd.fifo_reset); > > - rw_mgr_mem_calibrate_write_test_issue( > + rw_mgr_mem_calibrate_write_test_issue(sdr, > write_group * > rwcfg->mem_virtual_groups_per_write_dqs + vg, > use_dm); > > - base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); > + base_rw_mgr = readl((u32)(&sdr->rwmgr_grp)); > tmp_bit_chk <<= shift_ratio; > tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr)); > } > @@ -1207,7 +1207,7 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, > const u32 write_group, > *bit_chk &= tmp_bit_chk; > } > > - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); > + set_rank_and_odt_mask(sdr, 0, RW_MGR_ODT_MODE_OFF); > if (all_correct) { > debug_cond(DLEVEL >= 2, > "write_test(%u,%u,ALL) : %u == %u => %i\n", > @@ -1233,10 +1233,10 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, > const u32 write_group, > * read test to ensure memory works. > */ > static int > -rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, > +rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdr *sdr, const u32 > rank_bgn, const u32 group, > const u32 all_ranks) > { > - const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | > + const u32 addr = ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET; > const u32 addr_offset = > (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2; > @@ -1255,28 +1255,28 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 > rank_bgn, const u32 group, > > for (r = rank_bgn; r < rank_end; r++) { > /* Set rank */ > - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); > + set_rank_and_odt_mask(sdr, r, RW_MGR_ODT_MODE_READ_WRITE); > > /* Load up a constant bursts of read commands */ > - writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x20, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > writel(rwcfg->guaranteed_read, > - &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > > - writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); > + writel(0x20, &sdr->sdr_rw_load_mgr_regs.load_cntr1); > writel(rwcfg->guaranteed_read_cont, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > > tmp_bit_chk = 0; > for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; > vg >= 0; vg--) { > /* Reset the FIFOs to get pointers to known state. */ > - writel(0, &phy_mgr_cmd->fifo_reset); > - writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(0, &sdr->phy_mgr_cmd.fifo_reset); > + writel(0, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RESET_READ_DATAPATH_OFFSET); > writel(rwcfg->guaranteed_read, > addr + addr_offset + (vg << 2)); > > - base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); > + base_rw_mgr = readl((u32)(&sdr->rwmgr_grp)); > tmp_bit_chk <<= shift_ratio; > tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr; > } > @@ -1286,7 +1286,7 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 > rank_bgn, const u32 group, > > writel(rwcfg->clear_dqs_enable, addr + (group << 2)); > > - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); > + set_rank_and_odt_mask(sdr, 0, RW_MGR_ODT_MODE_OFF); > > if (bit_chk != param->read_correct_mask) > ret = -EIO; > @@ -1306,7 +1306,7 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 > rank_bgn, const u32 group, > * > * Load up the patterns we are going to use during a read test. > */ > -static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, > +static void rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdr *sdr, > const u32 rank_bgn, > const int all_ranks) > { > const u32 rank_end = all_ranks ? > @@ -1318,34 +1318,34 @@ static void > rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, > > for (r = rank_bgn; r < rank_end; r++) { > /* set rank */ > - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); > + set_rank_and_odt_mask(sdr, r, RW_MGR_ODT_MODE_READ_WRITE); > > /* Load up a constant bursts */ > - writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x20, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > > writel(rwcfg->guaranteed_write_wait0, > - &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > > - writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); > + writel(0x20, &sdr->sdr_rw_load_mgr_regs.load_cntr1); > > writel(rwcfg->guaranteed_write_wait1, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > > - writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2); > + writel(0x04, &sdr->sdr_rw_load_mgr_regs.load_cntr2); > > writel(rwcfg->guaranteed_write_wait2, > - &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > > - writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3); > + writel(0x04, &sdr->sdr_rw_load_mgr_regs.load_cntr3); > > writel(rwcfg->guaranteed_write_wait3, > - &sdr_rw_load_jump_mgr_regs->load_jump_add3); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add3); > > - writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(rwcfg->guaranteed_write, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET); > } > > - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); > + set_rank_and_odt_mask(sdr, 0, RW_MGR_ODT_MODE_OFF); > } > > /** > @@ -1363,7 +1363,7 @@ static void > rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, > * checks than the regular read test. > */ > static int > -rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, > +rw_mgr_mem_calibrate_read_test(struct socfpga_sdr *sdr, const u32 rank_bgn, > const u32 group, > const u32 num_tries, const u32 all_correct, > u32 *bit_chk, > const u32 all_groups, const u32 all_ranks) > @@ -1384,50 +1384,50 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, > const u32 group, > > for (r = rank_bgn; r < rank_end; r++) { > /* set rank */ > - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); > + set_rank_and_odt_mask(sdr, r, RW_MGR_ODT_MODE_READ_WRITE); > > - writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1); > + writel(0x10, &sdr->sdr_rw_load_mgr_regs.load_cntr1); > > writel(rwcfg->read_b2b_wait1, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > > - writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2); > + writel(0x10, &sdr->sdr_rw_load_mgr_regs.load_cntr2); > writel(rwcfg->read_b2b_wait2, > - &sdr_rw_load_jump_mgr_regs->load_jump_add2); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add2); > > if (quick_read_mode) > - writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x1, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > /* need at least two (1+1) reads to capture failures */ > else if (all_groups) > - writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x06, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > else > - writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x32, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > > writel(rwcfg->read_b2b, > - &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > if (all_groups) > writel(rwcfg->mem_if_read_dqs_width * > rwcfg->mem_virtual_groups_per_read_dqs - 1, > - &sdr_rw_load_mgr_regs->load_cntr3); > + &sdr->sdr_rw_load_mgr_regs.load_cntr3); > else > - writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3); > + writel(0x0, &sdr->sdr_rw_load_mgr_regs.load_cntr3); > > writel(rwcfg->read_b2b, > - &sdr_rw_load_jump_mgr_regs->load_jump_add3); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add3); > > tmp_bit_chk = 0; > for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; > vg--) { > /* Reset the FIFOs to get pointers to known state. */ > - writel(0, &phy_mgr_cmd->fifo_reset); > - writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(0, &sdr->phy_mgr_cmd.fifo_reset); > + writel(0, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RESET_READ_DATAPATH_OFFSET); > > if (all_groups) { > - addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | > + addr = ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_ALL_GROUPS_OFFSET; > } else { > - addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | > + addr = ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET; > } > > @@ -1436,7 +1436,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const > u32 group, > rwcfg->mem_virtual_groups_per_read_dqs + > vg) << 2)); > > - base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); > + base_rw_mgr = readl(&sdr->rwmgr_grp); > tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / > rwcfg->mem_virtual_groups_per_read_dqs; > tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr); > @@ -1445,10 +1445,10 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, > const u32 group, > *bit_chk &= tmp_bit_chk; > } > > - addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; > + addr = ((u32)(&sdr->rwmgr_grp)) | RW_MGR_RUN_SINGLE_GROUP_OFFSET; > writel(rwcfg->clear_dqs_enable, addr + (group << 2)); > > - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); > + set_rank_and_odt_mask(sdr, 0, RW_MGR_ODT_MODE_OFF); > > if (all_correct) { > ret = (*bit_chk == param->read_correct_mask); > @@ -1477,12 +1477,12 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, > const u32 group, > * Perform a READ test across all memory ranks. > */ > static int > -rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries, > +rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdr *sdr, const u32 > grp, const u32 num_tries, > const u32 all_correct, > const u32 all_groups) > { > u32 bit_chk; > - return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct, > + return rw_mgr_mem_calibrate_read_test(sdr, 0, grp, num_tries, > all_correct, > &bit_chk, all_groups, 1); > } > > @@ -1492,9 +1492,9 @@ rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, > const u32 num_tries, > * > * Increase VFIFO value. > */ > -static void rw_mgr_incr_vfifo(const u32 grp) > +static void rw_mgr_incr_vfifo(struct socfpga_sdr *sdr, const u32 grp) > { > - writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy); > + writel(grp, &sdr->phy_mgr_cmd.inc_vfifo_hard_phy); > } > > /** > @@ -1503,12 +1503,12 @@ static void rw_mgr_incr_vfifo(const u32 grp) > * > * Decrease VFIFO value. > */ > -static void rw_mgr_decr_vfifo(const u32 grp) > +static void rw_mgr_decr_vfifo(struct socfpga_sdr *sdr, const u32 grp) > { > u32 i; > > for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++) > - rw_mgr_incr_vfifo(grp); > + rw_mgr_incr_vfifo(sdr, grp); > } > > /** > @@ -1517,14 +1517,14 @@ static void rw_mgr_decr_vfifo(const u32 grp) > * > * Push VFIFO until a failing read happens. > */ > -static int find_vfifo_failing_read(const u32 grp) > +static int find_vfifo_failing_read(struct socfpga_sdr *sdr, const u32 grp) > { > u32 v, ret, fail_cnt = 0; > > for (v = 0; v < misccfg->read_valid_fifo_size; v++) { > debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n", > __func__, __LINE__, v); > - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, > + ret = rw_mgr_mem_calibrate_read_test_all_ranks(sdr, grp, 1, > PASS_ONE_BIT, 0); > if (!ret) { > fail_cnt++; > @@ -1534,7 +1534,7 @@ static int find_vfifo_failing_read(const u32 grp) > } > > /* Fiddle with FIFO. */ > - rw_mgr_incr_vfifo(grp); > + rw_mgr_incr_vfifo(sdr, grp); > } > > /* No failing read found! Something must have gone wrong. */ > @@ -1553,7 +1553,7 @@ static int find_vfifo_failing_read(const u32 grp) > * > * Find working or non-working DQS enable phase setting. > */ > -static int sdr_find_phase_delay(int working, int delay, const u32 grp, > +static int sdr_find_phase_delay(struct socfpga_sdr *sdr, int working, int > delay, const u32 grp, > u32 *work, const u32 work_inc, u32 *pd) > { > const u32 max = delay ? iocfg->dqs_en_delay_max : > @@ -1562,11 +1562,11 @@ static int sdr_find_phase_delay(int working, int > delay, const u32 grp, > > for (; *pd <= max; (*pd)++) { > if (delay) > - scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd); > + scc_mgr_set_dqs_en_delay_all_ranks(sdr, grp, *pd); > else > - scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd); > + scc_mgr_set_dqs_en_phase_all_ranks(sdr, grp, *pd); > > - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, > + ret = rw_mgr_mem_calibrate_read_test_all_ranks(sdr, grp, 1, > PASS_ONE_BIT, 0); > if (!working) > ret = !ret; > @@ -1590,7 +1590,7 @@ static int sdr_find_phase_delay(int working, int delay, > const u32 grp, > * > * Find working or non-working DQS enable phase setting. > */ > -static int sdr_find_phase(int working, const u32 grp, u32 *work, > +static int sdr_find_phase(struct socfpga_sdr *sdr, int working, const u32 > grp, u32 *work, > u32 *i, u32 *p) > { > const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1); > @@ -1600,14 +1600,14 @@ static int sdr_find_phase(int working, const u32 grp, > u32 *work, > if (working) > *p = 0; > > - ret = sdr_find_phase_delay(working, 0, grp, work, > + ret = sdr_find_phase_delay(sdr, working, 0, grp, work, > iocfg->delay_per_opa_tap, p); > if (!ret) > return 0; > > if (*p > iocfg->dqs_en_phase_max) { > /* Fiddle with FIFO. */ > - rw_mgr_incr_vfifo(grp); > + rw_mgr_incr_vfifo(sdr, grp); > if (!working) > *p = 0; > } > @@ -1626,7 +1626,7 @@ static int sdr_find_phase(int working, const u32 grp, > u32 *work, > * > * Find working DQS enable phase setting. > */ > -static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d, > +static int sdr_working_phase(struct socfpga_sdr *sdr, const u32 grp, u32 > *work_bgn, u32 *d, > u32 *p, u32 *i) > { > const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap / > @@ -1637,8 +1637,8 @@ static int sdr_working_phase(const u32 grp, u32 > *work_bgn, u32 *d, > > for (*d = 0; *d <= dtaps_per_ptap; (*d)++) { > *i = 0; > - scc_mgr_set_dqs_en_delay_all_ranks(grp, *d); > - ret = sdr_find_phase(1, grp, work_bgn, i, p); > + scc_mgr_set_dqs_en_delay_all_ranks(sdr, grp, *d); > + ret = sdr_find_phase(sdr, 1, grp, work_bgn, i, p); > if (!ret) > return 0; > *work_bgn += iocfg->delay_per_dqs_en_dchain_tap; > @@ -1658,7 +1658,7 @@ static int sdr_working_phase(const u32 grp, u32 > *work_bgn, u32 *d, > * > * Find DQS enable backup phase setting. > */ > -static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) > +static void sdr_backup_phase(struct socfpga_sdr *sdr, const u32 grp, u32 > *work_bgn, u32 *p) > { > u32 tmp_delay, d; > int ret; > @@ -1666,18 +1666,18 @@ static void sdr_backup_phase(const u32 grp, u32 > *work_bgn, u32 *p) > /* Special case code for backing up a phase */ > if (*p == 0) { > *p = iocfg->dqs_en_phase_max; > - rw_mgr_decr_vfifo(grp); > + rw_mgr_decr_vfifo(sdr, grp); > } else { > (*p)--; > } > tmp_delay = *work_bgn - iocfg->delay_per_opa_tap; > - scc_mgr_set_dqs_en_phase_all_ranks(grp, *p); > + scc_mgr_set_dqs_en_phase_all_ranks(sdr, grp, *p); > > for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; > d++) { > - scc_mgr_set_dqs_en_delay_all_ranks(grp, d); > + scc_mgr_set_dqs_en_delay_all_ranks(sdr, grp, d); > > - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, > + ret = rw_mgr_mem_calibrate_read_test_all_ranks(sdr, grp, 1, > PASS_ONE_BIT, 0); > if (ret) { > *work_bgn = tmp_delay; > @@ -1691,10 +1691,10 @@ static void sdr_backup_phase(const u32 grp, u32 > *work_bgn, u32 *p) > (*p)++; > if (*p > iocfg->dqs_en_phase_max) { > *p = 0; > - rw_mgr_incr_vfifo(grp); > + rw_mgr_incr_vfifo(sdr, grp); > } > > - scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); > + scc_mgr_set_dqs_en_delay_all_ranks(sdr, grp, 0); > } > > /** > @@ -1706,7 +1706,7 @@ static void sdr_backup_phase(const u32 grp, u32 > *work_bgn, u32 *p) > * > * Find non-working DQS enable phase setting. > */ > -static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i) > +static int sdr_nonworking_phase(struct socfpga_sdr *sdr, const u32 grp, u32 > *work_end, u32 *p, u32 *i) > { > int ret; > > @@ -1715,10 +1715,10 @@ static int sdr_nonworking_phase(const u32 grp, u32 > *work_end, u32 *p, u32 *i) > if (*p > iocfg->dqs_en_phase_max) { > /* Fiddle with FIFO. */ > *p = 0; > - rw_mgr_incr_vfifo(grp); > + rw_mgr_incr_vfifo(sdr, grp); > } > > - ret = sdr_find_phase(0, grp, work_end, i, p); > + ret = sdr_find_phase(sdr, 0, grp, work_end, i, p); > if (ret) { > /* Cannot see edge of failing read. */ > debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n", > @@ -1736,7 +1736,7 @@ static int sdr_nonworking_phase(const u32 grp, u32 > *work_end, u32 *p, u32 *i) > * > * Find center of the working DQS enable window. > */ > -static int sdr_find_window_center(const u32 grp, const u32 work_bgn, > +static int sdr_find_window_center(struct socfpga_sdr *sdr, const u32 grp, > const u32 work_bgn, > const u32 work_end) > { > u32 work_mid; > @@ -1769,8 +1769,8 @@ static int sdr_find_window_center(const u32 grp, const > u32 work_bgn, > > debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay); > > - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); > - scc_mgr_set_dqs_en_delay_all_ranks(grp, d); > + scc_mgr_set_dqs_en_phase_all_ranks(sdr, grp, p); > + scc_mgr_set_dqs_en_delay_all_ranks(sdr, grp, d); > > /* > * push vfifo until we can successfully calibrate. We can do this > @@ -1778,7 +1778,7 @@ static int sdr_find_window_center(const u32 grp, const > u32 work_bgn, > */ > for (i = 0; i < misccfg->read_valid_fifo_size; i++) { > debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n"); > - if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, > + if (rw_mgr_mem_calibrate_read_test_all_ranks(sdr, grp, 1, > PASS_ONE_BIT, > 0)) { > debug_cond(DLEVEL >= 2, > @@ -1788,7 +1788,7 @@ static int sdr_find_window_center(const u32 grp, const > u32 work_bgn, > } > > /* Fiddle with FIFO. */ > - rw_mgr_incr_vfifo(grp); > + rw_mgr_incr_vfifo(sdr, grp); > } > > debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n", > @@ -1802,7 +1802,7 @@ static int sdr_find_window_center(const u32 grp, const > u32 work_bgn, > * > * Find a good DQS enable to use. > */ > -static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > +static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdr > *sdr, const u32 grp) > { > u32 d, p, i; > u32 dtaps_per_ptap; > @@ -1812,21 +1812,21 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > > debug("%s:%d %u\n", __func__, __LINE__, grp); > > - reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); > + reg_file_set_sub_stage(sdr, CAL_SUBSTAGE_VFIFO_CENTER); > > - scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); > - scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); > + scc_mgr_set_dqs_en_delay_all_ranks(sdr, grp, 0); > + scc_mgr_set_dqs_en_phase_all_ranks(sdr, grp, 0); > > /* Step 0: Determine number of delay taps for each phase tap. */ > dtaps_per_ptap = iocfg->delay_per_opa_tap / > iocfg->delay_per_dqs_en_dchain_tap; > > /* Step 1: First push vfifo until we get a failing read. */ > - find_vfifo_failing_read(grp); > + find_vfifo_failing_read(sdr, grp); > > /* Step 2: Find first working phase, increment in ptaps. */ > work_bgn = 0; > - ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i); > + ret = sdr_working_phase(sdr, grp, &work_bgn, &d, &p, &i); > if (ret) > return ret; > > @@ -1842,13 +1842,13 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > * Step 3a: If we have room, back off by one and > * increment in dtaps. > */ > - sdr_backup_phase(grp, &work_bgn, &p); > + sdr_backup_phase(sdr, grp, &work_bgn, &p); > > /* > * Step 4a: go forward from working phase to non working > * phase, increment in ptaps. > */ > - ret = sdr_nonworking_phase(grp, &work_end, &p, &i); > + ret = sdr_nonworking_phase(sdr, grp, &work_end, &p, &i); > if (ret) > return ret; > > @@ -1857,13 +1857,13 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > /* Special case code for backing up a phase */ > if (p == 0) { > p = iocfg->dqs_en_phase_max; > - rw_mgr_decr_vfifo(grp); > + rw_mgr_decr_vfifo(sdr, grp); > } else { > p = p - 1; > } > > work_end -= iocfg->delay_per_opa_tap; > - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); > + scc_mgr_set_dqs_en_phase_all_ranks(sdr, grp, p); > > d = 0; > > @@ -1872,7 +1872,7 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > } > > /* The dtap increment to find the failing edge is done here. */ > - sdr_find_phase_delay(0, 1, grp, &work_end, > + sdr_find_phase_delay(sdr, 0, 1, grp, &work_end, > iocfg->delay_per_dqs_en_dchain_tap, &d); > > /* Go back to working dtap */ > @@ -1904,7 +1904,7 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > /* Special case code for backing up a phase */ > if (p == 0) { > p = iocfg->dqs_en_phase_max; > - rw_mgr_decr_vfifo(grp); > + rw_mgr_decr_vfifo(sdr, grp); > debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n", > __func__, __LINE__, p); > } else { > @@ -1913,7 +1913,7 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > __func__, __LINE__, p); > } > > - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); > + scc_mgr_set_dqs_en_phase_all_ranks(sdr, grp, p); > > /* > * Increase dtap until we first see a passing read (in case the > @@ -1927,13 +1927,13 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > > initial_failing_dtap = d; > > - found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d); > + found_passing_read = !sdr_find_phase_delay(sdr, 1, 1, grp, NULL, 0, &d); > if (found_passing_read) { > /* Find a failing read. */ > debug_cond(DLEVEL >= 2, "%s:%d find failing read\n", > __func__, __LINE__); > d++; > - found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0, > + found_failing_read = !sdr_find_phase_delay(sdr, 0, 1, grp, NULL, > 0, > &d); > } else { > debug_cond(DLEVEL >= 1, > @@ -1950,12 +1950,12 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > if (found_passing_read && found_failing_read) > dtaps_per_ptap = d - initial_failing_dtap; > > - writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap); > + writel(dtaps_per_ptap, &sdr->sdr_reg_file.dtaps_per_ptap); > debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u", > __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap); > > /* Step 6: Find the centre of the window. */ > - ret = sdr_find_window_center(grp, work_bgn, work_end); > + ret = sdr_find_window_center(sdr, grp, work_bgn, work_end); > > return ret; > } > @@ -1973,7 +1973,7 @@ static int > rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) > * > * Test if the found edge is valid. > */ > -static u32 search_stop_check(const int write, const int d, const int > rank_bgn, > +static u32 search_stop_check(struct socfpga_sdr *sdr, const int write, const > int d, const int rank_bgn, > const u32 write_group, const u32 read_group, > u32 *bit_chk, u32 *sticky_bit_chk, > const u32 use_read_test) > @@ -1990,16 +1990,16 @@ static u32 search_stop_check(const int write, const > int d, const int rank_bgn, > * we've seen a passing read on every bit. > */ > if (write) { /* WRITE-ONLY */ > - ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, > + ret = !rw_mgr_mem_calibrate_write_test(sdr, rank_bgn, > write_group, > 0, PASS_ONE_BIT, > bit_chk, 0); > } else if (use_read_test) { /* READ-ONLY */ > - ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, > + ret = !rw_mgr_mem_calibrate_read_test(sdr, rank_bgn, read_group, > NUM_READ_PB_TESTS, > PASS_ONE_BIT, bit_chk, > 0, 0); > } else { /* READ-ONLY */ > - rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, > + rw_mgr_mem_calibrate_write_test(sdr, rank_bgn, write_group, 0, > PASS_ONE_BIT, bit_chk, 0); > *bit_chk = *bit_chk >> (per_dqs * > (read_group - (write_group * ratio))); > @@ -2028,7 +2028,7 @@ static u32 search_stop_check(const int write, const int > d, const int rank_bgn, > * > * Find left edge of DQ/DQS working phase. > */ > -static void search_left_edge(const int write, const int rank_bgn, > +static void search_left_edge(struct socfpga_sdr *sdr, const int write, const > int rank_bgn, > const u32 write_group, const u32 read_group, const u32 test_bgn, > u32 *sticky_bit_chk, > int *left_edge, int *right_edge, const u32 use_read_test) > @@ -2044,13 +2044,13 @@ static void search_left_edge(const int write, const > int rank_bgn, > > for (d = 0; d <= dqs_max; d++) { > if (write) > - scc_mgr_apply_group_dq_out1_delay(d); > + scc_mgr_apply_group_dq_out1_delay(sdr, d); > else > - scc_mgr_apply_group_dq_in_delay(test_bgn, d); > + scc_mgr_apply_group_dq_in_delay(sdr, test_bgn, d); > > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > > - stop = search_stop_check(write, d, rank_bgn, write_group, > + stop = search_stop_check(sdr, write, d, rank_bgn, write_group, > read_group, &bit_chk, sticky_bit_chk, > use_read_test); > if (stop == 1) > @@ -2080,9 +2080,9 @@ static void search_left_edge(const int write, const int > rank_bgn, > > /* Reset DQ delay chains to 0 */ > if (write) > - scc_mgr_apply_group_dq_out1_delay(0); > + scc_mgr_apply_group_dq_out1_delay(sdr, 0); > else > - scc_mgr_apply_group_dq_in_delay(test_bgn, 0); > + scc_mgr_apply_group_dq_in_delay(sdr, test_bgn, 0); > > *sticky_bit_chk = 0; > for (i = per_dqs - 1; i >= 0; i--) { > @@ -2138,7 +2138,7 @@ static void search_left_edge(const int write, const int > rank_bgn, > * > * Find right edge of DQ/DQS working phase. > */ > -static int search_right_edge(const int write, const int rank_bgn, > +static int search_right_edge(struct socfpga_sdr *sdr, const int write, const > int rank_bgn, > const u32 write_group, const u32 read_group, > const int start_dqs, const int start_dqs_en, > u32 *sticky_bit_chk, > @@ -2155,22 +2155,22 @@ static int search_right_edge(const int write, const > int rank_bgn, > > for (d = 0; d <= dqs_max - start_dqs; d++) { > if (write) { /* WRITE-ONLY */ > - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, > + scc_mgr_apply_group_dqs_io_and_oct_out1(sdr, > write_group, > d + start_dqs); > } else { /* READ-ONLY */ > - scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); > + scc_mgr_set_dqs_bus_in_delay(sdr, read_group, d + > start_dqs); > if (iocfg->shift_dqs_en_when_shift_dqs) { > u32 delay = d + start_dqs_en; > if (delay > iocfg->dqs_en_delay_max) > delay = iocfg->dqs_en_delay_max; > - scc_mgr_set_dqs_en_delay(read_group, delay); > + scc_mgr_set_dqs_en_delay(sdr, read_group, > delay); > } > - scc_mgr_load_dqs(read_group); > + scc_mgr_load_dqs(sdr, read_group); > } > > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > > - stop = search_stop_check(write, d, rank_bgn, write_group, > + stop = search_stop_check(sdr, write, d, rank_bgn, write_group, > read_group, &bit_chk, sticky_bit_chk, > use_read_test); > if (stop == 1) { > @@ -2310,7 +2310,7 @@ static int get_window_mid_index(const int write, int > *left_edge, > * > * Align the DQ/DQS windows in each group. > */ > -static void center_dq_windows(const int write, int *left_edge, int > *right_edge, > +static void center_dq_windows(struct socfpga_sdr *sdr, const int write, int > *left_edge, int *right_edge, > const int mid_min, const int orig_mid_min, > const int min_index, const int test_bgn, > int *dq_margin, int *dqs_margin) > @@ -2321,7 +2321,7 @@ static void center_dq_windows(const int write, int > *left_edge, int *right_edge, > rwcfg->mem_dq_per_read_dqs; > const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET : > SCC_MGR_IO_IN_DELAY_OFFSET; > - const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off; > + const s32 addr = (u32)sdr | delay_off; > > s32 temp_dq_io_delay1; > int shift_dq, i, p; > @@ -2353,13 +2353,13 @@ static void center_dq_windows(const int write, int > *left_edge, int *right_edge, > i, shift_dq); > > if (write) > - scc_mgr_set_dq_out1_delay(i, > + scc_mgr_set_dq_out1_delay(sdr, i, > temp_dq_io_delay1 + shift_dq); > else > - scc_mgr_set_dq_in_delay(p, > + scc_mgr_set_dq_in_delay(sdr, p, > temp_dq_io_delay1 + shift_dq); > > - scc_mgr_load_dq(p); > + scc_mgr_load_dq(sdr, p); > > debug_cond(DLEVEL >= 2, > "vfifo_center: margin[%u]=[%d,%d]\n", i, > @@ -2385,12 +2385,12 @@ static void center_dq_windows(const int write, int > *left_edge, int *right_edge, > * > * Per-bit deskew DQ and centering. > */ > -static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, > +static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdr *sdr, const > u32 rank_bgn, > const u32 rw_group, const u32 test_bgn, > const int use_read_test, const int update_fom) > { > const u32 addr = > - SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET + > + (u32)sdr + SCC_MGR_DQS_IN_DELAY_OFFSET + > (rw_group << 2); > /* > * Store these as signed since there are comparisons with > @@ -2420,13 +2420,13 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 > rank_bgn, > } > > /* Search for the left edge of the window for each bit */ > - search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn, > + search_left_edge(sdr, 0, rank_bgn, rw_group, rw_group, test_bgn, > &sticky_bit_chk, > left_edge, right_edge, use_read_test); > > > /* Search for the right edge of the window for each bit */ > - ret = search_right_edge(0, rank_bgn, rw_group, rw_group, > + ret = search_right_edge(sdr, 0, rank_bgn, rw_group, rw_group, > start_dqs, start_dqs_en, > &sticky_bit_chk, > left_edge, right_edge, use_read_test); > @@ -2436,12 +2436,12 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 > rank_bgn, > * in rw_mgr_mem_calibrate_vfifo to retry different > * dqs/ck relationships. > */ > - scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs); > + scc_mgr_set_dqs_bus_in_delay(sdr, rw_group, start_dqs); > if (iocfg->shift_dqs_en_when_shift_dqs) > - scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en); > + scc_mgr_set_dqs_en_delay(sdr, rw_group, start_dqs_en); > > - scc_mgr_load_dqs(rw_group); > - writel(0, &sdr_scc_mgr->update); > + scc_mgr_load_dqs(sdr, rw_group); > + writel(0, &sdr->sdr_scc_mgr.update); > > debug_cond(DLEVEL >= 1, > "%s:%d vfifo_center: failed to find edge [%u]: %d > %d", > @@ -2490,19 +2490,19 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 > rank_bgn, > new_dqs, mid_min); > > /* Add delay to bring centre of all DQ windows to the same "level". */ > - center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min, > + center_dq_windows(sdr, 0, left_edge, right_edge, mid_min, orig_mid_min, > min_index, test_bgn, &dq_margin, &dqs_margin); > > /* Move DQS-en */ > if (iocfg->shift_dqs_en_when_shift_dqs) { > final_dqs_en = start_dqs_en - mid_min; > - scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en); > - scc_mgr_load_dqs(rw_group); > + scc_mgr_set_dqs_en_delay(sdr, rw_group, final_dqs_en); > + scc_mgr_load_dqs(sdr, rw_group); > } > > /* Move DQS */ > - scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs); > - scc_mgr_load_dqs(rw_group); > + scc_mgr_set_dqs_bus_in_delay(sdr, rw_group, new_dqs); > + scc_mgr_load_dqs(sdr, rw_group); > debug_cond(DLEVEL >= 2, > "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d", > __func__, __LINE__, dq_margin, dqs_margin); > @@ -2511,7 +2511,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 > rank_bgn, > * Do not remove this line as it makes sure all of our decisions > * have been applied. Apply the update bit. > */ > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > > if ((dq_margin < 0) || (dqs_margin < 0)) > return -EINVAL; > @@ -2528,13 +2528,13 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 > rank_bgn, > * device, the sequencer uses a guaranteed write mechanism to write data into > * the memory device. > */ > -static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, > +static int rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdr *sdr, > const u32 rw_group, > const u32 phase) > { > int ret; > > /* Set a particular DQ/DQS phase. */ > - scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase); > + scc_mgr_set_dqdqs_output_phase_all_ranks(sdr, rw_group, phase); > > debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n", > __func__, __LINE__, rw_group, phase); > @@ -2544,7 +2544,7 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const > u32 rw_group, > * Load up the patterns used by read calibration using the > * current DQDQS phase. > */ > - rw_mgr_mem_calibrate_read_load_patterns(0, 1); > + rw_mgr_mem_calibrate_read_load_patterns(sdr, 0, 1); > > if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ) > return 0; > @@ -2553,7 +2553,7 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const > u32 rw_group, > * Altera EMI_RM 2015.05.04 :: Figure 1-26 > * Back-to-Back reads of the patterns used for calibration. > */ > - ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1); > + ret = rw_mgr_mem_calibrate_read_test_patterns(sdr, 0, rw_group, 1); > if (ret) > debug_cond(DLEVEL >= 1, > "%s:%d Guaranteed read test failed: g=%u p=%u\n", > @@ -2569,7 +2569,7 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const > u32 rw_group, > * DQS enable calibration ensures reliable capture of the DQ signal without > * glitches on the DQS line. > */ > -static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, > +static int rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdr > *sdr, const u32 rw_group, > const u32 test_bgn) > { > /* > @@ -2595,18 +2595,18 @@ static int > rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, > "%s:%d: g=%u r=%u i=%u p=%u d=%u\n", > __func__, __LINE__, rw_group, r, i, p, d); > > - scc_mgr_set_dq_in_delay(p, d); > - scc_mgr_load_dq(p); > + scc_mgr_set_dq_in_delay(sdr, p, d); > + scc_mgr_load_dq(sdr, p); > } > > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > } > > /* > * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different > * dq_in_delay values > */ > - ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group); > + ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(sdr, rw_group); > > debug_cond(DLEVEL >= 1, > "%s:%d: g=%u found=%u; Reseting delay chain to zero\n", > @@ -2614,8 +2614,8 @@ static int > rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, > > for (r = 0; r < rwcfg->mem_number_of_ranks; > r += NUM_RANKS_PER_SHADOW_REG) { > - scc_mgr_apply_group_dq_in_delay(test_bgn, 0); > - writel(0, &sdr_scc_mgr->update); > + scc_mgr_apply_group_dq_in_delay(sdr, test_bgn, 0); > + writel(0, &sdr->sdr_scc_mgr.update); > } > > return ret; > @@ -2632,7 +2632,7 @@ static int > rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, > * within a group. > */ > static int > -rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, > +rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdr *sdr, const u32 > rw_group, const u32 test_bgn, > const int use_read_test, > const int update_fom) > > @@ -2648,7 +2648,7 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 > rw_group, const u32 test_bgn, > for (rank_bgn = 0, sr = 0; > rank_bgn < rwcfg->mem_number_of_ranks; > rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { > - ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group, > + ret = rw_mgr_mem_calibrate_vfifo_center(sdr, rank_bgn, rw_group, > test_bgn, > use_read_test, > update_fom); > @@ -2679,7 +2679,7 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 > rw_group, const u32 test_bgn, > * - DQS input phase and DQS input delay (DQ/DQS Centering) > * - we also do a per-bit deskew on the DQ lines. > */ > -static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) > +static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdr *sdr, const u32 > rw_group, const u32 test_bgn) > { > u32 p, d; > u32 dtaps_per_ptap; > @@ -2690,9 +2690,9 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 > rw_group, const u32 test_bgn) > debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn); > > /* Update info for sims */ > - reg_file_set_group(rw_group); > - reg_file_set_stage(CAL_STAGE_VFIFO); > - reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ); > + reg_file_set_group(sdr, rw_group); > + reg_file_set_stage(sdr, CAL_STAGE_VFIFO); > + reg_file_set_sub_stage(sdr, CAL_SUBSTAGE_GUARANTEED_READ); > > failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; > > @@ -2708,18 +2708,18 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 > rw_group, const u32 test_bgn) > * output side yet. > */ > if (d > 0) { > - scc_mgr_apply_group_all_out_delay_add_all_ranks( > + scc_mgr_apply_group_all_out_delay_add_all_ranks(sdr, > rw_group, d); > } > > for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) { > /* 1) Guaranteed Write */ > - ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, > p); > + ret = rw_mgr_mem_calibrate_guaranteed_write(sdr, > rw_group, p); > if (ret) > break; > > /* 2) DQS Enable Calibration */ > - ret = > rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group, > + ret = rw_mgr_mem_calibrate_dqs_enable_calibration(sdr, > rw_group, > test_b > gn); > if (ret) { > failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; > @@ -2731,7 +2731,7 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 > rw_group, const u32 test_bgn) > * If doing read after write calibration, do not update > * FOM now. Do it then. > */ > - ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, > + ret = rw_mgr_mem_calibrate_dq_dqs_centering(sdr, > rw_group, > test_bgn, 1, 0); > if (ret) { > failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; > @@ -2755,7 +2755,7 @@ cal_done_ok: > * first case). > */ > if (d > 2) > - scc_mgr_zero_group(rw_group, 1); > + scc_mgr_zero_group(sdr, rw_group, 1); > > return 1; > } > @@ -2770,7 +2770,7 @@ cal_done_ok: > * This function implements UniPHY calibration Stage 3, as explained in > * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". > */ > -static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, > +static int rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdr *sdr, const u32 > rw_group, > const u32 test_bgn) > { > int ret; > @@ -2778,11 +2778,11 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 > rw_group, > debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn); > > /* Update info for sims. */ > - reg_file_set_group(rw_group); > - reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); > - reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); > + reg_file_set_group(sdr, rw_group); > + reg_file_set_stage(sdr, CAL_STAGE_VFIFO_AFTER_WRITES); > + reg_file_set_sub_stage(sdr, CAL_SUBSTAGE_VFIFO_CENTER); > > - ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1); > + ret = rw_mgr_mem_calibrate_dq_dqs_centering(sdr, rw_group, test_bgn, 0, > 1); > if (ret) > set_failing_group_stage(rw_group, > CAL_STAGE_VFIFO_AFTER_WRITES, > @@ -2799,25 +2799,25 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 > rw_group, > * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". > * Calibrate LFIFO to find smallest read latency. > */ > -static u32 rw_mgr_mem_calibrate_lfifo(void) > +static u32 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdr *sdr) > { > int found_one = 0; > > debug("%s:%d\n", __func__, __LINE__); > > /* Update info for sims. */ > - reg_file_set_stage(CAL_STAGE_LFIFO); > - reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY); > + reg_file_set_stage(sdr, CAL_STAGE_LFIFO); > + reg_file_set_sub_stage(sdr, CAL_SUBSTAGE_READ_LATENCY); > > /* Load up the patterns used by read calibration for all ranks */ > - rw_mgr_mem_calibrate_read_load_patterns(0, 1); > + rw_mgr_mem_calibrate_read_load_patterns(sdr, 0, 1); > > do { > - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); > + writel(gbl->curr_read_lat, &sdr->phy_mgr_cfg.phy_rlat); > debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u", > __func__, __LINE__, gbl->curr_read_lat); > > - if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS, > + if (!rw_mgr_mem_calibrate_read_test_all_ranks(sdr, 0, > NUM_READ_TESTS, > PASS_ALL_BITS, 1)) > break; > > @@ -2830,12 +2830,12 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) > } while (gbl->curr_read_lat > 0); > > /* Reset the fifos to get pointers to known state. */ > - writel(0, &phy_mgr_cmd->fifo_reset); > + writel(0, &sdr->phy_mgr_cmd.fifo_reset); > > if (found_one) { > /* Add a fudge factor to the read latency that was determined */ > gbl->curr_read_lat += 2; > - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); > + writel(gbl->curr_read_lat, &sdr->phy_mgr_cfg.phy_rlat); > debug_cond(DLEVEL >= 2, > "%s:%d lfifo: success: using read_lat=%u\n", > __func__, __LINE__, gbl->curr_read_lat); > @@ -2865,7 +2865,7 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) > * > * Search for the/part of the window with DM/DQS shift. > */ > -static void search_window(const int search_dm, > +static void search_window(struct socfpga_sdr *sdr, const int search_dm, > const u32 rank_bgn, const u32 write_group, > int *bgn_curr, int *end_curr, int *bgn_best, > int *end_best, int *win_best, int new_dqs) > @@ -2878,7 +2878,7 @@ static void search_window(const int search_dm, > for (di = max; di >= 0; di -= DELTA_D) { > if (search_dm) { > d = di; > - scc_mgr_apply_group_dm_out1_delay(d); > + scc_mgr_apply_group_dm_out1_delay(sdr, d); > } else { > /* For DQS, we go from 0...max */ > d = max - di; > @@ -2886,13 +2886,13 @@ static void search_window(const int search_dm, > * Note: This only shifts DQS, so are we limiting > * ourselves to width of DQ unnecessarily. > */ > - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, > + scc_mgr_apply_group_dqs_io_and_oct_out1(sdr, > write_group, > d + new_dqs); > } > > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > > - if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1, > + if (rw_mgr_mem_calibrate_write_test(sdr, rank_bgn, write_group, > 1, > PASS_ALL_BITS, &bit_chk, > 0)) { > /* Set current end of the window. */ > @@ -2944,7 +2944,7 @@ static void search_window(const int search_dm, > * certain windows. > */ > static int > -rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, > +rw_mgr_mem_calibrate_writes_center(struct socfpga_sdr *sdr, const u32 > rank_bgn, const u32 write_group, > const u32 test_bgn) > { > int i; > @@ -2968,7 +2968,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > > dm_margin = 0; > > - start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | > + start_dqs = readl(((u32)sdr | > SCC_MGR_IO_OUT1_DELAY_OFFSET) + > (rwcfg->mem_dq_per_write_dqs << 2)); > > @@ -2985,12 +2985,12 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > } > > /* Search for the left edge of the window for each bit. */ > - search_left_edge(1, rank_bgn, write_group, 0, test_bgn, > + search_left_edge(sdr, 1, rank_bgn, write_group, 0, test_bgn, > &sticky_bit_chk, > left_edge, right_edge, 0); > > /* Search for the right edge of the window for each bit. */ > - ret = search_right_edge(1, rank_bgn, write_group, 0, > + ret = search_right_edge(sdr, 1, rank_bgn, write_group, 0, > start_dqs, 0, > &sticky_bit_chk, > left_edge, right_edge, 0); > @@ -3011,12 +3011,12 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > __func__, __LINE__, start_dqs, new_dqs, mid_min); > > /* Add delay to bring centre of all DQ windows to the same "level". */ > - center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min, > + center_dq_windows(sdr, 1, left_edge, right_edge, mid_min, orig_mid_min, > min_index, 0, &dq_margin, &dqs_margin); > > /* Move DQS */ > - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); > - writel(0, &sdr_scc_mgr->update); > + scc_mgr_apply_group_dqs_io_and_oct_out1(sdr, write_group, new_dqs); > + writel(0, &sdr->sdr_scc_mgr.update); > > /* Centre DM */ > debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__); > @@ -3029,11 +3029,11 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > right_edge[0] = iocfg->io_out1_delay_max + 1; > > /* Search for the/part of the window with DM shift. */ > - search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr, > + search_window(sdr, 1, rank_bgn, write_group, &bgn_curr, &end_curr, > &bgn_best, &end_best, &win_best, 0); > > /* Reset DM delay chains to 0. */ > - scc_mgr_apply_group_dm_out1_delay(0); > + scc_mgr_apply_group_dm_out1_delay(sdr, 0); > > /* > * Check to see if the current window nudges up aganist 0 delay. > @@ -3046,7 +3046,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > } > > /* Search for the/part of the window with DQS shifts. */ > - search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr, > + search_window(sdr, 0, rank_bgn, write_group, &bgn_curr, &end_curr, > &bgn_best, &end_best, &win_best, new_dqs); > > /* Assign left and right edge for cal and reporting. */ > @@ -3057,7 +3057,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > __func__, __LINE__, left_edge[0], right_edge[0]); > > /* Move DQS (back to orig). */ > - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); > + scc_mgr_apply_group_dqs_io_and_oct_out1(sdr, write_group, new_dqs); > > /* Move DM */ > > @@ -3074,8 +3074,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > else > dm_margin = left_edge[0] - mid; > > - scc_mgr_apply_group_dm_out1_delay(mid); > - writel(0, &sdr_scc_mgr->update); > + scc_mgr_apply_group_dm_out1_delay(sdr, mid); > + writel(0, &sdr->sdr_scc_mgr.update); > > debug_cond(DLEVEL >= 2, > "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n", > @@ -3092,7 +3092,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > * Do not remove this line as it makes sure all of our > * decisions have been applied. > */ > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > > if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0)) > return -EINVAL; > @@ -3111,7 +3111,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, > const u32 write_group, > * This function implements UniPHY calibration Stage 2, as explained in > * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". > */ > -static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, > +static int rw_mgr_mem_calibrate_writes(struct socfpga_sdr *sdr, const u32 > rank_bgn, const u32 group, > const u32 test_bgn) > { > int ret; > @@ -3119,11 +3119,11 @@ static int rw_mgr_mem_calibrate_writes(const u32 > rank_bgn, const u32 group, > /* Update info for sims */ > debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn); > > - reg_file_set_group(group); > - reg_file_set_stage(CAL_STAGE_WRITES); > - reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER); > + reg_file_set_group(sdr, group); > + reg_file_set_stage(sdr, CAL_STAGE_WRITES); > + reg_file_set_sub_stage(sdr, CAL_SUBSTAGE_WRITES_CENTER); > > - ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn); > + ret = rw_mgr_mem_calibrate_writes_center(sdr, rank_bgn, group, > test_bgn); > if (ret) > set_failing_group_stage(group, CAL_STAGE_WRITES, > CAL_SUBSTAGE_WRITES_CENTER); > @@ -3136,28 +3136,28 @@ static int rw_mgr_mem_calibrate_writes(const u32 > rank_bgn, const u32 group, > * > * Precharge all banks and activate row 0 in bank "000..." and bank "111...". > */ > -static void mem_precharge_and_activate(void) > +static void mem_precharge_and_activate(struct socfpga_sdr *sdr) > { > int r; > > for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { > /* Set rank. */ > - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); > + set_rank_and_odt_mask(sdr, r, RW_MGR_ODT_MODE_OFF); > > /* Precharge all banks. */ > - writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(rwcfg->precharge_all, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET); > > - writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0); > + writel(0x0F, &sdr->sdr_rw_load_mgr_regs.load_cntr0); > writel(rwcfg->activate_0_and_1_wait1, > - &sdr_rw_load_jump_mgr_regs->load_jump_add0); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add0); > > - writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1); > + writel(0x0F, &sdr->sdr_rw_load_mgr_regs.load_cntr1); > writel(rwcfg->activate_0_and_1_wait2, > - &sdr_rw_load_jump_mgr_regs->load_jump_add1); > + &sdr->sdr_rw_load_jump_mgr_regs.load_jump_add1); > > /* Activate rows. */ > - writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | > + writel(rwcfg->activate_0_and_1, ((u32)(&sdr->rwmgr_grp)) | > RW_MGR_RUN_SINGLE_GROUP_OFFSET); > } > } > @@ -3167,7 +3167,7 @@ static void mem_precharge_and_activate(void) > * > * Configure memory RLAT and WLAT parameters. > */ > -static void mem_init_latency(void) > +static void mem_init_latency(struct socfpga_sdr *sdr) > { > /* > * For AV/CV, LFIFO is hardened and always runs at full rate > @@ -3183,23 +3183,23 @@ static void mem_init_latency(void) > * Read in write latency. > * WL for Hard PHY does not include additive latency. > */ > - wlat = readl(&data_mgr->t_wl_add); > - wlat += readl(&data_mgr->mem_t_add); > + wlat = readl(&sdr->data_mgr.t_wl_add); > + wlat += readl(&sdr->data_mgr.mem_t_add); > > gbl->rw_wl_nop_cycles = wlat - 1; > > /* Read in readl latency. */ > - rlat = readl(&data_mgr->t_rl_add); > + rlat = readl(&sdr->data_mgr.t_rl_add); > > /* Set a pretty high read latency initially. */ > gbl->curr_read_lat = rlat + 16; > if (gbl->curr_read_lat > max_latency) > gbl->curr_read_lat = max_latency; > > - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); > + writel(gbl->curr_read_lat, &sdr->phy_mgr_cfg.phy_rlat); > > /* Advertise write latency. */ > - writel(wlat, &phy_mgr_cfg->afi_wlat); > + writel(wlat, &sdr->phy_mgr_cfg.afi_wlat); > } > > /** > @@ -3207,7 +3207,7 @@ static void mem_init_latency(void) > * > * Set VFIFO and LFIFO to instant-on settings in skip calibration mode. > */ > -static void mem_skip_calibrate(void) > +static void mem_skip_calibrate(struct socfpga_sdr *sdr) > { > u32 vfifo_offset; > u32 i, j, r; > @@ -3221,11 +3221,11 @@ static void mem_skip_calibrate(void) > * skip calibration. > */ > for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { > - scc_mgr_set_dqs_en_phase(i, 0); > + scc_mgr_set_dqs_en_phase(sdr, i, 0); > if (iocfg->dll_chain_length == 6) > - scc_mgr_set_dqdqs_output_phase(i, 6); > + scc_mgr_set_dqdqs_output_phase(sdr, i, 6); > else > - scc_mgr_set_dqdqs_output_phase(i, 7); > + scc_mgr_set_dqdqs_output_phase(sdr, i, 7); > /* > * Case:33398 > * > @@ -3252,27 +3252,27 @@ static void mem_skip_calibrate(void) > * > * (1.25 * iocfg->dll_chain_length - 2) > */ > - scc_mgr_set_dqdqs_output_phase(i, > + scc_mgr_set_dqdqs_output_phase(sdr, i, > ((125 * iocfg->dll_chain_length) / 100) - > 2); > } > - writel(0xff, &sdr_scc_mgr->dqs_ena); > - writel(0xff, &sdr_scc_mgr->dqs_io_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dqs_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dqs_io_ena); > > for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { > - writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | > + writel(i, (u32)sdr | > SCC_MGR_GROUP_COUNTER_OFFSET); > } > - writel(0xff, &sdr_scc_mgr->dq_ena); > - writel(0xff, &sdr_scc_mgr->dm_ena); > - writel(0, &sdr_scc_mgr->update); > + writel(0xff, &sdr->sdr_scc_mgr.dq_ena); > + writel(0xff, &sdr->sdr_scc_mgr.dm_ena); > + writel(0, &sdr->sdr_scc_mgr.update); > } > > /* Compensate for simulation model behaviour */ > for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { > - scc_mgr_set_dqs_bus_in_delay(i, 10); > - scc_mgr_load_dqs(i); > + scc_mgr_set_dqs_bus_in_delay(sdr, i, 10); > + scc_mgr_load_dqs(sdr, i); > } > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > > /* > * ArriaV has hard FIFOs that can only be initialized by incrementing > @@ -3280,15 +3280,15 @@ static void mem_skip_calibrate(void) > */ > vfifo_offset = misccfg->calib_vfifo_offset; > for (j = 0; j < vfifo_offset; j++) > - writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy); > - writel(0, &phy_mgr_cmd->fifo_reset); > + writel(0xff, &sdr->phy_mgr_cmd.inc_vfifo_hard_phy); > + writel(0, &sdr->phy_mgr_cmd.fifo_reset); > > /* > * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal > * setting from generation-time constant. > */ > gbl->curr_read_lat = misccfg->calib_lfifo_offset; > - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); > + writel(gbl->curr_read_lat, &sdr->phy_mgr_cfg.phy_rlat); > } > > /** > @@ -3296,7 +3296,7 @@ static void mem_skip_calibrate(void) > * > * Perform memory calibration. > */ > -static u32 mem_calibrate(void) > +static u32 mem_calibrate(struct socfpga_sdr *sdr) > { > u32 i; > u32 rank_bgn, sr; > @@ -3319,19 +3319,19 @@ static u32 mem_calibrate(void) > gbl->fom_out = 0; > > /* Initialize WLAT and RLAT. */ > - mem_init_latency(); > + mem_init_latency(sdr); > > /* Initialize bit slips. */ > - mem_precharge_and_activate(); > + mem_precharge_and_activate(sdr); > > for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { > - writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | > + writel(i, (u32)sdr | > SCC_MGR_GROUP_COUNTER_OFFSET); > /* Only needed once to set all groups, pins, DQ, DQS, DM. */ > if (i == 0) > - scc_mgr_set_hhp_extras(); > + scc_mgr_set_hhp_extras(sdr); > > - scc_set_bypass_mode(i); > + scc_set_bypass_mode(sdr, i); > } > > /* Calibration is skipped. */ > @@ -3340,13 +3340,13 @@ static u32 mem_calibrate(void) > * Set VFIFO and LFIFO to instant-on settings in skip > * calibration mode. > */ > - mem_skip_calibrate(); > + mem_skip_calibrate(sdr); > > /* > * Do not remove this line as it makes sure all of our > * decisions have been applied. > */ > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > return 1; > } > > @@ -3356,7 +3356,7 @@ static u32 mem_calibrate(void) > * Zero all delay chain/phase settings for all > * groups and all shadow register sets. > */ > - scc_mgr_zero_all(); > + scc_mgr_zero_all(sdr); > > run_groups = ~0; > > @@ -3374,9 +3374,9 @@ static u32 mem_calibrate(void) > if (current_run == 0) > continue; > > - writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS | > + writel(write_group, (u32)sdr | > SCC_MGR_GROUP_COUNTER_OFFSET); > - scc_mgr_zero_group(write_group, 0); > + scc_mgr_zero_group(sdr, write_group, 0); > > for (read_group = write_group * rwdqs_ratio, > read_test_bgn = 0; > @@ -3387,7 +3387,7 @@ static u32 mem_calibrate(void) > continue; > > /* Calibrate the VFIFO */ > - if (rw_mgr_mem_calibrate_vfifo(read_group, > + if (rw_mgr_mem_calibrate_vfifo(sdr, read_group, > read_test_bgn)) > continue; > > @@ -3412,7 +3412,7 @@ static u32 mem_calibrate(void) > continue; > > /* Calibrate WRITEs */ > - if (!rw_mgr_mem_calibrate_writes(rank_bgn, > + if (!rw_mgr_mem_calibrate_writes(sdr, rank_bgn, > write_group, > write_test_bgn) > ) > continue; > @@ -3435,7 +3435,7 @@ static u32 mem_calibrate(void) > if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) > continue; > > - if (!rw_mgr_mem_calibrate_vfifo_end(read_group, > + if (!rw_mgr_mem_calibrate_vfifo_end(sdr, > read_group, > read_test_bg > n)) > continue; > > @@ -3465,7 +3465,7 @@ grp_failed: /* A group failed, increment the > counter. */ > continue; > > /* Calibrate the LFIFO */ > - if (!rw_mgr_mem_calibrate_lfifo()) > + if (!rw_mgr_mem_calibrate_lfifo(sdr)) > return 0; > } > > @@ -3473,7 +3473,7 @@ grp_failed: /* A group failed, increment the > counter. */ > * Do not remove this line as it makes sure all of our decisions > * have been applied. > */ > - writel(0, &sdr_scc_mgr->update); > + writel(0, &sdr->sdr_scc_mgr.update); > return 1; > } > > @@ -3482,7 +3482,7 @@ grp_failed: /* A group failed, increment the > counter. */ > * > * This function triggers the entire memory calibration procedure. > */ > -static int run_mem_calibrate(void) > +static int run_mem_calibrate(struct socfpga_sdr *sdr) > { > int pass; > u32 ctrl_cfg; > @@ -3490,33 +3490,33 @@ static int run_mem_calibrate(void) > debug("%s:%d\n", __func__, __LINE__); > > /* Reset pass/fail status shown on afi_cal_success/fail */ > - writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status); > + writel(PHY_MGR_CAL_RESET, &sdr->phy_mgr_cfg.cal_status); > > /* Stop tracking manager. */ > - ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg); > + ctrl_cfg = readl(&sdr->sdr_ctrl.ctrl_cfg); > writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, > - &sdr_ctrl->ctrl_cfg); > + &sdr->sdr_ctrl.ctrl_cfg); > > - phy_mgr_initialize(); > - rw_mgr_mem_initialize(); > + phy_mgr_initialize(sdr); > + rw_mgr_mem_initialize(sdr); > > /* Perform the actual memory calibration. */ > - pass = mem_calibrate(); > + pass = mem_calibrate(sdr); > > - mem_precharge_and_activate(); > - writel(0, &phy_mgr_cmd->fifo_reset); > + mem_precharge_and_activate(sdr); > + writel(0, &sdr->phy_mgr_cmd.fifo_reset); > > /* Handoff. */ > - rw_mgr_mem_handoff(); > + rw_mgr_mem_handoff(sdr); > /* > * In Hard PHY this is a 2-bit control: > * 0: AFI Mux Select > * 1: DDIO Mux Select > */ > - writel(0x2, &phy_mgr_cfg->mux_sel); > + writel(0x2, &sdr->phy_mgr_cfg.mux_sel); > > /* Start tracking manager. */ > - writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); > + writel(ctrl_cfg, &sdr->sdr_ctrl.ctrl_cfg); > > return pass; > } > @@ -3528,7 +3528,7 @@ static int run_mem_calibrate(void) > * This function reports the results of the memory calibration > * and writes debug information into the register file. > */ > -static void debug_mem_calibrate(int pass) > +static void debug_mem_calibrate(struct socfpga_sdr *sdr, int pass) > { > u32 debug_info; > > @@ -3547,10 +3547,10 @@ static void debug_mem_calibrate(int pass) > /* Update the FOM in the register file */ > debug_info = gbl->fom_in; > debug_info |= gbl->fom_out << 8; > - writel(debug_info, &sdr_reg_file->fom); > + writel(debug_info, &sdr->sdr_reg_file.fom); > > - writel(debug_info, &phy_mgr_cfg->cal_debug_info); > - writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status); > + writel(debug_info, &sdr->phy_mgr_cfg.cal_debug_info); > + writel(PHY_MGR_CAL_SUCCESS, &sdr->phy_mgr_cfg.cal_status); > } else { > debug("%s: CALIBRATION FAILED\n", __FILE__); > > @@ -3558,15 +3558,15 @@ static void debug_mem_calibrate(int pass) > debug_info |= gbl->error_substage << 8; > debug_info |= gbl->error_group << 16; > > - writel(debug_info, &sdr_reg_file->failing_stage); > - writel(debug_info, &phy_mgr_cfg->cal_debug_info); > - writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status); > + writel(debug_info, &sdr->sdr_reg_file.failing_stage); > + writel(debug_info, &sdr->phy_mgr_cfg.cal_debug_info); > + writel(PHY_MGR_CAL_FAIL, &sdr->phy_mgr_cfg.cal_status); > > /* Update the failing group/stage in the register file */ > debug_info = gbl->error_stage; > debug_info |= gbl->error_substage << 8; > debug_info |= gbl->error_group << 16; > - writel(debug_info, &sdr_reg_file->failing_stage); > + writel(debug_info, &sdr->sdr_reg_file.failing_stage); > } > > debug("%s: Calibration complete\n", __FILE__); > @@ -3577,19 +3577,19 @@ static void debug_mem_calibrate(int pass) > * > * Initialize ROM data. > */ > -static void hc_initialize_rom_data(void) > +static void hc_initialize_rom_data(struct socfpga_sdr *sdr) > { > unsigned int nelem = 0; > const u32 *rom_init; > u32 i, addr; > > socfpga_get_seq_inst_init(&rom_init, &nelem); > - addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET; > + addr = ((u32)(&sdr->rwmgr_grp)) | RW_MGR_INST_ROM_WRITE_OFFSET; > for (i = 0; i < nelem; i++) > writel(rom_init[i], addr + (i << 2)); > > socfpga_get_seq_ac_init(&rom_init, &nelem); > - addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET; > + addr = ((u32)(&sdr->rwmgr_grp)) | RW_MGR_AC_ROM_WRITE_OFFSET; > for (i = 0; i < nelem; i++) > writel(rom_init[i], addr + (i << 2)); > } > @@ -3599,16 +3599,16 @@ static void hc_initialize_rom_data(void) > * > * Initialize SDR register file. > */ > -static void initialize_reg_file(void) > +static void initialize_reg_file(struct socfpga_sdr *sdr) > { > /* Initialize the register file with the correct data */ > - writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature); > - writel(0, &sdr_reg_file->debug_data_addr); > - writel(0, &sdr_reg_file->cur_stage); > - writel(0, &sdr_reg_file->fom); > - writel(0, &sdr_reg_file->failing_stage); > - writel(0, &sdr_reg_file->debug1); > - writel(0, &sdr_reg_file->debug2); > + writel(misccfg->reg_file_init_seq_signature, &sdr- > >sdr_reg_file.signature); > + writel(0, &sdr->sdr_reg_file.debug_data_addr); > + writel(0, &sdr->sdr_reg_file.cur_stage); > + writel(0, &sdr->sdr_reg_file.fom); > + writel(0, &sdr->sdr_reg_file.failing_stage); > + writel(0, &sdr->sdr_reg_file.debug1); > + writel(0, &sdr->sdr_reg_file.debug2); > } > > /** > @@ -3616,7 +3616,7 @@ static void initialize_reg_file(void) > * > * Initialize HPS PHY. > */ > -static void initialize_hps_phy(void) > +static void initialize_hps_phy(struct socfpga_sdr *sdr) > { > u32 reg; > /* > @@ -3644,7 +3644,7 @@ static void initialize_hps_phy(void) > reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0); > reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET( > trk_sample_count); > - writel(reg, &sdr_ctrl->phy_ctrl0); > + writel(reg, &sdr->sdr_ctrl.phy_ctrl0); > > reg = 0; > reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET( > @@ -3652,13 +3652,13 @@ static void initialize_hps_phy(void) > SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH); > reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET( > trk_long_idle_sample_count); > - writel(reg, &sdr_ctrl->phy_ctrl1); > + writel(reg, &sdr->sdr_ctrl.phy_ctrl1); > > reg = 0; > reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET( > trk_long_idle_sample_count >> > SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH); > - writel(reg, &sdr_ctrl->phy_ctrl2); > + writel(reg, &sdr->sdr_ctrl.phy_ctrl2); > } > > /** > @@ -3666,7 +3666,7 @@ static void initialize_hps_phy(void) > * > * Initialize the register file with usable initial data. > */ > -static void initialize_tracking(void) > +static void initialize_tracking(struct socfpga_sdr *sdr) > { > /* > * Initialize the register file with the correct data. > @@ -3675,13 +3675,13 @@ static void initialize_tracking(void) > */ > writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, > iocfg->delay_per_dchain_tap) - 1, > - &sdr_reg_file->dtaps_per_ptap); > + &sdr->sdr_reg_file.dtaps_per_ptap); > > /* trk_sample_count */ > - writel(7500, &sdr_reg_file->trk_sample_count); > + writel(7500, &sdr->sdr_reg_file.trk_sample_count); > > /* longidle outer loop [15:0] */ > - writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle); > + writel((10 << 16) | (100 << 0), &sdr->sdr_reg_file.trk_longidle); > > /* > * longidle sample count [31:24] > @@ -3690,22 +3690,22 @@ static void initialize_tracking(void) > * vfifo wait [7:0] > */ > writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0), > - &sdr_reg_file->delays); > + &sdr->sdr_reg_file.delays); > > /* mux delay */ > writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) | > (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0), > - &sdr_reg_file->trk_rw_mgr_addr); > + &sdr->sdr_reg_file.trk_rw_mgr_addr); > > writel(rwcfg->mem_if_read_dqs_width, > - &sdr_reg_file->trk_read_dqs_width); > + &sdr->sdr_reg_file.trk_read_dqs_width); > > /* trefi [7:0] */ > writel((rwcfg->refresh_all << 24) | (1000 << 0), > - &sdr_reg_file->trk_rfsh); > + &sdr->sdr_reg_file.trk_rfsh); > } > > -int sdram_calibration_full(void) > +int sdram_calibration_full(struct socfpga_sdr *sdr) > { > struct param_type my_param; > struct gbl_type my_gbl; > @@ -3731,14 +3731,14 @@ int sdram_calibration_full(void) > gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; > #endif > /* Initialize the register file */ > - initialize_reg_file(); > + initialize_reg_file(sdr); > > /* Initialize any PHY CSR */ > - initialize_hps_phy(); > + initialize_hps_phy(sdr); > > - scc_mgr_initialize(); > + scc_mgr_initialize(sdr); > > - initialize_tracking(); > + initialize_tracking(sdr); > > debug("%s: Preparing to start memory calibration\n", __FILE__); > > @@ -3766,11 +3766,11 @@ int sdram_calibration_full(void) > debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n", > iocfg->dqs_in_reserve, iocfg->dqs_out_reserve); > > - hc_initialize_rom_data(); > + hc_initialize_rom_data(sdr); > > /* update info for sims */ > - reg_file_set_stage(CAL_STAGE_NIL); > - reg_file_set_group(0); > + reg_file_set_stage(sdr, CAL_STAGE_NIL); > + reg_file_set_group(sdr, 0); > > /* > * Load global needed for those actions that require > @@ -3786,7 +3786,7 @@ int sdram_calibration_full(void) > else > skip_delay_mask = 0x0; > > - pass = run_mem_calibrate(); > - debug_mem_calibrate(pass); > + pass = run_mem_calibrate(sdr); > + debug_mem_calibrate(sdr, pass); > return pass; > } > diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h > index a5760b03a5..7e182f0140 100644 > --- a/drivers/ddr/altera/sequencer.h > +++ b/drivers/ddr/altera/sequencer.h > @@ -80,11 +80,11 @@ > #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00 > #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 > > -#define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) > +/*#define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) > #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) > #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) > #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | > 0x4000) > -#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | > 0x4800) > +#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | > 0x4800)*/ > > #define PHY_MGR_CAL_RESET (0) > #define PHY_MGR_CAL_SUCCESS (1) > @@ -223,4 +223,28 @@ struct socfpga_data_mgr { > u32 mem_t_add; > u32 t_rl_add; > }; > + > +struct socfpga_sdr { /* SOCFPGA_SDR_ADDRESS, SDR_PHYGRP_SCCGRP_ADDRESS */ > + u8 _align1[0xe00]; > + struct socfpga_sdr_scc_mgr sdr_scc_mgr; /* @ SDR_PHYGRP_SCCGRP_ADDRESS | > 0xe00 -> SOCFPGA_SDR_ADDRESS | 0xe00 */ > + u8 _align2[0x1bc]; > + struct socfpga_phy_mgr_cmd phy_mgr_cmd; /* SDR_PHYGRP_PHYMGRGRP_ADDRESS > -> SOCFPGA_SDR_ADDRESS | 0x1000 */ > + u8 _align3[0x2c]; > + struct socfpga_phy_mgr_cfg phy_mgr_cfg; /* SDR_PHYGRP_PHYMGRGRP_ADDRESS > | 0x40 -> SOCFPGA_SDR_ADDRESS | 0x1040 */ > + u8 _align4[0xfa0]; > + u8 rwmgr_grp[0x800]; /* SDR_PHYGRP_RWMGRGRP_ADDRESS -> > SOCFPGA_SDR_ADDRESS | 0x2000 */ > + struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs; /* > SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 -> SOCFPGA_SDR_ADDRESS | 0x2800 */ > + u8 _align5[0x3f0]; > + struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs; /* > SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 -> SOCFPGA_SDR_ADDRESS | 0x2C00 */ > + u8 _align6[0x13f0]; > + struct socfpga_data_mgr data_mgr; /* SDR_PHYGRP_DATAMGRGRP_ADDRESS -> > SOCFPGA_SDR_ADDRESS | 0x4000 */ > + u8 _align7[0x7f0]; > + struct socfpga_sdr_reg_file sdr_reg_file; /* > SDR_PHYGRP_REGFILEGRP_ADDRESS -> SOCFPGA_SDR_ADDRESS | 0x4800 */ > + u8 _align8[0x7c8]; > + struct socfpga_sdr_ctrl sdr_ctrl; /* SDR_CTRLGRP_ADDRESS -> > SOCFPGA_SDR_ADDRESS | 0x5000 */ > + u8 _align9[0xea4]; > +}; > + > +int sdram_calibration_full(struct socfpga_sdr *sdr); > + > #endif /* _SEQUENCER_H_ */