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From: "Souza, Jose" <jose.souza@intel.com>
To: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"chris@chris-wilson.co.uk" <chris@chris-wilson.co.uk>
Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH] drm/i915: Add not fenceable reason to not enable FBC
Date: Tue, 26 Mar 2019 01:11:06 +0000	[thread overview]
Message-ID: <e69bd67db1ae15a58931388ea934e6c10e12fdb5.camel@intel.com> (raw)
In-Reply-To: <155323836208.26447.7033200965287682560@skylake-alporthouse-com>


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On Fri, 2019-03-22 at 07:06 +0000, Chris Wilson wrote:
> Quoting José Roberto de Souza (2019-03-22 00:42:59)
> > There is some kms_frontbuffer_tracking failures due FBC being
> > disabled with the reason "framebuffer not tiled or fenced".
> > Although the test is setting up everything correctly to have
> > FBC enabled sporadically it is failing, due the alignment and size
> > restrictions in __i915_vma_set_map_and_fenceable().
> > 
> > So lets add another FBC failure reason and skip tests when that is
> > set and keep "framebuffer not tiled or fenced" as error as it
> > indicates that buffer is not tiled due wrong setup of the test.
> > 
> > Also fixing close typos.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108040
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_fbc.c | 15 +++++++++++++--
> >  1 file changed, 13 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> > b/drivers/gpu/drm/i915/intel_fbc.c
> > index 656e684e7c9a..2980a3b579e0 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -726,19 +726,30 @@ static bool intel_fbc_can_activate(struct
> > intel_crtc *crtc)
> >          * by the CPU to the scanout and trigger updates to the
> > FBC.
> >          *
> >          * Note that is possible for a tiled surface to be
> > unmappable (and
> > -        * so have no fence associated with it) due to aperture
> > constaints
> > +        * so have no fence associated with it) due to aperture
> > constraints
> >          * at the time of pinning.
> >          *
> >          * FIXME with 90/270 degree rotation we should use the
> > fence on
> >          * the normal GTT view (the rotated view doesn't even have
> > a
> >          * fence). Would need changes to the FBC fence Y offset as
> > well.
> > -        * For now this will effecively disable FBC with 90/270
> > degree
> > +        * For now this will effectively disable FBC with 90/270
> > degree
> >          * rotation.
> >          */
> > +       if (!(cache->vma->flags & I915_VMA_CAN_FENCE)) {
> 
> if (!i915_vma_is_map_and_fenceable(cache->vma)) {

Thanks

> 
> > +               /* Requirements not meet see
> > __i915_vma_set_map_and_fenceable() */
> 
> I would suggest pointing at intel_pin_and_fence_fb and
> i915_gem_object_pin_to_display_plane as to why it chose not to
> require
> a fence.

Oh so even if i915_vma_is_map_and_fenceable() returns true in
intel_pin_and_fence_fb_obj() it could still fail to set the fence in
i915_vma_pin_fence() because there is no fences available.

So I guess is better not add 'framebuffer is not fenceable' and skip
tests when 'framebuffer not tiled or fenced' is set, what do you think?


> -Chris

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  reply	other threads:[~2019-03-26  1:11 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22  0:42 [PATCH] drm/i915: Add not fenceable reason to not enable FBC José Roberto de Souza
2019-03-22  0:47 ` Souza, Jose
2019-03-22  3:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-03-22  7:06 ` [PATCH] " Chris Wilson
2019-03-26  1:11   ` Souza, Jose [this message]
2019-03-22 22:24 ` ✓ Fi.CI.IGT: success for " Patchwork

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