From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:33854) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1grGVU-0004sQ-AK for qemu-devel@nongnu.org; Wed, 06 Feb 2019 01:16:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1grGNG-0007Pc-54 for qemu-devel@nongnu.org; Wed, 06 Feb 2019 01:07:54 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35397) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1grGNF-0007PD-UN for qemu-devel@nongnu.org; Wed, 06 Feb 2019 01:07:54 -0500 Received: by mail-wr1-x435.google.com with SMTP id z18so5420519wrh.2 for ; Tue, 05 Feb 2019 22:07:52 -0800 (PST) References: <20190129191402.29539-1-svens@stackframe.org> From: Richard Henderson Message-ID: Date: Wed, 6 Feb 2019 06:07:47 +0000 MIME-Version: 1.0 In-Reply-To: <20190129191402.29539-1-svens@stackframe.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target/hppa: fix PSW Q bit behaviour to match hardware List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sven Schnelle , qemu-devel@nongnu.org Cc: deller@gmx.de, Richard Henderson On 1/29/19 7:14 PM, Sven Schnelle wrote: > PA-RISC specification says: "Setting the PSW Q-bit, PSW{28}, to 1 > with this instruction, if it was not already 1, is an undefined > operation." However, at least HP-UX 10.20 sets the Q bit from 0 to 1 > with the SSM instruction. Tested this both on HP9000/712 and > HP9000/785/C3750, both machines set the Q bit from 0 to 1 without > exception. This makes HP-UX 10.20 progress a little bit further. > > Signed-off-by: Sven Schnelle > --- > target/hppa/op_helper.c | 5 ----- > 1 file changed, 5 deletions(-) Queued, with much of this text copied into a comment in the code. r~