All of lore.kernel.org
 help / color / mirror / Atom feed
From: BALATON Zoltan <balaton@eik.bme.hu>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	laurent@vivier.eu, qemu-devel@nongnu.org
Subject: Re: [PATCH 01/11] mos6522: add defines for IFR bit flags
Date: Sat, 5 Feb 2022 13:06:29 +0100 (CET)	[thread overview]
Message-ID: <e6b2e9c-6082-cb63-a8ae-d96ab96e8c2e@eik.bme.hu> (raw)
In-Reply-To: <84db72ea-9aca-43f9-2876-28a5d6d840f4@amsat.org>

[-- Attachment #1: Type: text/plain, Size: 3449 bytes --]

On Sat, 5 Feb 2022, Philippe Mathieu-Daudé wrote:
> On 5/2/22 11:51, Mark Cave-Ayland wrote:
>> On 27/01/2022 23:16, BALATON Zoltan wrote:
>> 
>>> On Thu, 27 Jan 2022, Mark Cave-Ayland wrote:
>>>> These are intended to make it easier to see how the physical control 
>>>> lines
>>>> are wired for each instance.
>>>> 
>>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>>> ---
>>>> include/hw/misc/mos6522.h | 22 +++++++++++++++-------
>>>> 1 file changed, 15 insertions(+), 7 deletions(-)
>>>> 
>>>> diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h
>>>> index fc95d22b0f..12abd8b8d2 100644
>>>> --- a/include/hw/misc/mos6522.h
>>>> +++ b/include/hw/misc/mos6522.h
>>>> @@ -41,13 +41,21 @@
>>>> #define IER_SET            0x80    /* set bits in IER */
>>>> #define IER_CLR            0       /* clear bits in IER */
>>>> 
>>>> -#define CA2_INT            0x01
>>>> -#define CA1_INT            0x02
>>>> -#define SR_INT             0x04    /* Shift register full/empty */
>>>> -#define CB2_INT            0x08
>>>> -#define CB1_INT            0x10
>>>> -#define T2_INT             0x20    /* Timer 2 interrupt */
>>>> -#define T1_INT             0x40    /* Timer 1 interrupt */
>>>> +#define CA2_INT_BIT        0
>>>> +#define CA1_INT_BIT        1
>>>> +#define SR_INT_BIT         2       /* Shift register full/empty */
>>>> +#define CB2_INT_BIT        3
>>>> +#define CB1_INT_BIT        4
>>>> +#define T2_INT_BIT         5       /* Timer 2 interrupt */
>>>> +#define T1_INT_BIT         6       /* Timer 1 interrupt */
>>>> +
>>>> +#define CA2_INT            (1 << CA2_INT_BIT)
>>>> +#define CA1_INT            (1 << CA1_INT_BIT)
>>>> +#define SR_INT             (1 << SR_INT_BIT)
>>>> +#define CB2_INT            (1 << CB2_INT_BIT)
>>>> +#define CB1_INT            (1 << CB1_INT_BIT)
>>>> +#define T2_INT             (1 << T2_INT_BIT)
>>>> +#define T1_INT             (1 << T1_INT_BIT)
>>> 
>>> Maybe you could leave the #defines called XX_INT and then use BIT(XX_INT) 
>>> instead of the second set of #defines which would provide same readability 
>>> but with less #defines needed.
>> 
>> I'm not so keen on removing the _INT defines since that would require 
>> updating all users to use BIT() everywhere which I don't think gains us 
>> much. I could certainly replace these definitions with BIT(FOO) instead of 
>> (1 << FOO) if that helps readability though.
>
> Do you mean simply doing this?
>
> -#define T1_INT             0x40    /* Timer 1 interrupt */
> +#define T1_INT             BIT(6)  /* Timer 1 interrupt */

I meant:

#define T1_INT 6

and then replace current usage of T1_INT with BIT(T1_INT) that way we 
don't need both T1_INT_BIT and T1_INT defines which seems redundant as 
BIT(T1_INT) is not much longer and still clear what it refers to. It's 
true that this needs more changes but the result is more readable IMO than 
introducing another set of defines that ome has to look up when encounters 
them as the meaning might not be clear. That's why I think one set of 
defines for bit numbers and using existing BIT(num) for values is better 
but it's just an idea, I don't care that much.

Regards,
BALATON Zoltan

  reply	other threads:[~2022-02-05 12:09 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-27 20:53 [PATCH 00/11] mos6522: switch to gpios, add control line edge-triggering and extra debugging Mark Cave-Ayland
2022-01-27 20:53 ` [PATCH 01/11] mos6522: add defines for IFR bit flags Mark Cave-Ayland
2022-01-27 23:16   ` BALATON Zoltan
2022-02-05 10:51     ` Mark Cave-Ayland
2022-02-05 11:16       ` Philippe Mathieu-Daudé via
2022-02-05 12:06         ` BALATON Zoltan [this message]
2022-02-20 10:53           ` Mark Cave-Ayland
2022-02-20 19:21             ` BALATON Zoltan
2022-01-27 20:53 ` [PATCH 02/11] mac_via: use IFR bit flag constants for VIA1 IRQs Mark Cave-Ayland
2022-01-27 20:53 ` [PATCH 03/11] mac_via: use IFR bit flag constants for VIA2 IRQs Mark Cave-Ayland
2022-01-27 20:53 ` [PATCH 04/11] mos6522: switch over to use qdev gpios for IRQs Mark Cave-Ayland
2022-02-07 19:29   ` Peter Maydell
2022-02-20 11:01     ` Mark Cave-Ayland
2022-01-27 20:53 ` [PATCH 05/11] mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClass Mark Cave-Ayland
2022-02-07 19:30   ` Peter Maydell
2022-01-27 20:54 ` [PATCH 06/11] mos6522: use device_class_set_parent_reset() to propagate reset to parent Mark Cave-Ayland
2022-02-07 19:31   ` Peter Maydell
2022-01-27 20:54 ` [PATCH 07/11] mos6522: add register names to register read/write trace events Mark Cave-Ayland
2022-02-07 19:32   ` Peter Maydell
2022-01-27 20:54 ` [PATCH 08/11] mos6522: add "info via" HMP command for debugging Mark Cave-Ayland
2022-02-07 19:34   ` Peter Maydell
2022-02-08  5:14     ` Philippe Mathieu-Daudé via
2022-02-08  8:10       ` Markus Armbruster
2022-02-08 10:29         ` Dr. David Alan Gilbert
2022-02-08 11:52           ` Daniel P. Berrangé
2022-02-08 12:43             ` Mark Cave-Ayland
2022-02-08 13:03               ` Dr. David Alan Gilbert
2022-02-08 15:13             ` Markus Armbruster
2022-02-08 12:32           ` Mark Cave-Ayland
2022-02-08 13:04             ` Dr. David Alan Gilbert
2022-02-08 11:38   ` Daniel P. Berrangé
2022-02-08 12:39     ` Mark Cave-Ayland
2022-02-08 12:49       ` Daniel P. Berrangé
2022-02-08 13:06         ` Mark Cave-Ayland
2022-02-08 13:10           ` Daniel P. Berrangé
2022-02-20 17:18             ` Mark Cave-Ayland
2022-02-21 12:20               ` Philippe Mathieu-Daudé
2022-02-21 22:27                 ` Mark Cave-Ayland
2022-02-21 17:11               ` Daniel P. Berrangé
2022-02-21 22:29                 ` Mark Cave-Ayland
2022-02-22 15:03                   ` Dr. David Alan Gilbert
2022-02-24 12:26                     ` Mark Cave-Ayland
2022-01-27 20:54 ` [PATCH 09/11] mos6522: record last_irq_levels in mos6522_set_irq() Mark Cave-Ayland
2022-01-27 20:54 ` [PATCH 10/11] mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs Mark Cave-Ayland
2022-01-27 20:54 ` [PATCH 11/11] macio/pmu.c: remove redundant code Mark Cave-Ayland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e6b2e9c-6082-cb63-a8ae-d96ab96e8c2e@eik.bme.hu \
    --to=balaton@eik.bme.hu \
    --cc=f4bug@amsat.org \
    --cc=laurent@vivier.eu \
    --cc=mark.cave-ayland@ilande.co.uk \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.