From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751336AbdHaFU1 (ORCPT ); Thu, 31 Aug 2017 01:20:27 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:38345 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750816AbdHaFUZ (ORCPT ); Thu, 31 Aug 2017 01:20:25 -0400 Subject: Re: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 To: Maxime Ripard , Stefan Mavrodiev Cc: Rob Herring , Mark Rutland , Russell King , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com References: <1503901963-9457-1-git-send-email-stefan@olimex.com> <1503901963-9457-2-git-send-email-stefan@olimex.com> <20170830143728.friajjequvioqjpu@flea.lan> From: Stefan Mavrodiev Organization: Olimex Ltd. Message-ID: Date: Thu, 31 Aug 2017 08:20:18 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170830143728.friajjequvioqjpu@flea.lan> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/30/2017 05:37 PM, Maxime Ripard wrote: > Hi, > > On Mon, Aug 28, 2017 at 09:32:42AM +0300, Stefan Mavrodiev wrote: >> From revision J the board uses new phy chip LAN8710. Compared >> with RTL8201, RA17 pin is TXERR. It has pullup which causes phy >> not to work. To fix this PA17 is muxed with GMAC function. This >> makes the pin output-low. >> >> This patch is compatible with earlier board revisions, since this >> pin wasn't connected to phy. >> >> Signed-off-by: Stefan Mavrodiev >> --- >> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> index 0b7403e..cb1b081 100644 >> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> @@ -102,7 +102,7 @@ >> >> &gmac { >> pinctrl-names = "default"; >> - pinctrl-0 = <&gmac_pins_mii_a>; >> + pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; >> phy = <&phy1>; >> phy-mode = "mii"; >> status = "okay"; >> @@ -229,6 +229,11 @@ >> }; >> >> &pio { >> + gmac_txerr: gmac_txerr@0 { >> + pins = "PA17"; >> + function = "gmac"; >> + }; >> + > The patch looks fine, I still have one question though. > > Can a PHY operate without this signal? My real question is, would it > make sense to mux that pin for all the users, or is it an optional > signal that each board designer can choose to use or not? > > Thanks! > Maxime > This phy (LAN8710) cannot work without this pin. Part of the problem is in that we've replaced without paying attention to this signal. RTL8201 has no TXERR pin. The pin PA17 is used as reset signal and therefore is pulled up with resistor. However on old revisions this option (there is jumper pad between SOC and PHY). As I said, LAN8710 cannot work without this signal. In the datasheet is written: ... The controller drives TXER high when a transmit error is detected. ... In the current variant of the dts, all data is threated as error. So to answer you question. This is feature only on our board and highly depends on the chosen PHY. I don't think this should be muxed for all users. Best regards, Stefan Mavrodiev, Olimex Ltd. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Mavrodiev Subject: Re: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 Date: Thu, 31 Aug 2017 08:20:18 +0300 Message-ID: References: <1503901963-9457-1-git-send-email-stefan@olimex.com> <1503901963-9457-2-git-send-email-stefan@olimex.com> <20170830143728.friajjequvioqjpu@flea.lan> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20170830143728.friajjequvioqjpu-ZC1Zs529Oq4@public.gmane.org> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Maxime Ripard , Stefan Mavrodiev Cc: Rob Herring , Mark Rutland , Russell King , Chen-Yu Tsai , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org On 08/30/2017 05:37 PM, Maxime Ripard wrote: > Hi, > > On Mon, Aug 28, 2017 at 09:32:42AM +0300, Stefan Mavrodiev wrote: >> From revision J the board uses new phy chip LAN8710. Compared >> with RTL8201, RA17 pin is TXERR. It has pullup which causes phy >> not to work. To fix this PA17 is muxed with GMAC function. This >> makes the pin output-low. >> >> This patch is compatible with earlier board revisions, since this >> pin wasn't connected to phy. >> >> Signed-off-by: Stefan Mavrodiev >> --- >> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> index 0b7403e..cb1b081 100644 >> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> @@ -102,7 +102,7 @@ >> >> &gmac { >> pinctrl-names = "default"; >> - pinctrl-0 = <&gmac_pins_mii_a>; >> + pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; >> phy = <&phy1>; >> phy-mode = "mii"; >> status = "okay"; >> @@ -229,6 +229,11 @@ >> }; >> >> &pio { >> + gmac_txerr: gmac_txerr@0 { >> + pins = "PA17"; >> + function = "gmac"; >> + }; >> + > The patch looks fine, I still have one question though. > > Can a PHY operate without this signal? My real question is, would it > make sense to mux that pin for all the users, or is it an optional > signal that each board designer can choose to use or not? > > Thanks! > Maxime > This phy (LAN8710) cannot work without this pin. Part of the problem is in that we've replaced without paying attention to this signal. RTL8201 has no TXERR pin. The pin PA17 is used as reset signal and therefore is pulled up with resistor. However on old revisions this option (there is jumper pad between SOC and PHY). As I said, LAN8710 cannot work without this signal. In the datasheet is written: ... The controller drives TXER high when a transmit error is detected. ... In the current variant of the dts, all data is threated as error. So to answer you question. This is feature only on our board and highly depends on the chosen PHY. I don't think this should be muxed for all users. Best regards, Stefan Mavrodiev, Olimex Ltd. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: stefan.mavrodiev@gmail.com (Stefan Mavrodiev) Date: Thu, 31 Aug 2017 08:20:18 +0300 Subject: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 In-Reply-To: <20170830143728.friajjequvioqjpu@flea.lan> References: <1503901963-9457-1-git-send-email-stefan@olimex.com> <1503901963-9457-2-git-send-email-stefan@olimex.com> <20170830143728.friajjequvioqjpu@flea.lan> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08/30/2017 05:37 PM, Maxime Ripard wrote: > Hi, > > On Mon, Aug 28, 2017 at 09:32:42AM +0300, Stefan Mavrodiev wrote: >> From revision J the board uses new phy chip LAN8710. Compared >> with RTL8201, RA17 pin is TXERR. It has pullup which causes phy >> not to work. To fix this PA17 is muxed with GMAC function. This >> makes the pin output-low. >> >> This patch is compatible with earlier board revisions, since this >> pin wasn't connected to phy. >> >> Signed-off-by: Stefan Mavrodiev >> --- >> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> index 0b7403e..cb1b081 100644 >> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts >> @@ -102,7 +102,7 @@ >> >> &gmac { >> pinctrl-names = "default"; >> - pinctrl-0 = <&gmac_pins_mii_a>; >> + pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; >> phy = <&phy1>; >> phy-mode = "mii"; >> status = "okay"; >> @@ -229,6 +229,11 @@ >> }; >> >> &pio { >> + gmac_txerr: gmac_txerr at 0 { >> + pins = "PA17"; >> + function = "gmac"; >> + }; >> + > The patch looks fine, I still have one question though. > > Can a PHY operate without this signal? My real question is, would it > make sense to mux that pin for all the users, or is it an optional > signal that each board designer can choose to use or not? > > Thanks! > Maxime > This phy (LAN8710) cannot work without this pin. Part of the problem is in that we've replaced without paying attention to this signal. RTL8201 has no TXERR pin. The pin PA17 is used as reset signal and therefore is pulled up with resistor. However on old revisions this option (there is jumper pad between SOC and PHY). As I said, LAN8710 cannot work without this signal. In the datasheet is written: ... The controller drives TXER high when a transmit error is detected. ... In the current variant of the dts, all data is threated as error. So to answer you question. This is feature only on our board and highly depends on the chosen PHY. I don't think this should be muxed for all users. Best regards, Stefan Mavrodiev, Olimex Ltd.