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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id d5sm18218168wrp.39.2021.02.15.23.30.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Feb 2021 23:30:33 -0800 (PST) Subject: Re: [PATCH v2 30/42] esp: add 4 byte PDMA read and write transfers To: Mark Cave-Ayland , qemu-devel@nongnu.org, laurent@vivier.eu References: <20210209193018.31339-1-mark.cave-ayland@ilande.co.uk> <20210209193018.31339-31-mark.cave-ayland@ilande.co.uk> <0978e91b-d2e8-ce30-87de-cba2896ecc16@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 16 Feb 2021 08:30:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, pbonzini@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Mark, On 2/15/21 11:35 PM, Mark Cave-Ayland wrote: > On 12/02/2021 18:56, Philippe Mathieu-Daudé wrote: > >> On 2/9/21 8:30 PM, Mark Cave-Ayland wrote: >>> The MacOS toolbox ROM performs 4 byte reads/writes when transferring >>> data to >>> and from the target. Since the SCSI bus is 16-bits wide, use the >>> memory API >>> to split a 4 byte access into 2 x 2 byte accesses. >>> >>> Signed-off-by: Mark Cave-Ayland >>> --- >>>   hw/scsi/esp.c | 6 ++++-- >>>   1 file changed, 4 insertions(+), 2 deletions(-) >> >> Reviewed-by: Philippe Mathieu-Daudé >> >> Out of curiosity, what is the bus used? > > AFAICT it's a custom logic chip that sits on the CPU address/data buses > that does the decoding between the CPU and ESP chip. Other than a simple > block diagram of the Quadra there isn't much official documentation out > there :/ OK. > Are you planning to review any more of this series? I'm keen to put out > a (hopefully final) v3 soon, but I'll hold off for little while if you > want more time to look over the remaining patches. I talked about this series with Laurent on Sunday, asking him for review help ;) I don't remember if there is any big comment to address in patches 1-14. If not I can review the missing ones there today and you could send directly a pull request for this first set, then send the rest as v3. Does that help? For the rest I doubt having time to focus before Friday. Regards, Phil.