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From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
To: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>,
	agross@kernel.org, bjorn.andersson@linaro.org,
	lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
	plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz,
	tiwai@suse.com, rohitkr@codeaurora.org,
	linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	swboyd@chromium.org, judyhsiao@chromium.org
Cc: Venkata Prasad Potturu <potturu@codeaurora.org>
Subject: Re: [PATCH 3/7] ASoC: codecs: tx-macro: Change mic control registers to volatile
Date: Tue, 21 Sep 2021 09:48:33 +0100	[thread overview]
Message-ID: <e87ef6e1-0c10-beaa-81ad-2c0ceae6bbcc@linaro.org> (raw)
In-Reply-To: <b442ee2b-622c-674d-3abe-b1fbbfa5aeb9@codeaurora.org>



On 21/09/2021 08:30, Srinivasa Rao Mandadapu wrote:
> 
> On 9/20/2021 6:54 PM, Srinivas Kandagatla wrote:
> Thanks for your time Srini!!
>>
>> On 20/09/2021 08:35, Srinivasa Rao Mandadapu wrote:
>>> Update amic and dmic related tx macro control registers to volatile
>>>
>>> Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for 
>>> lpass tx macro)
>>>
>>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>> ---
>>>   sound/soc/codecs/lpass-tx-macro.c | 13 +++++++++++++
>>>   1 file changed, 13 insertions(+)
>>>
>>> diff --git a/sound/soc/codecs/lpass-tx-macro.c 
>>> b/sound/soc/codecs/lpass-tx-macro.c
>>> index 9273724..e65b592 100644
>>> --- a/sound/soc/codecs/lpass-tx-macro.c
>>> +++ b/sound/soc/codecs/lpass-tx-macro.c
>>> @@ -423,6 +423,13 @@ static bool tx_is_volatile_register(struct 
>>> device *dev, unsigned int reg)
>>>       case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
>>>       case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
>>>       case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
>>> +    case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
>>> +    case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
>>> +    case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
>>> +    case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
>>> +    case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
>>> +    case CDC_TX_TOP_CSR_SWR_CTRL:
>>> +    case CDC_TX0_TX_PATH_SEC7:
>>
>> Why are these marked as Volatile?
>> Can you provide some details on the issue that you are seeing?
>>
>> --srini
> 
> Without volatile these registers are not reflecting in Hardware and 
> playback and capture is not working.
> 
> Will do recheck and keep only required registers as volatile.

This sounds like a total hack to me,

this might be happening in your case:

The default values for this register are different to actual defaults.
Ex: CDC_TX_TOP_CSR_SWR_AMIC0_CTL default is 0x00
so writing 0x0 to this register will be no-op as there is no change in 
the register value as compared to default value as per regmap.

In you case make sure the hardware default values are correctly 
reflected in tx_defaults array.

Then setting the desired value should work.


--srini



> 
>>
>>
>>>           return true;
>>>       }
>>>       return false;
>>> @@ -1674,6 +1681,12 @@ static int tx_macro_component_probe(struct 
>>> snd_soc_component *comp)
>>>         snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
>>>                         0x0A);
>>> +    snd_soc_component_update_bits(comp, 
>>> CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
>>> +    snd_soc_component_update_bits(comp, 
>>> CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
>>> +    snd_soc_component_update_bits(comp, 
>>> CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0xFF, 0x00);
>>> +    snd_soc_component_update_bits(comp, 
>>> CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0xFF, 0x00);
>>> +    snd_soc_component_update_bits(comp, 
>>> CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0xFF, 0x00);
>>> +    snd_soc_component_update_bits(comp, 
>>> CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0xFF, 0x00);
>>>         return 0;
>>>   }
>>>

  reply	other threads:[~2021-09-21  8:48 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-20  7:35 [PATCH 0/7] Update Lpass digital codec macro drivers Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 1/7] ASoC: qcom: Add compatible names in va,wsa,rx,tx codec drivers for sc7280 Srinivasa Rao Mandadapu
2021-09-20  7:35   ` [PATCH 1/7] ASoC: qcom: Add compatible names in va, wsa, rx, tx " Srinivasa Rao Mandadapu
2021-09-20 18:17   ` [PATCH 1/7] ASoC: qcom: Add compatible names in va,wsa,rx,tx " Stephen Boyd
2021-09-20 18:17     ` Stephen Boyd
2021-09-21  8:42     ` Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 2/7] ASoC: qcom: dt-bindings: Add compatible names for lpass sc7280 digital codecs Srinivasa Rao Mandadapu
2021-09-20  7:35   ` Srinivasa Rao Mandadapu
2021-09-20 13:24   ` Srinivas Kandagatla
2021-09-21  6:59     ` Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 3/7] ASoC: codecs: tx-macro: Change mic control registers to volatile Srinivasa Rao Mandadapu
2021-09-20  7:35   ` Srinivasa Rao Mandadapu
2021-09-20 13:24   ` Srinivas Kandagatla
2021-09-21  7:30     ` Srinivasa Rao Mandadapu
2021-09-21  8:48       ` Srinivas Kandagatla [this message]
2021-09-21 13:02         ` Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 4/7] ASoC: codecs: lpass-va-macro: Change bulk voting to individual clock voting Srinivasa Rao Mandadapu
2021-09-20  7:35   ` Srinivasa Rao Mandadapu
2021-09-20 13:25   ` Srinivas Kandagatla
2021-09-21  8:14     ` Srinivasa Rao Mandadapu
2021-09-21  8:50       ` Srinivas Kandagatla
2021-09-21 12:25         ` Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 5/7] ASoC: codecs: lpass-rx-macro: " Srinivasa Rao Mandadapu
2021-09-20  7:35   ` Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 6/7] ASoC: codecs: lpass-tx-macro: " Srinivasa Rao Mandadapu
2021-09-20  7:35   ` Srinivasa Rao Mandadapu
2021-09-20  7:35 ` [PATCH 7/7] ASoC: codecs: lpass-va-macro: set mclk clock rate correctly Srinivasa Rao Mandadapu
2021-09-20  7:35   ` Srinivasa Rao Mandadapu

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