Re: [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers

From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers
Date: Mon, 5 Feb 2018 05:55:49 -0800	[thread overview]
Message-ID: <e8ac6889-2231-5947-fd7c-8c927e993b29@linaro.org> (raw)
In-Reply-To: <1517811767-75958-5-git-send-email-mjc@sifive.com>

On 02/04/2018 10:22 PM, Michael Clark wrote:
> Privileged control and status register helpers and page fault handling.
> 
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  target/riscv/helper.c    | 464 ++++++++++++++++++++++++++++++++++
>  target/riscv/helper.h    |  78 ++++++
>  target/riscv/op_helper.c | 644 +++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 1186 insertions(+)
>  create mode 100644 target/riscv/helper.c
>  create mode 100644 target/riscv/helper.h
>  create mode 100644 target/riscv/op_helper.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

> +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    if (interrupt_request & CPU_INTERRUPT_HARD) {
> +        RISCVCPU *cpu = RISCV_CPU(cs);
> +        CPURISCVState *env = &cpu->env;
> +        int interruptno = riscv_cpu_hw_interrupts_pending(env);
> +        if (interruptno + 1) {

Perhaps clearer as (interrupno >= 0) or (interruptno != -1).
But it's not actively wrong, so tidy at your convenience.

r~