Re: [PATCH 3/4] Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"

["Christian König" <ckoenig.leichtzumerken@gmail.com>]

Am 25.03.21 um 17:38 schrieb Oak Zeng:
> This reverts commit 34a33d4683cba7ba63c894132efb1998c0217631.

We need a single sentence here why we do the revert and I think you need 
to reorder the patches.

E.g. patch #3 should be #4 and #4 should be #3, otherwise you break the 
driver in between.

Apart from that looks like a nice cleanup to me.

Christian.

>
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h  |  9 ---------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  | 10 ----------
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 21 ++++++---------------
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c  | 10 ++++------
>   4 files changed, 10 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 7cd9d34..a9e0bba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -217,15 +217,6 @@ struct amdgpu_gmc {
>   	 */
>   	u64			fb_start;
>   	u64			fb_end;
> -	/* In the case of use GART table for vmid0 FB access, [fb_start, fb_end]
> -	 * will be squeezed to GART aperture. But we have a PSP FW issue to fix
> -	 * for now. To temporarily workaround the PSP FW issue, added below two
> -	 * variables to remember the original fb_start/end to re-enable FB
> -	 * aperture to workaround the PSP FW issue. Will delete it after we
> -	 * get a proper PSP FW fix.
> -	 */
> -	u64			fb_start_original;
> -	u64			fb_end_original;
>   	unsigned		vram_width;
>   	u64			real_vram_size;
>   	int			vram_mtrr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 5c71c5c..1005124 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -410,16 +410,6 @@ static int psp_tmr_init(struct psp_context *psp)
>   				      AMDGPU_GEM_DOMAIN_VRAM,
>   				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
>   
> -	/* workaround the tmr_mc_addr:
> -	 * PSP requires an address in FB aperture. Right now driver produce
> -	 * tmr_mc_addr in the GART aperture. Convert it back to FB aperture
> -	 * for PSP. Will revert it after we get a fix from PSP FW.
> -	 */
> -	if (psp->adev->asic_type == CHIP_ALDEBARAN) {
> -		psp->tmr_mc_addr -= psp->adev->gmc.fb_start;
> -		psp->tmr_mc_addr += psp->adev->gmc.fb_start_original;
> -	}
> -
>   	return ret;
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 7beef4c..8c8f0d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -154,21 +154,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
>   	 * FB aperture and AGP aperture. Disable them.
>   	 */
>   	if (adev->gmc.pdb0_bo) {
> -		if (adev->asic_type == CHIP_ALDEBARAN) {
> -			WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24);
> -			WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24);
> -			WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
> -			WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);
> -			WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18);
> -			WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18);
> -		} else {
> -			WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
> -			WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
> -			WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
> -			WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);
> -			WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
> -			WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
> -		}
> +		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
> +		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
> +		WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
> +		WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);
> +		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
> +		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
>   	}
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
> index 8862ac2..8bb36d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
> @@ -51,8 +51,6 @@ static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
>   
>   	adev->gmc.fb_start = base;
>   	adev->gmc.fb_end = top;
> -	adev->gmc.fb_start_original = base;
> -	adev->gmc.fb_end_original = top;
>   
>   	return base;
>   }
> @@ -148,10 +146,10 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
>   	if (adev->gmc.pdb0_bo) {
>   		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
>   		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
> -		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24);
> -		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24);
> -		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18);
> -		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18);
> +		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
> +		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
> +		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
> +		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
>   	}
>   	if (amdgpu_sriov_vf(adev))
>   		return;

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