All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
@ 2019-04-04 13:44 Pu Wen
  2019-04-04 13:45 ` [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
                   ` (17 more replies)
  0 siblings, 18 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:44 UTC (permalink / raw)
  To: xen-devel
  Cc: Stefano Stabellini, Wei Liu, Suravee Suthikulpanit,
	Konrad Rzeszutek Wilk, George Dunlap, Pu Wen, Ian Jackson,
	Tim Deegan, Julien Grall, Jan Beulich, Andrew Cooper,
	Boris Ostrovsky, Brian Woods, Roger Pau Monné

As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon)
is a joint venture between AMD and Haiguang Information Technology Co.,
Ltd., aims at providing high performance x86 processors for China
server market.

The first generation Hygon processor(Dhyana) originates from AMD
technology and shares most of the architecture with AMD's family 17h,
but with different CPU vendor ID("HygonGenuine") and family series
number 18h (Hygon negotiated with AMD to make sure that only Hygon
will use family 18h).

To enable support of Xen to Hygon Dhyana CPU, add a new vendor type
(X86_VENDOR_HYGON, with value of 5), and share most of the code with
AMD family 17h.

The MSRs and CPUIDs which are used by this patch series are all defined
in this PPR[1].

This patch series have been applied and tested successfully on Hygon
Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
It works fine and makes no harm to the existing code.

Reference:
[1] https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf


v4->v5:
  - Rebased over https://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=0763cd26
    to fit the new x86 vendor lookup mechanism.
  - Rework patch 15/15 to fit the new x86 vendor lookup mechanism.
  - Add Acked-by from Jan Beulich for patch 02/15 and 04/15.
  - Retain more conditionals from amd.c.
  - Refine coding style.

v3->v4:
  - Revert opt_cpuid_mask_l7s0_(eax/ebx) to amd.c.
  - Create a separate patch to fix common cpuid faulting probing issue
    for AMD and Hygon.
  - Rename _vpmu_init() to common_init() and move the default case into it.
  - Coding style refine.

v2->v3:
  - Rebased on 4.13-unstable and tested against it.
  - Simplify code of hygon.c by re-using early_init_amd().
  - Return false in the function probe_cpuid_faulting().
  - Adjust code for calculating phys_proc_id for Hygon.
  - Abstract common function _vpmu_init() and add hygon_vpmu_init().
  - Refine some comments and descriptions.
  - Add Acked-by from Jan Beulich for x86/cpu/mtrr, x86/cpu/mce,
    x86/spec_ctrl, x86/apic, x86/acpi, x86/iommu, x86/pv, x86/domain,
    x86/domctl and x86/cpuid.

v1->v2:
  - Rebased on 4.12.0-rc3 and tested against it.
  - Move opt_cpuid_mask_l7s0_(eax/ebx) to common.c.
  - Insert Hygon cases after AMD ones instead of above.
  - Remove (rd/wr)msr_hygon_safe and use (rd/wr)msr_safe instead.
  - Remove wrmsr_hygon and use wrmsrl instead.
  - Remove the unnecessary change to xstate.
  - Refine some codes and comments.
  - Add Acked-by from Jan Beulich for x86/traps.
  - Add Acked-by from Wei Liu for tools/libxc.


Pu Wen (15):
  x86/cpu: Create Hygon Dhyana architecture support file
  x86/cpu: Fix common cpuid faulting probing for AMD and Hygon
  x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2
  x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU
  x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure
  x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery
  x86/apic: Add Hygon Dhyana support
  x86/acpi: Add Hygon Dhyana support
  x86/iommu: Add Hygon Dhyana support
  x86/pv: Add Hygon Dhyana support to emulate MSRs access
  x86/domain: Add Hygon Dhyana support
  x86/domctl: Add Hygon Dhyana support
  x86/traps: Add Hygon Dhyana support
  x86/cpuid: Add Hygon Dhyana support
  tools/libxc: Add Hygon Dhyana support

 tools/libxc/xc_cpuid_x86.c             |  11 ++--
 xen/arch/x86/acpi/cpu_idle.c           |   3 +-
 xen/arch/x86/acpi/cpufreq/cpufreq.c    |   8 ++-
 xen/arch/x86/acpi/cpufreq/powernow.c   |   3 +-
 xen/arch/x86/apic.c                    |   5 ++
 xen/arch/x86/cpu/Makefile              |   1 +
 xen/arch/x86/cpu/amd.c                 |   2 +-
 xen/arch/x86/cpu/common.c              |   9 ++-
 xen/arch/x86/cpu/cpu.h                 |   3 +
 xen/arch/x86/cpu/hygon.c               | 114 +++++++++++++++++++++++++++++++++
 xen/arch/x86/cpu/mcheck/amd_nonfatal.c |   5 +-
 xen/arch/x86/cpu/mcheck/mce.c          |   6 +-
 xen/arch/x86/cpu/mcheck/mce_amd.c      |   5 +-
 xen/arch/x86/cpu/mcheck/non-fatal.c    |   3 +-
 xen/arch/x86/cpu/mcheck/vmce.c         |   2 +
 xen/arch/x86/cpu/mtrr/generic.c        |   5 +-
 xen/arch/x86/cpu/vpmu.c                |   8 +++
 xen/arch/x86/cpu/vpmu_amd.c            |  61 ++++++++++++------
 xen/arch/x86/cpuid.c                   |  10 ++-
 xen/arch/x86/dom0_build.c              |   3 +-
 xen/arch/x86/domain.c                  |   9 +--
 xen/arch/x86/domctl.c                  |  13 +++-
 xen/arch/x86/pv/emul-priv-op.c         |  19 ++++--
 xen/arch/x86/spec_ctrl.c               |   6 +-
 xen/arch/x86/traps.c                   |   3 +
 xen/include/asm-x86/iommu.h            |   1 +
 xen/include/asm-x86/vpmu.h             |   1 +
 xen/include/asm-x86/x86-vendors.h      |   7 +-
 xen/lib/x86/cpuid.c                    |   6 ++
 29 files changed, 275 insertions(+), 57 deletions(-)
 create mode 100644 xen/arch/x86/cpu/hygon.c

-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
@ 2019-04-04 13:45 ` Pu Wen
  2019-04-04 14:02   ` Andrew Cooper
  2019-04-04 13:45 ` [PATCH v5 02/15] x86/cpu: Fix common cpuid faulting probing for AMD and Hygon Pu Wen
                   ` (16 subsequent siblings)
  17 siblings, 1 reply; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:45 UTC (permalink / raw)
  To: xen-devel
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Pu Wen, Ian Jackson, Tim Deegan, Julien Grall,
	Jan Beulich, Andrew Cooper, Roger Pau Monné

Add x86 architecture support for a new processor: Hygon Dhyana Family
18h. To make Hygon initialization flow more clear, carve out code from
amd.c into a separate file hygon.c, and remove unnecessary code for
Hygon Dhyana.

To identify Hygon Dhyana CPU, add a new vendor type X86_VENDOR_HYGON
and vendor ID "HygonGenuine" for system recognition, and fit the new
x86 vendor lookup mechanism.

Hygon can fully use the function early_init_amd(), so make this common
function non-static and direct call it from Hygon code.

Add a separate hygon_get_topology(), which calculate phys_proc_id from
AcpiId[6](see reference [1]).

Reference:
[1] https://git.kernel.org/tip/e0ceeae708cebf22c990c3d703a4ca187dc837f5

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 xen/arch/x86/cpu/Makefile         |   1 +
 xen/arch/x86/cpu/amd.c            |   2 +-
 xen/arch/x86/cpu/common.c         |   1 +
 xen/arch/x86/cpu/cpu.h            |   3 +
 xen/arch/x86/cpu/hygon.c          | 114 ++++++++++++++++++++++++++++++++++++++
 xen/include/asm-x86/x86-vendors.h |   7 ++-
 xen/lib/x86/cpuid.c               |   6 ++
 7 files changed, 132 insertions(+), 2 deletions(-)
 create mode 100644 xen/arch/x86/cpu/hygon.c

diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index 34a01ca..466acc8 100644
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -4,6 +4,7 @@ subdir-y += mtrr
 obj-y += amd.o
 obj-y += centaur.o
 obj-y += common.o
+obj-y += hygon.o
 obj-y += intel.o
 obj-y += intel_cacheinfo.o
 obj-y += mwait-idle.o
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 7a73d62..6554d5d 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -526,7 +526,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
                                                           : c->cpu_core_id);
 }
 
-static void early_init_amd(struct cpuinfo_x86 *c)
+void early_init_amd(struct cpuinfo_x86 *c)
 {
 	if (c == &boot_cpu_data)
 		amd_init_levelling();
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index b2249b5..74c9426 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -691,6 +691,7 @@ void __init early_cpu_init(void)
 	amd_init_cpu();
 	centaur_init_cpu();
 	shanghai_init_cpu();
+	hygon_init_cpu();
 	early_cpu_detect();
 }
 
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index edc88b1..c3ae2ee 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -16,7 +16,10 @@ extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
 extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
 
+void early_init_amd(struct cpuinfo_x86 *c);
+
 int intel_cpu_init(void);
 int amd_init_cpu(void);
 int centaur_init_cpu(void);
 int shanghai_init_cpu(void);
+int hygon_init_cpu(void);
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
new file mode 100644
index 0000000..912849c
--- /dev/null
+++ b/xen/arch/x86/cpu/hygon.c
@@ -0,0 +1,114 @@
+#include <xen/init.h>
+#include <asm/processor.h>
+#include <asm/hvm/support.h>
+#include <asm/spec_ctrl.h>
+
+#include "cpu.h"
+
+#define APICID_SOCKET_ID_BIT 6
+
+static void hygon_get_topology(struct cpuinfo_x86 *c)
+{
+	unsigned int ebx;
+
+	if (c->x86_max_cores <= 1)
+		return;
+
+	/* Socket ID is ApicId[6] for Hygon processors. */
+	c->phys_proc_id >>= APICID_SOCKET_ID_BIT;
+
+	ebx = cpuid_ebx(0x8000001e);
+	c->x86_num_siblings = ((ebx >> 8) & 0x3) + 1;
+	c->x86_max_cores /= c->x86_num_siblings;
+	c->cpu_core_id = ebx & 0xff;
+
+	if (opt_cpu_info)
+	        printk("CPU %d(%d) -> Processor %d, Core %d\n",
+	                smp_processor_id(), c->x86_max_cores,
+	                        c->phys_proc_id, c->cpu_core_id);
+}
+
+static void init_hygon(struct cpuinfo_x86 *c)
+{
+	unsigned long long value;
+
+	/*
+	 * Attempt to set lfence to be Dispatch Serialising.  This MSR almost
+	 * certainly isn't virtualised (and Xen at least will leak the real
+	 * value in but silently discard writes), as well as being per-core
+	 * rather than per-thread, so do a full safe read/write/readback cycle
+	 * in the worst case.
+	 */
+	if (rdmsr_safe(MSR_AMD64_DE_CFG, value))
+		/* Unable to read.  Assume the safer default. */
+		__clear_bit(X86_FEATURE_LFENCE_DISPATCH,
+			    c->x86_capability);
+	else if (value & AMD64_DE_CFG_LFENCE_SERIALISE)
+		/* Already dispatch serialising. */
+		__set_bit(X86_FEATURE_LFENCE_DISPATCH,
+			  c->x86_capability);
+	else if (wrmsr_safe(MSR_AMD64_DE_CFG,
+			    value | AMD64_DE_CFG_LFENCE_SERIALISE) ||
+		 rdmsr_safe(MSR_AMD64_DE_CFG, value) ||
+		 !(value & AMD64_DE_CFG_LFENCE_SERIALISE))
+		/* Attempt to set failed.  Assume the safer default. */
+		__clear_bit(X86_FEATURE_LFENCE_DISPATCH,
+			    c->x86_capability);
+	else
+		/* Successfully enabled! */
+		__set_bit(X86_FEATURE_LFENCE_DISPATCH,
+			  c->x86_capability);
+
+	/*
+	 * If the user has explicitly chosen to disable Memory Disambiguation
+	 * to mitigiate Speculative Store Bypass, poke the appropriate MSR.
+	 */
+	if (opt_ssbd && !rdmsr_safe(MSR_AMD64_LS_CFG, value)) {
+		value |= 1ull << 10;
+		wrmsr_safe(MSR_AMD64_LS_CFG, value);
+	}
+
+	/* MFENCE stops RDTSC speculation */
+	if (!cpu_has_lfence_dispatch)
+		__set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
+
+	display_cacheinfo(c);
+
+	if (c->extended_cpuid_level >= 0x80000008)
+		c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
+
+	if (c->extended_cpuid_level >= 0x80000007) {
+		if (cpu_has(c, X86_FEATURE_ITSC)) {
+			__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+			__set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+			__set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
+		}
+	}
+
+	hygon_get_topology(c);
+
+	/* Hygon CPUs do not support SYSENTER outside of legacy mode. */
+	__clear_bit(X86_FEATURE_SEP, c->x86_capability);
+
+	/* Hygon processors have APIC timer running in deep C states. */
+	if (opt_arat)
+		__set_bit(X86_FEATURE_ARAT, c->x86_capability);
+
+	if (cpu_has(c, X86_FEATURE_EFRO)) {
+		rdmsrl(MSR_K7_HWCR, value);
+		value |= (1 << 27); /* Enable read-only APERF/MPERF bit */
+		wrmsrl(MSR_K7_HWCR, value);
+	}
+}
+
+static const struct cpu_dev hygon_cpu_dev = {
+	.c_vendor	= "Hygon",
+	.c_early_init	= early_init_amd,
+	.c_init		= init_hygon,
+};
+
+int __init hygon_init_cpu(void)
+{
+	cpu_devs[X86_VENDOR_HYGON] = &hygon_cpu_dev;
+	return 0;
+}
diff --git a/xen/include/asm-x86/x86-vendors.h b/xen/include/asm-x86/x86-vendors.h
index 774ceac..75fefcf 100644
--- a/xen/include/asm-x86/x86-vendors.h
+++ b/xen/include/asm-x86/x86-vendors.h
@@ -30,6 +30,11 @@
 #define X86_VENDOR_SHANGHAI_ECX 0x20206961U
 #define X86_VENDOR_SHANGHAI_EDX 0x68676e61U
 
-#define X86_VENDOR_NUM 5
+#define X86_VENDOR_HYGON 5
+#define X86_VENDOR_HYGON_EBX 0x6f677948 /* "HygonGenuine" */
+#define X86_VENDOR_HYGON_ECX 0x656e6975
+#define X86_VENDOR_HYGON_EDX 0x6e65476e
+
+#define X86_VENDOR_NUM 6
 
 #endif	/* __XEN_X86_VENDORS_H__ */
diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c
index 311d19e..d0b3ff7 100644
--- a/xen/lib/x86/cpuid.c
+++ b/xen/lib/x86/cpuid.c
@@ -29,6 +29,12 @@ unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx)
              edx == X86_VENDOR_SHANGHAI_EDX )
             return X86_VENDOR_SHANGHAI;
         break;
+
+    case X86_VENDOR_HYGON_EBX:
+        if ( ecx == X86_VENDOR_HYGON_ECX &&
+             edx == X86_VENDOR_HYGON_EDX )
+            return X86_VENDOR_HYGON;
+        break;
     }
 
     return X86_VENDOR_UNKNOWN;
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 02/15] x86/cpu: Fix common cpuid faulting probing for AMD and Hygon
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
  2019-04-04 13:45 ` [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
@ 2019-04-04 13:45 ` Pu Wen
  2019-04-04 13:45 ` [PATCH v5 03/15] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 Pu Wen
                   ` (15 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:45 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

There is no MSR_INTEL_PLATFORM_INFO for AMD and Hygon families. Read
this MSR will stop the Xen initialization process in some Hygon
systems or produce GPF(0). So directly return false in the function
probe_cpuid_faulting() if !cpu_has_hypervisor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/cpu/common.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 74c9426..1a095fc 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -116,6 +116,11 @@ bool __init probe_cpuid_faulting(void)
 	uint64_t val;
 	int rc;
 
+	if ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
+	     boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+	    !cpu_has_hypervisor)
+		return false;
+
 	if ((rc = rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) == 0)
 		raw_msr_policy.plaform_info.cpuid_faulting =
 			val & MSR_PLATFORM_INFO_CPUID_FAULTING;
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 03/15] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
  2019-04-04 13:45 ` [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
  2019-04-04 13:45 ` [PATCH v5 02/15] x86/cpu: Fix common cpuid faulting probing for AMD and Hygon Pu Wen
@ 2019-04-04 13:45 ` Pu Wen
  2019-04-04 13:46 ` [PATCH v5 04/15] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU Pu Wen
                   ` (14 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:45 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The Hygon Dhyana CPU supports the MSR way to get TOP_MEM2. So add Hygon
Dhyana support to print the value of TOP_MEM2.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/cpu/mtrr/generic.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index 8f9cf1b..94ee7d6 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -217,8 +217,9 @@ static void __init print_mtrr_state(const char *level)
 			printk("%s  %u disabled\n", level, i);
 	}
 
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD
-	    && boot_cpu_data.x86 >= 0xf) {
+	if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+	     boot_cpu_data.x86 >= 0xf) ||
+	     boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 		uint64_t syscfg, tom2;
 
 		rdmsrl(MSR_K8_SYSCFG, syscfg);
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 04/15] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (2 preceding siblings ...)
  2019-04-04 13:45 ` [PATCH v5 03/15] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 Pu Wen
@ 2019-04-04 13:46 ` Pu Wen
  2019-04-04 13:46 ` [PATCH v5 05/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure Pu Wen
                   ` (13 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:46 UTC (permalink / raw)
  To: xen-devel
  Cc: Wei Liu, Suravee Suthikulpanit, Pu Wen, Jan Beulich,
	Andrew Cooper, Boris Ostrovsky, Brian Woods, Roger Pau Monné

As Hygon Dhyana CPU share similar PMU architecture with AMD family
17h one, so add Hygon Dhyana support in vpmu_arch_initialise() and
vpmu_init() by sharing AMD code path.

Split the common part in amd_vpmu_init() to a static function
_vpmu_init(), making AMD and Hygon to call the shared function to
initialize vPMU.

As current vPMU still not support AMD Zen(family 17h), add 0x17 support
to amd_vpmu_init().

Also create a function hygon_vpmu_init() for Hygon vPMU initialization.

Both of AMD 17h and Hygon 18h have the same performance event select
and counter MSRs as AMD 15h has, so reuse the 15h definitions for them.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/cpu/vpmu.c     |  8 ++++++
 xen/arch/x86/cpu/vpmu_amd.c | 61 ++++++++++++++++++++++++++++++++-------------
 xen/include/asm-x86/vpmu.h  |  1 +
 3 files changed, 52 insertions(+), 18 deletions(-)

diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index 8f6daf1..375599a 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -456,6 +456,7 @@ static int vpmu_arch_initialise(struct vcpu *v)
     switch ( vendor )
     {
     case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
         ret = svm_vpmu_initialise(v);
         break;
 
@@ -876,10 +877,17 @@ static int __init vpmu_init(void)
         if ( amd_vpmu_init() )
            vpmu_mode = XENPMU_MODE_OFF;
         break;
+
+    case X86_VENDOR_HYGON:
+        if ( hygon_vpmu_init() )
+           vpmu_mode = XENPMU_MODE_OFF;
+        break;
+
     case X86_VENDOR_INTEL:
         if ( core2_vpmu_init() )
            vpmu_mode = XENPMU_MODE_OFF;
         break;
+
     default:
         printk(XENLOG_WARNING "VPMU: Unknown CPU vendor: %d. "
                "Turning VPMU off.\n", vendor);
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 5efc39b..124b7cb 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -538,28 +538,12 @@ int svm_vpmu_initialise(struct vcpu *v)
     return 0;
 }
 
-int __init amd_vpmu_init(void)
+static int __init common_init(void)
 {
     unsigned int i;
 
-    switch ( current_cpu_data.x86 )
+    if ( !num_counters )
     {
-    case 0x15:
-        num_counters = F15H_NUM_COUNTERS;
-        counters = AMD_F15H_COUNTERS;
-        ctrls = AMD_F15H_CTRLS;
-        k7_counters_mirrored = 1;
-        break;
-    case 0x10:
-    case 0x12:
-    case 0x14:
-    case 0x16:
-        num_counters = F10H_NUM_COUNTERS;
-        counters = AMD_F10H_COUNTERS;
-        ctrls = AMD_F10H_CTRLS;
-        k7_counters_mirrored = 0;
-        break;
-    default:
         printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n",
                current_cpu_data.x86);
         return -EINVAL;
@@ -586,3 +570,44 @@ int __init amd_vpmu_init(void)
     return 0;
 }
 
+int __init amd_vpmu_init(void)
+{
+    switch ( current_cpu_data.x86 )
+    {
+    case 0x15:
+    case 0x17:
+        num_counters = F15H_NUM_COUNTERS;
+        counters = AMD_F15H_COUNTERS;
+        ctrls = AMD_F15H_CTRLS;
+        k7_counters_mirrored = 1;
+        break;
+
+    case 0x10:
+    case 0x12:
+    case 0x14:
+    case 0x16:
+        num_counters = F10H_NUM_COUNTERS;
+        counters = AMD_F10H_COUNTERS;
+        ctrls = AMD_F10H_CTRLS;
+        k7_counters_mirrored = 0;
+        break;
+    }
+
+    return common_init();
+}
+
+int __init hygon_vpmu_init(void)
+{
+    switch ( current_cpu_data.x86 )
+    {
+    case 0x18:
+        num_counters = F15H_NUM_COUNTERS;
+        counters = AMD_F15H_COUNTERS;
+        ctrls = AMD_F15H_CTRLS;
+        k7_counters_mirrored = 1;
+        break;
+    }
+
+    return common_init();
+}
+
diff --git a/xen/include/asm-x86/vpmu.h b/xen/include/asm-x86/vpmu.h
index 1287b9f..55f85ba 100644
--- a/xen/include/asm-x86/vpmu.h
+++ b/xen/include/asm-x86/vpmu.h
@@ -52,6 +52,7 @@ struct arch_vpmu_ops {
 int core2_vpmu_init(void);
 int vmx_vpmu_initialise(struct vcpu *);
 int amd_vpmu_init(void);
+int hygon_vpmu_init(void);
 int svm_vpmu_initialise(struct vcpu *);
 
 struct vpmu_struct {
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 05/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (3 preceding siblings ...)
  2019-04-04 13:46 ` [PATCH v5 04/15] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU Pu Wen
@ 2019-04-04 13:46 ` Pu Wen
  2019-04-04 13:46 ` [PATCH v5 06/15] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery Pu Wen
                   ` (12 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:46 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/cpu/common.c              | 3 ++-
 xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 5 +++--
 xen/arch/x86/cpu/mcheck/mce.c          | 6 ++++--
 xen/arch/x86/cpu/mcheck/mce_amd.c      | 5 ++++-
 xen/arch/x86/cpu/mcheck/non-fatal.c    | 3 ++-
 xen/arch/x86/cpu/mcheck/vmce.c         | 2 ++
 6 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 1a095fc..c14ff1b 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -326,7 +326,8 @@ static void __init early_cpu_detect(void)
 			hap_paddr_bits = PADDR_BITS;
 	}
 
-	if (c->x86_vendor != X86_VENDOR_AMD)
+	if (c->x86_vendor != X86_VENDOR_AMD &&
+	    c->x86_vendor != X86_VENDOR_HYGON)
 		park_offline_cpus = opt_mce;
 
 	initialize_cpu_data(0);
diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
index 222f539..589dac5 100644
--- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
+++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
@@ -203,10 +203,11 @@ static void mce_amd_work_fn(void *data)
 
 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c)
 {
-	if (c->x86_vendor != X86_VENDOR_AMD)
+	if (c->x86_vendor != X86_VENDOR_AMD &&
+	    c->x86_vendor != X86_VENDOR_HYGON)
 		return;
 
-	/* Assume we are on K8 or newer AMD CPU here */
+	/* Assume we are on K8 or newer AMD or Hygon CPU here */
 
 	/* The threshold bitfields in MSR_IA32_MC4_MISC has
 	 * been introduced along with the SVME feature bit. */
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index 30cdb06..0798dea 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -778,6 +778,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp)
     switch ( c->x86_vendor )
     {
     case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
         inited = amd_mcheck_init(c);
         break;
 
@@ -1172,10 +1173,11 @@ static bool x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
 
             /* MSRs that the HV will take care of */
             case MSR_K8_HWCR:
-                if ( c->x86_vendor == X86_VENDOR_AMD )
+                if ( c->x86_vendor == X86_VENDOR_AMD ||
+                     c->x86_vendor == X86_VENDOR_HYGON )
                     reason = "HV will operate HWCR";
                 else
-                    reason = "only supported on AMD";
+                    reason = "only supported on AMD or Hygon";
                 break;
 
             default:
diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c
index ed29fcc..8ed2b17 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -286,7 +286,10 @@ enum mcheck_type
 amd_mcheck_init(struct cpuinfo_x86 *ci)
 {
     uint32_t i;
-    enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(ci);
+    enum mcequirk_amd_flags quirkflag = 0;
+
+    if (ci->x86_vendor != X86_VENDOR_HYGON)
+        quirkflag = mcequirk_lookup_amd_quirkdata(ci);
 
     /* Assume that machine check support is available.
      * The minimum provided support is at least the K8. */
diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c
index d12e8f2..77be418 100644
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c
@@ -101,7 +101,8 @@ static int __init init_nonfatal_mce_checker(void)
 	 */
 	switch (c->x86_vendor) {
 	case X86_VENDOR_AMD:
-		/* Assume we are on K8 or newer AMD CPU here */
+	case X86_VENDOR_HYGON:
+		/* Assume we are on K8 or newer AMD or Hygon CPU here */
 		amd_nonfatal_mcheck_init(c);
 		break;
 
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index f15835e..4f5de07 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -154,6 +154,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
             break;
 
         case X86_VENDOR_AMD:
+        case X86_VENDOR_HYGON:
             ret = vmce_amd_rdmsr(v, msr, val);
             break;
 
@@ -284,6 +285,7 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
             break;
 
         case X86_VENDOR_AMD:
+        case X86_VENDOR_HYGON:
             ret = vmce_amd_wrmsr(v, msr, val);
             break;
 
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 06/15] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (4 preceding siblings ...)
  2019-04-04 13:46 ` [PATCH v5 05/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure Pu Wen
@ 2019-04-04 13:46 ` Pu Wen
  2019-04-04 13:46 ` [PATCH v5 07/15] x86/apic: Add Hygon Dhyana support Pu Wen
                   ` (11 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:46 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The Hygon Dhyana CPU has the same speculative execution as AMD family
17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/spec_ctrl.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 1171c02..1cd7903 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -306,7 +306,8 @@ static bool __init retpoline_safe(uint64_t caps)
 {
     unsigned int ucode_rev = this_cpu(ucode_cpu_info).cpu_sig.rev;
 
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+         boot_cpu_data.x86_vendor == X86_VENDOR_HYGON )
         return true;
 
     if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
@@ -632,7 +633,8 @@ int8_t __read_mostly opt_xpti_domu = -1;
 
 static __init void xpti_init_default(uint64_t caps)
 {
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+         boot_cpu_data.x86_vendor == X86_VENDOR_HYGON )
         caps = ARCH_CAPS_RDCL_NO;
 
     if ( caps & ARCH_CAPS_RDCL_NO )
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 07/15] x86/apic: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (5 preceding siblings ...)
  2019-04-04 13:46 ` [PATCH v5 06/15] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery Pu Wen
@ 2019-04-04 13:46 ` Pu Wen
  2019-04-04 13:46 ` [PATCH v5 08/15] x86/acpi: " Pu Wen
                   ` (10 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:46 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

Add Hygon Dhyana support to use modern APIC.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/apic.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index e6130cf..65228cb 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -92,6 +92,11 @@ static int modern_apic(void)
     if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
         boot_cpu_data.x86 >= 0xf)
         return 1;
+
+    /* Hygon systems use modern APIC */
+    if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+        return 1;
+
     lvr = apic_read(APIC_LVR);
     version = GET_APIC_VERSION(lvr);
     return version >= 0x14;
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 08/15] x86/acpi: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (6 preceding siblings ...)
  2019-04-04 13:46 ` [PATCH v5 07/15] x86/apic: Add Hygon Dhyana support Pu Wen
@ 2019-04-04 13:46 ` Pu Wen
  2019-04-04 13:47 ` [PATCH v5 09/15] x86/iommu: " Pu Wen
                   ` (9 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:46 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

Add Hygon Dhyana support to the acpi cpufreq and cpuidle subsystems by
using the code path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/acpi/cpu_idle.c         | 3 ++-
 xen/arch/x86/acpi/cpufreq/cpufreq.c  | 8 +++++---
 xen/arch/x86/acpi/cpufreq/powernow.c | 3 ++-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 654de24..02e4873 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -796,7 +796,8 @@ void acpi_dead_idle(void)
             __mwait(cx->address, 0);
         }
     }
-    else if ( current_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+    else if ( (current_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+               current_cpu_data.x86_vendor == X86_VENDOR_HYGON) &&
               cx->entry_method == ACPI_CSTATE_EM_SYSIO )
     {
         /* Intel prefers not to use SYSIO */
diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index 844ab85..14c18bd 100644
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -649,7 +649,8 @@ static int __init cpufreq_driver_init(void)
         (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL))
         ret = cpufreq_register_driver(&acpi_cpufreq_driver);
     else if ((cpufreq_controller == FREQCTL_xen) &&
-        (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
+        (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+         boot_cpu_data.x86_vendor == X86_VENDOR_HYGON))
         ret = powernow_register_driver();
 
     return ret;
@@ -660,9 +661,10 @@ int cpufreq_cpu_init(unsigned int cpuid)
 {
     int ret;
 
-    /* Currently we only handle Intel and AMD processor */
+    /* Currently we only handle Intel, AMD and Hygon processor */
     if ( (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) ||
-         (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) )
+         (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) ||
+         (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ) )
         ret = cpufreq_add_cpu(cpuid);
     else
         ret = -EFAULT;
diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufreq/powernow.c
index 025b37d..f245908 100644
--- a/xen/arch/x86/acpi/cpufreq/powernow.c
+++ b/xen/arch/x86/acpi/cpufreq/powernow.c
@@ -360,7 +360,8 @@ unsigned int __init powernow_register_driver()
 
     for_each_online_cpu(i) {
         struct cpuinfo_x86 *c = &cpu_data[i];
-        if (c->x86_vendor != X86_VENDOR_AMD)
+        if (c->x86_vendor != X86_VENDOR_AMD &&
+            c->x86_vendor != X86_VENDOR_HYGON)
             ret = -ENODEV;
         else
         {
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 09/15] x86/iommu: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (7 preceding siblings ...)
  2019-04-04 13:46 ` [PATCH v5 08/15] x86/acpi: " Pu Wen
@ 2019-04-04 13:47 ` Pu Wen
  2019-04-04 13:47 ` [PATCH v5 10/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access Pu Wen
                   ` (8 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:47 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The IOMMU architecture for the Hygon Dhyana CPU is similar to the AMD
family 17h one. So add Hygon Dhyana support to it by sharing the code
path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/include/asm-x86/iommu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/include/asm-x86/iommu.h b/xen/include/asm-x86/iommu.h
index 8dc3924..699a8f7 100644
--- a/xen/include/asm-x86/iommu.h
+++ b/xen/include/asm-x86/iommu.h
@@ -74,6 +74,7 @@ static inline int iommu_hardware_setup(void)
     case X86_VENDOR_INTEL:
         return intel_vtd_setup();
     case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
         return amd_iov_detect();
     }
 
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 10/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (8 preceding siblings ...)
  2019-04-04 13:47 ` [PATCH v5 09/15] x86/iommu: " Pu Wen
@ 2019-04-04 13:47 ` Pu Wen
  2019-04-04 13:47 ` [PATCH v5 11/15] x86/domain: Add Hygon Dhyana support Pu Wen
                   ` (7 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:47 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
counter MSRs, hardware configuration MSR, MMIO configuration base address
MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
PV emulation infrastructure by using the code path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/pv/emul-priv-op.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 84ce67c..4f73375 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -924,7 +924,9 @@ static int read_msr(unsigned int reg, uint64_t *val,
             /* fall through */
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+            if ( vpmu_msr ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
             {
                 if ( vpmu_do_rdmsr(reg, val) )
                     break;
@@ -1006,7 +1008,8 @@ static int write_msr(unsigned int reg, uint64_t val,
     case MSR_K8_PSTATE6:
     case MSR_K8_PSTATE7:
     case MSR_K8_HWCR:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
              wrmsr_safe(reg, val) == 0 )
@@ -1027,8 +1030,9 @@ static int write_msr(unsigned int reg, uint64_t val,
         break;
 
     case MSR_FAM10H_MMIO_CONF_BASE:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
+        if ( (boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+              boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17) &&
+              boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
@@ -1067,7 +1071,8 @@ static int write_msr(unsigned int reg, uint64_t val,
     case MSR_IA32_MPERF:
     case MSR_IA32_APERF:
         if ( (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) &&
-             (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) )
+             (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) &&
+             (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
              wrmsr_safe(reg, val) == 0 )
@@ -1099,7 +1104,9 @@ static int write_msr(unsigned int reg, uint64_t val,
             vpmu_msr = true;
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+            if ( vpmu_msr ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
             {
                 if ( (vpmu_mode & XENPMU_MODE_ALL) &&
                      !is_hardware_domain(currd) )
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 11/15] x86/domain: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (9 preceding siblings ...)
  2019-04-04 13:47 ` [PATCH v5 10/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access Pu Wen
@ 2019-04-04 13:47 ` Pu Wen
  2019-04-04 13:47 ` [PATCH v5 12/15] x86/domctl: " Pu Wen
                   ` (6 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:47 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

Add Hygon Dhyana support to handle HyperTransport range.

Also loading a nul selector does not clear bases and limits on Hygon
CPUs, so add Hygon Dhyana support to the function preload_segment.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/dom0_build.c | 3 ++-
 xen/arch/x86/domain.c     | 9 +++++----
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 73f5407..4a36b63 100644
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -542,7 +542,8 @@ int __init dom0_setup_permissions(struct domain *d)
                             paddr_to_pfn(MSI_ADDR_BASE_LO +
                                          MSI_ADDR_DEST_ID_MASK));
     /* HyperTransport range. */
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+         boot_cpu_data.x86_vendor == X86_VENDOR_HYGON )
         rc |= iomem_deny_access(d, paddr_to_pfn(0xfdULL << 32),
                                 paddr_to_pfn((1ULL << 40) - 1));
 
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 20b86fd..c9a7964 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1253,13 +1253,14 @@ arch_do_vcpu_op(
 }
 
 /*
- * Loading a nul selector does not clear bases and limits on AMD CPUs. Be on
- * the safe side and re-initialize both to flat segment values before loading
- * a nul selector.
+ * Loading a nul selector does not clear bases and limits on AMD or Hygon
+ * CPUs. Be on the safe side and re-initialize both to flat segment values
+ * before loading a nul selector.
  */
 #define preload_segment(seg, value) do {              \
     if ( !((value) & ~3) &&                           \
-         boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) \
+        (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || \
+         boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) ) \
         asm volatile ( "movl %k0, %%" #seg            \
                        :: "r" (FLAT_USER_DS32) );     \
 } while ( false )
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 12/15] x86/domctl: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (10 preceding siblings ...)
  2019-04-04 13:47 ` [PATCH v5 11/15] x86/domain: Add Hygon Dhyana support Pu Wen
@ 2019-04-04 13:47 ` Pu Wen
  2019-04-04 13:47 ` [PATCH v5 13/15] x86/traps: " Pu Wen
                   ` (5 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:47 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

Add Hygon Dhyana support to update cpuid info for creating PV guest.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/domctl.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 9bf2d08..19b7bdd 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -176,6 +176,7 @@ static int update_domain_cpuid_info(struct domain *d,
                 break;
 
             case X86_VENDOR_AMD:
+            case X86_VENDOR_HYGON:
                 mask &= ((uint64_t)ecx << 32) | edx;
 
                 /*
@@ -220,7 +221,8 @@ static int update_domain_cpuid_info(struct domain *d,
             uint32_t eax = ctl->eax;
             uint32_t ebx = p->feat._7b0;
 
-            if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+            if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+                 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON )
                 mask &= ((uint64_t)eax << 32) | ebx;
 
             d->arch.pv.cpuidmasks->_7ab0 = mask;
@@ -281,8 +283,12 @@ static int update_domain_cpuid_info(struct domain *d,
             if ( cpu_has_cmp_legacy )
                 ecx |= cpufeat_mask(X86_FEATURE_CMP_LEGACY);
 
-            /* If not emulating AMD, clear the duplicated features in e1d. */
-            if ( p->x86_vendor != X86_VENDOR_AMD )
+            /*
+             * If not emulating AMD or Hygon, clear the duplicated features
+             * in e1d.
+             */
+            if ( p->x86_vendor != X86_VENDOR_AMD &&
+                 p->x86_vendor != X86_VENDOR_HYGON )
                 edx &= ~CPUID_COMMON_1D_FEATURES;
 
             switch ( boot_cpu_data.x86_vendor )
@@ -292,6 +298,7 @@ static int update_domain_cpuid_info(struct domain *d,
                 break;
 
             case X86_VENDOR_AMD:
+            case X86_VENDOR_HYGON:
                 mask &= ((uint64_t)ecx << 32) | edx;
 
                 /*
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 13/15] x86/traps: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (11 preceding siblings ...)
  2019-04-04 13:47 ` [PATCH v5 12/15] x86/domctl: " Pu Wen
@ 2019-04-04 13:47 ` Pu Wen
  2019-04-04 13:48 ` [PATCH v5 14/15] x86/cpuid: " Pu Wen
                   ` (4 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:47 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR0000_01DD. So add support for it if the boot param
ler is true.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/traps.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 05ddc39..97bf9e2 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,9 @@ static unsigned int calc_ler_msr(void)
             return MSR_IA32_LASTINTFROMIP;
         }
         break;
+
+    case X86_VENDOR_HYGON:
+        return MSR_IA32_LASTINTFROMIP;
     }
 
     return 0;
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 14/15] x86/cpuid: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (12 preceding siblings ...)
  2019-04-04 13:47 ` [PATCH v5 13/15] x86/traps: " Pu Wen
@ 2019-04-04 13:48 ` Pu Wen
  2019-04-04 13:48 ` [PATCH v5 15/15] tools/libxc: " Pu Wen
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:48 UTC (permalink / raw)
  To: xen-devel
  Cc: Pu Wen, Roger Pau Monné, Wei Liu, Jan Beulich, Andrew Cooper

The Hygon Dhyana family 18h processor shares the same cpuid leaves as
the AMD family 17h one. So add Hygon Dhyana support to caculate the
cpuid policies as the AMD CPU does.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/cpuid.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index cb170ac..a3fb770 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -240,6 +240,7 @@ static void recalculate_misc(struct cpuid_policy *p)
         break;
 
     case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
         zero_leaves(p->basic.raw, 0x2, 0x3);
         memset(p->cache.raw, 0, sizeof(p->cache.raw));
         zero_leaves(p->basic.raw, 0x9, 0xa);
@@ -391,7 +392,8 @@ static void __init calculate_hvm_max_policy(void)
      * long mode (and init_amd() has cleared it out of host capabilities), but
      * HVM guests are able if running in protected mode.
      */
-    if ( (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+    if ( (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+          boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) &&
          raw_cpuid_policy.basic.sep )
         __set_bit(X86_FEATURE_SEP, hvm_featureset);
 
@@ -466,7 +468,8 @@ void recalculate_cpuid_policy(struct domain *d)
     p->basic.max_leaf   = min(p->basic.max_leaf,   max->basic.max_leaf);
     p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf);
     p->extd.max_leaf    = 0x80000000 | min(p->extd.max_leaf & 0xffff,
-                                           (p->x86_vendor == X86_VENDOR_AMD
+                                          ((p->x86_vendor == X86_VENDOR_AMD ||
+                                            p->x86_vendor == X86_VENDOR_HYGON)
                                             ? CPUID_GUEST_NR_EXTD_AMD
                                             : CPUID_GUEST_NR_EXTD_INTEL) - 1);
 
@@ -508,7 +511,8 @@ void recalculate_cpuid_policy(struct domain *d)
     if ( is_pv_32bit_domain(d) )
     {
         __clear_bit(X86_FEATURE_LM, max_fs);
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             __clear_bit(X86_FEATURE_SYSCALL, max_fs);
     }
 
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [PATCH v5 15/15] tools/libxc: Add Hygon Dhyana support
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (13 preceding siblings ...)
  2019-04-04 13:48 ` [PATCH v5 14/15] x86/cpuid: " Pu Wen
@ 2019-04-04 13:48 ` Pu Wen
  2019-04-04 16:26   ` Wei Liu
  2019-04-04 13:53 ` [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Julien Grall
                   ` (2 subsequent siblings)
  17 siblings, 1 reply; 37+ messages in thread
From: Pu Wen @ 2019-04-04 13:48 UTC (permalink / raw)
  To: xen-devel; +Cc: Pu Wen, Ian Jackson, Wei Liu, Jan Beulich, Andrew Cooper

Add Hygon Dhyana support to caculate the cpuid policies for creating PV
or HVM guest by using the code path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 tools/libxc/xc_cpuid_x86.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 71e1ee7..e5afa55 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -556,7 +556,8 @@ static void xc_cpuid_hvm_policy(const struct cpuid_domain_info *info,
         break;
     }
 
-    if ( info->vendor == X86_VENDOR_AMD )
+    if ( info->vendor == X86_VENDOR_AMD ||
+         info->vendor == X86_VENDOR_HYGON )
         amd_xc_cpuid_policy(info, input, regs);
     else
         intel_xc_cpuid_policy(info, input, regs);
@@ -618,7 +619,8 @@ static void xc_cpuid_pv_policy(const struct cpuid_domain_info *info,
 
     case 0x80000000:
     {
-        unsigned int max = info->vendor == X86_VENDOR_AMD
+        unsigned int max = (info->vendor == X86_VENDOR_AMD ||
+                            info->vendor == X86_VENDOR_HYGON)
             ? DEF_MAX_AMDEXT : DEF_MAX_INTELEXT;
 
         if ( regs[0] > max )
@@ -724,7 +726,8 @@ static void sanitise_featureset(struct cpuid_domain_info *info)
         if ( !info->pv64 )
         {
             clear_bit(X86_FEATURE_LM, info->featureset);
-            if ( info->vendor != X86_VENDOR_AMD )
+            if ( info->vendor != X86_VENDOR_AMD &&
+                 info->vendor != X86_VENDOR_HYGON )
                 clear_bit(X86_FEATURE_SYSCALL, info->featureset);
         }
 
@@ -775,7 +778,7 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid,
     input[0] = 0x80000000;
     cpuid(input, regs);
 
-    if ( info.vendor == X86_VENDOR_AMD )
+    if ( info.vendor == X86_VENDOR_AMD || info.vendor == X86_VENDOR_HYGON )
         ext_max = (regs[0] <= DEF_MAX_AMDEXT) ? regs[0] : DEF_MAX_AMDEXT;
     else
         ext_max = (regs[0] <= DEF_MAX_INTELEXT) ? regs[0] : DEF_MAX_INTELEXT;
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (14 preceding siblings ...)
  2019-04-04 13:48 ` [PATCH v5 15/15] tools/libxc: " Pu Wen
@ 2019-04-04 13:53 ` Julien Grall
  2019-04-04 16:47   ` Pu Wen
  2019-06-06 16:31 ` [Xen-devel] " Andrew Cooper
       [not found] ` <201906070115.x571Fd9j014046@spam1.hygon.cn>
  17 siblings, 1 reply; 37+ messages in thread
From: Julien Grall @ 2019-04-04 13:53 UTC (permalink / raw)
  To: Pu Wen, xen-devel
  Cc: Stefano Stabellini, Wei Liu, Suravee Suthikulpanit,
	Konrad Rzeszutek Wilk, George Dunlap, Andrew Cooper, Ian Jackson,
	Tim Deegan, Jan Beulich, Boris Ostrovsky, Brian Woods,
	Roger Pau Monné

Hi,

I am not sure why I end up to be CCed on the cover letter when I am not CCed on 
the rest of series.

Cheers,

On 04/04/2019 14:44, Pu Wen wrote:
> As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon)
> is a joint venture between AMD and Haiguang Information Technology Co.,
> Ltd., aims at providing high performance x86 processors for China
> server market.
> 
> The first generation Hygon processor(Dhyana) originates from AMD
> technology and shares most of the architecture with AMD's family 17h,
> but with different CPU vendor ID("HygonGenuine") and family series
> number 18h (Hygon negotiated with AMD to make sure that only Hygon
> will use family 18h).
> 
> To enable support of Xen to Hygon Dhyana CPU, add a new vendor type
> (X86_VENDOR_HYGON, with value of 5), and share most of the code with
> AMD family 17h.
> 
> The MSRs and CPUIDs which are used by this patch series are all defined
> in this PPR[1].
> 
> This patch series have been applied and tested successfully on Hygon
> Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
> It works fine and makes no harm to the existing code.
> 
> Reference:
> [1] https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
> 
> 
> v4->v5:
>    - Rebased over https://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=0763cd26
>      to fit the new x86 vendor lookup mechanism.
>    - Rework patch 15/15 to fit the new x86 vendor lookup mechanism.
>    - Add Acked-by from Jan Beulich for patch 02/15 and 04/15.
>    - Retain more conditionals from amd.c.
>    - Refine coding style.
> 
> v3->v4:
>    - Revert opt_cpuid_mask_l7s0_(eax/ebx) to amd.c.
>    - Create a separate patch to fix common cpuid faulting probing issue
>      for AMD and Hygon.
>    - Rename _vpmu_init() to common_init() and move the default case into it.
>    - Coding style refine.
> 
> v2->v3:
>    - Rebased on 4.13-unstable and tested against it.
>    - Simplify code of hygon.c by re-using early_init_amd().
>    - Return false in the function probe_cpuid_faulting().
>    - Adjust code for calculating phys_proc_id for Hygon.
>    - Abstract common function _vpmu_init() and add hygon_vpmu_init().
>    - Refine some comments and descriptions.
>    - Add Acked-by from Jan Beulich for x86/cpu/mtrr, x86/cpu/mce,
>      x86/spec_ctrl, x86/apic, x86/acpi, x86/iommu, x86/pv, x86/domain,
>      x86/domctl and x86/cpuid.
> 
> v1->v2:
>    - Rebased on 4.12.0-rc3 and tested against it.
>    - Move opt_cpuid_mask_l7s0_(eax/ebx) to common.c.
>    - Insert Hygon cases after AMD ones instead of above.
>    - Remove (rd/wr)msr_hygon_safe and use (rd/wr)msr_safe instead.
>    - Remove wrmsr_hygon and use wrmsrl instead.
>    - Remove the unnecessary change to xstate.
>    - Refine some codes and comments.
>    - Add Acked-by from Jan Beulich for x86/traps.
>    - Add Acked-by from Wei Liu for tools/libxc.
> 
> 
> Pu Wen (15):
>    x86/cpu: Create Hygon Dhyana architecture support file
>    x86/cpu: Fix common cpuid faulting probing for AMD and Hygon
>    x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2
>    x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU
>    x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure
>    x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery
>    x86/apic: Add Hygon Dhyana support
>    x86/acpi: Add Hygon Dhyana support
>    x86/iommu: Add Hygon Dhyana support
>    x86/pv: Add Hygon Dhyana support to emulate MSRs access
>    x86/domain: Add Hygon Dhyana support
>    x86/domctl: Add Hygon Dhyana support
>    x86/traps: Add Hygon Dhyana support
>    x86/cpuid: Add Hygon Dhyana support
>    tools/libxc: Add Hygon Dhyana support
> 
>   tools/libxc/xc_cpuid_x86.c             |  11 ++--
>   xen/arch/x86/acpi/cpu_idle.c           |   3 +-
>   xen/arch/x86/acpi/cpufreq/cpufreq.c    |   8 ++-
>   xen/arch/x86/acpi/cpufreq/powernow.c   |   3 +-
>   xen/arch/x86/apic.c                    |   5 ++
>   xen/arch/x86/cpu/Makefile              |   1 +
>   xen/arch/x86/cpu/amd.c                 |   2 +-
>   xen/arch/x86/cpu/common.c              |   9 ++-
>   xen/arch/x86/cpu/cpu.h                 |   3 +
>   xen/arch/x86/cpu/hygon.c               | 114 +++++++++++++++++++++++++++++++++
>   xen/arch/x86/cpu/mcheck/amd_nonfatal.c |   5 +-
>   xen/arch/x86/cpu/mcheck/mce.c          |   6 +-
>   xen/arch/x86/cpu/mcheck/mce_amd.c      |   5 +-
>   xen/arch/x86/cpu/mcheck/non-fatal.c    |   3 +-
>   xen/arch/x86/cpu/mcheck/vmce.c         |   2 +
>   xen/arch/x86/cpu/mtrr/generic.c        |   5 +-
>   xen/arch/x86/cpu/vpmu.c                |   8 +++
>   xen/arch/x86/cpu/vpmu_amd.c            |  61 ++++++++++++------
>   xen/arch/x86/cpuid.c                   |  10 ++-
>   xen/arch/x86/dom0_build.c              |   3 +-
>   xen/arch/x86/domain.c                  |   9 +--
>   xen/arch/x86/domctl.c                  |  13 +++-
>   xen/arch/x86/pv/emul-priv-op.c         |  19 ++++--
>   xen/arch/x86/spec_ctrl.c               |   6 +-
>   xen/arch/x86/traps.c                   |   3 +
>   xen/include/asm-x86/iommu.h            |   1 +
>   xen/include/asm-x86/vpmu.h             |   1 +
>   xen/include/asm-x86/x86-vendors.h      |   7 +-
>   xen/lib/x86/cpuid.c                    |   6 ++
>   29 files changed, 275 insertions(+), 57 deletions(-)
>   create mode 100644 xen/arch/x86/cpu/hygon.c
> 

-- 
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
  2019-04-04 13:45 ` [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
@ 2019-04-04 14:02   ` Andrew Cooper
  2019-04-04 16:39     ` Pu Wen
  0 siblings, 1 reply; 37+ messages in thread
From: Andrew Cooper @ 2019-04-04 14:02 UTC (permalink / raw)
  To: Pu Wen, xen-devel
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Tim Deegan, Ian Jackson, Julien Grall,
	Jan Beulich, Roger Pau Monné

On 04/04/2019 14:45, Pu Wen wrote:
> index 774ceac..75fefcf 100644
> --- a/xen/include/asm-x86/x86-vendors.h
> +++ b/xen/include/asm-x86/x86-vendors.h
> @@ -30,6 +30,11 @@
>  #define X86_VENDOR_SHANGHAI_ECX 0x20206961U
>  #define X86_VENDOR_SHANGHAI_EDX 0x68676e61U
>  
> -#define X86_VENDOR_NUM 5
> +#define X86_VENDOR_HYGON 5
> +#define X86_VENDOR_HYGON_EBX 0x6f677948 /* "HygonGenuine" */
> +#define X86_VENDOR_HYGON_ECX 0x656e6975
> +#define X86_VENDOR_HYGON_EDX 0x6e65476e
> +
> +#define X86_VENDOR_NUM 6
>  
>  #endif	/* __XEN_X86_VENDORS_H__ */
> diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c
> index 311d19e..d0b3ff7 100644
> --- a/xen/lib/x86/cpuid.c
> +++ b/xen/lib/x86/cpuid.c
> @@ -29,6 +29,12 @@ unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx)
>               edx == X86_VENDOR_SHANGHAI_EDX )
>              return X86_VENDOR_SHANGHAI;
>          break;
> +
> +    case X86_VENDOR_HYGON_EBX:
> +        if ( ecx == X86_VENDOR_HYGON_ECX &&
> +             edx == X86_VENDOR_HYGON_EDX )
> +            return X86_VENDOR_HYGON;
> +        break;
>      }
>  
>      return X86_VENDOR_UNKNOWN;

This needs the following hunk folding in

diff --git a/tools/tests/cpu-policy/test-cpu-policy.c
b/tools/tests/cpu-policy/test-cpu-policy.c
index beced5e..88f5121 100644
--- a/tools/tests/cpu-policy/test-cpu-policy.c
+++ b/tools/tests/cpu-policy/test-cpu-policy.c
@@ -35,6 +35,7 @@ static void test_vendor_identification(void)
         { { "AuthenticAMD" }, X86_VENDOR_AMD },
         { { "CentaurHauls" }, X86_VENDOR_CENTAUR },
         { { "  Shanghai  " }, X86_VENDOR_SHANGHAI },
+        { { "HygonGenuine" }, X86_VENDOR_HYGON },
 
         { { ""             }, X86_VENDOR_UNKNOWN },
         { { "            " }, X86_VENDOR_UNKNOWN },

which can be done on commit to avoid sending yet another version.

~Andrew

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 15/15] tools/libxc: Add Hygon Dhyana support
  2019-04-04 13:48 ` [PATCH v5 15/15] tools/libxc: " Pu Wen
@ 2019-04-04 16:26   ` Wei Liu
  2019-04-04 16:40     ` Pu Wen
  0 siblings, 1 reply; 37+ messages in thread
From: Wei Liu @ 2019-04-04 16:26 UTC (permalink / raw)
  To: Pu Wen; +Cc: xen-devel, Ian Jackson, Wei Liu, Jan Beulich, Andrew Cooper

On Thu, Apr 04, 2019 at 09:48:13PM +0800, Pu Wen wrote:
> Add Hygon Dhyana support to caculate the cpuid policies for creating PV
> or HVM guest by using the code path of AMD.
> 
> Signed-off-by: Pu Wen <puwen@hygon.cn>

Acked-by: Wei Liu <wei.liu2@citrix.com>

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
  2019-04-04 14:02   ` Andrew Cooper
@ 2019-04-04 16:39     ` Pu Wen
  2019-04-05  7:49         ` [Xen-devel] " Jan Beulich
  0 siblings, 1 reply; 37+ messages in thread
From: Pu Wen @ 2019-04-04 16:39 UTC (permalink / raw)
  To: Andrew Cooper, xen-devel
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Tim Deegan, Ian Jackson, Julien Grall,
	Jan Beulich, Roger Pau Monné

On 2019/4/4 22:07, Andrew Cooper wrote:
> On 04/04/2019 14:45, Pu Wen wrote:
>> index 774ceac..75fefcf 100644
>> --- a/xen/include/asm-x86/x86-vendors.h
>> +++ b/xen/include/asm-x86/x86-vendors.h
>> @@ -30,6 +30,11 @@
>>   #define X86_VENDOR_SHANGHAI_ECX 0x20206961U
>>   #define X86_VENDOR_SHANGHAI_EDX 0x68676e61U
>>   
>> -#define X86_VENDOR_NUM 5
>> +#define X86_VENDOR_HYGON 5
>> +#define X86_VENDOR_HYGON_EBX 0x6f677948 /* "HygonGenuine" */
>> +#define X86_VENDOR_HYGON_ECX 0x656e6975
>> +#define X86_VENDOR_HYGON_EDX 0x6e65476e
>> +
>> +#define X86_VENDOR_NUM 6
>>   
>>   #endif	/* __XEN_X86_VENDORS_H__ */
>> diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c
>> index 311d19e..d0b3ff7 100644
>> --- a/xen/lib/x86/cpuid.c
>> +++ b/xen/lib/x86/cpuid.c
>> @@ -29,6 +29,12 @@ unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx)
>>                edx == X86_VENDOR_SHANGHAI_EDX )
>>               return X86_VENDOR_SHANGHAI;
>>           break;
>> +
>> +    case X86_VENDOR_HYGON_EBX:
>> +        if ( ecx == X86_VENDOR_HYGON_ECX &&
>> +             edx == X86_VENDOR_HYGON_EDX )
>> +            return X86_VENDOR_HYGON;
>> +        break;
>>       }
>>   
>>       return X86_VENDOR_UNKNOWN;
> 
> This needs the following hunk folding in
> 
> diff --git a/tools/tests/cpu-policy/test-cpu-policy.c
> b/tools/tests/cpu-policy/test-cpu-policy.c
> index beced5e..88f5121 100644
> --- a/tools/tests/cpu-policy/test-cpu-policy.c
> +++ b/tools/tests/cpu-policy/test-cpu-policy.c
> @@ -35,6 +35,7 @@ static void test_vendor_identification(void)
>           { { "AuthenticAMD" }, X86_VENDOR_AMD },
>           { { "CentaurHauls" }, X86_VENDOR_CENTAUR },
>           { { "  Shanghai  " }, X86_VENDOR_SHANGHAI },
> +        { { "HygonGenuine" }, X86_VENDOR_HYGON },
>   
>           { { ""             }, X86_VENDOR_UNKNOWN },
>           { { "            " }, X86_VENDOR_UNKNOWN },

I'm sorry for missing this file.

> which can be done on commit to avoid sending yet another version.

Do you mean I need to send a individual patch for this file instead of 
reworking the whole series?

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 15/15] tools/libxc: Add Hygon Dhyana support
  2019-04-04 16:26   ` Wei Liu
@ 2019-04-04 16:40     ` Pu Wen
  0 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-04 16:40 UTC (permalink / raw)
  To: Wei Liu; +Cc: xen-devel, Ian Jackson, Jan Beulich, Andrew Cooper

On 2019/4/5 0:38, Wei Liu wrote:
> On Thu, Apr 04, 2019 at 09:48:13PM +0800, Pu Wen wrote:
>> Add Hygon Dhyana support to caculate the cpuid policies for creating PV
>> or HVM guest by using the code path of AMD.
>>
>> Signed-off-by: Pu Wen <puwen@hygon.cn>
> 
> Acked-by: Wei Liu <wei.liu2@citrix.com>

Thanks.

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
  2019-04-04 13:53 ` [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Julien Grall
@ 2019-04-04 16:47   ` Pu Wen
  2019-04-04 17:00     ` Julien Grall
  0 siblings, 1 reply; 37+ messages in thread
From: Pu Wen @ 2019-04-04 16:47 UTC (permalink / raw)
  To: Julien Grall, xen-devel
  Cc: Stefano Stabellini, Wei Liu, Suravee Suthikulpanit,
	Konrad Rzeszutek Wilk, George Dunlap, Andrew Cooper, Ian Jackson,
	Tim Deegan, Jan Beulich, Boris Ostrovsky, Brian Woods,
	Roger Pau Monné

On 2019/4/4 22:08, Julien Grall wrote:
> Hi,
> 
> I am not sure why I end up to be CCed on the cover letter when I am not CCed on
> the rest of series.

The patch 01/15 of the series is CCed to you. :)

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
  2019-04-04 16:47   ` Pu Wen
@ 2019-04-04 17:00     ` Julien Grall
  0 siblings, 0 replies; 37+ messages in thread
From: Julien Grall @ 2019-04-04 17:00 UTC (permalink / raw)
  To: Pu Wen, xen-devel
  Cc: Stefano Stabellini, Wei Liu, Suravee Suthikulpanit,
	Konrad Rzeszutek Wilk, George Dunlap, Andrew Cooper, Ian Jackson,
	Tim Deegan, Jan Beulich, Boris Ostrovsky, Brian Woods,
	Roger Pau Monné



On 04/04/2019 17:47, Pu Wen wrote:
> On 2019/4/4 22:08, Julien Grall wrote:
>> Hi,
>>
>> I am not sure why I end up to be CCed on the cover letter when I am not CCed on
>> the rest of series.
> 
> The patch 01/15 of the series is CCed to you. :)

I did notice it afterwards. But the code is only x86 specific...

It looks like xen/lib/x86 was not falling under the x86 maintainership. I have 
sent a patch to avoid the "REST" maintainers to be CCed on it.

Cheers,

-- 
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-05  7:49         ` Jan Beulich
  0 siblings, 0 replies; 37+ messages in thread
From: Jan Beulich @ 2019-04-05  7:49 UTC (permalink / raw)
  To: Pu Wen
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Andrew Cooper, Ian Jackson, Tim Deegan,
	Julien Grall, xen-devel, Roger Pau Monne

>>> On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
> On 2019/4/4 22:07, Andrew Cooper wrote:
>> This needs the following hunk folding in
>> 
>> diff --git a/tools/tests/cpu-policy/test-cpu-policy.c
>> b/tools/tests/cpu-policy/test-cpu-policy.c
>> index beced5e..88f5121 100644
>> --- a/tools/tests/cpu-policy/test-cpu-policy.c
>> +++ b/tools/tests/cpu-policy/test-cpu-policy.c
>> @@ -35,6 +35,7 @@ static void test_vendor_identification(void)
>>           { { "AuthenticAMD" }, X86_VENDOR_AMD },
>>           { { "CentaurHauls" }, X86_VENDOR_CENTAUR },
>>           { { "  Shanghai  " }, X86_VENDOR_SHANGHAI },
>> +        { { "HygonGenuine" }, X86_VENDOR_HYGON },
>>   
>>           { { ""             }, X86_VENDOR_UNKNOWN },
>>           { { "            " }, X86_VENDOR_UNKNOWN },
> 
> I'm sorry for missing this file.
> 
>> which can be done on commit to avoid sending yet another version.
> 
> Do you mean I need to send a individual patch for this file instead of 
> reworking the whole series?

I don't think that's necessary, unless other reasons arise for there
to be yet another round necessary. As Andrew says - this can easily
be done while committing.

Jan



_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-05  7:49         ` Jan Beulich
  0 siblings, 0 replies; 37+ messages in thread
From: Jan Beulich @ 2019-04-05  7:49 UTC (permalink / raw)
  To: Pu Wen
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Andrew Cooper, Ian Jackson, Tim Deegan,
	Julien Grall, xen-devel, Roger Pau Monne

>>> On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
> On 2019/4/4 22:07, Andrew Cooper wrote:
>> This needs the following hunk folding in
>> 
>> diff --git a/tools/tests/cpu-policy/test-cpu-policy.c
>> b/tools/tests/cpu-policy/test-cpu-policy.c
>> index beced5e..88f5121 100644
>> --- a/tools/tests/cpu-policy/test-cpu-policy.c
>> +++ b/tools/tests/cpu-policy/test-cpu-policy.c
>> @@ -35,6 +35,7 @@ static void test_vendor_identification(void)
>>           { { "AuthenticAMD" }, X86_VENDOR_AMD },
>>           { { "CentaurHauls" }, X86_VENDOR_CENTAUR },
>>           { { "  Shanghai  " }, X86_VENDOR_SHANGHAI },
>> +        { { "HygonGenuine" }, X86_VENDOR_HYGON },
>>   
>>           { { ""             }, X86_VENDOR_UNKNOWN },
>>           { { "            " }, X86_VENDOR_UNKNOWN },
> 
> I'm sorry for missing this file.
> 
>> which can be done on commit to avoid sending yet another version.
> 
> Do you mean I need to send a individual patch for this file instead of 
> reworking the whole series?

I don't think that's necessary, unless other reasons arise for there
to be yet another round necessary. As Andrew says - this can easily
be done while committing.

Jan



_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-12 16:14           ` Pu Wen
  0 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-12 16:14 UTC (permalink / raw)
  To: Jan Beulich, Andrew Cooper
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Tim Deegan, Ian Jackson, xen-devel,
	Roger Pau Monne

On 2019/4/5 15:50, Jan Beulich wrote:
> On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
>> On 2019/4/4 22:07, Andrew Cooper wrote:
>>> This needs the following hunk folding in
>>> which can be done on commit to avoid sending yet another version.
>>
>> Do you mean I need to send a individual patch for this file instead of
>> reworking the whole series?
> 
> I don't think that's necessary, unless other reasons arise for there
> to be yet another round necessary. As Andrew says - this can easily
> be done while committing.

Hi Jan and Andrew,

How about the patches till now? Are they acceptable to commit?

Thx.

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-12 16:14           ` Pu Wen
  0 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-12 16:14 UTC (permalink / raw)
  To: Jan Beulich, Andrew Cooper
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Tim Deegan, Ian Jackson, xen-devel,
	Roger Pau Monne

On 2019/4/5 15:50, Jan Beulich wrote:
> On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
>> On 2019/4/4 22:07, Andrew Cooper wrote:
>>> This needs the following hunk folding in
>>> which can be done on commit to avoid sending yet another version.
>>
>> Do you mean I need to send a individual patch for this file instead of
>> reworking the whole series?
> 
> I don't think that's necessary, unless other reasons arise for there
> to be yet another round necessary. As Andrew says - this can easily
> be done while committing.

Hi Jan and Andrew,

How about the patches till now? Are they acceptable to commit?

Thx.

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-17 15:03             ` Wei Liu
  0 siblings, 0 replies; 37+ messages in thread
From: Wei Liu @ 2019-04-17 15:03 UTC (permalink / raw)
  To: Pu Wen
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Andrew Cooper, Ian Jackson, Tim Deegan,
	Jan Beulich, xen-devel, Roger Pau Monne

On Sat, Apr 13, 2019 at 12:14:14AM +0800, Pu Wen wrote:
> On 2019/4/5 15:50, Jan Beulich wrote:
> > On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
> > > On 2019/4/4 22:07, Andrew Cooper wrote:
> > > > This needs the following hunk folding in
> > > > which can be done on commit to avoid sending yet another version.
> > > 
> > > Do you mean I need to send a individual patch for this file instead of
> > > reworking the whole series?
> > 
> > I don't think that's necessary, unless other reasons arise for there
> > to be yet another round necessary. As Andrew says - this can easily
> > be done while committing.
> 
> Hi Jan and Andrew,
> 
> How about the patches till now? Are they acceptable to commit?

FYI we're trying to sort out issues with upstream CI system, so
committing these patches need to wait a bit. But don't worry, they will
eventually be committed (assuming all the acks and Rbs are in place).

Wei.

> 
> Thx.
> 
> -- 
> Regards,
> Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-17 15:03             ` Wei Liu
  0 siblings, 0 replies; 37+ messages in thread
From: Wei Liu @ 2019-04-17 15:03 UTC (permalink / raw)
  To: Pu Wen
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Andrew Cooper, Ian Jackson, Tim Deegan,
	Jan Beulich, xen-devel, Roger Pau Monne

On Sat, Apr 13, 2019 at 12:14:14AM +0800, Pu Wen wrote:
> On 2019/4/5 15:50, Jan Beulich wrote:
> > On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
> > > On 2019/4/4 22:07, Andrew Cooper wrote:
> > > > This needs the following hunk folding in
> > > > which can be done on commit to avoid sending yet another version.
> > > 
> > > Do you mean I need to send a individual patch for this file instead of
> > > reworking the whole series?
> > 
> > I don't think that's necessary, unless other reasons arise for there
> > to be yet another round necessary. As Andrew says - this can easily
> > be done while committing.
> 
> Hi Jan and Andrew,
> 
> How about the patches till now? Are they acceptable to commit?

FYI we're trying to sort out issues with upstream CI system, so
committing these patches need to wait a bit. But don't worry, they will
eventually be committed (assuming all the acks and Rbs are in place).

Wei.

> 
> Thx.
> 
> -- 
> Regards,
> Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-18  2:15               ` Pu Wen
  0 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-18  2:15 UTC (permalink / raw)
  To: Wei Liu
  Cc: Stefano Stabellini, Konrad Rzeszutek Wilk, George Dunlap,
	Andrew Cooper, Ian Jackson, Tim Deegan, Jan Beulich, xen-devel,
	Roger Pau Monne

On 2019/4/17 23:04, Wei Liu wrote:
> On Sat, Apr 13, 2019 at 12:14:14AM +0800, Pu Wen wrote:
>> On 2019/4/5 15:50, Jan Beulich wrote:
>>> On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
>>>> On 2019/4/4 22:07, Andrew Cooper wrote:
>>>>> This needs the following hunk folding in
>>>>> which can be done on commit to avoid sending yet another version.
>>>>
>>>> Do you mean I need to send a individual patch for this file instead of
>>>> reworking the whole series?
>>>
>>> I don't think that's necessary, unless other reasons arise for there
>>> to be yet another round necessary. As Andrew says - this can easily
>>> be done while committing.
>>
>> Hi Jan and Andrew,
>>
>> How about the patches till now? Are they acceptable to commit?
> 
> FYI we're trying to sort out issues with upstream CI system, so
> committing these patches need to wait a bit. But don't worry, they will
> eventually be committed (assuming all the acks and Rbs are in place).

Okay, thanks! But there's still no acks for this patch of the whole 
series, so I just worry about it. Could someone offer Acked-by tag for it?

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-18  2:15               ` Pu Wen
  0 siblings, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-04-18  2:15 UTC (permalink / raw)
  To: Wei Liu
  Cc: Stefano Stabellini, Konrad Rzeszutek Wilk, George Dunlap,
	Andrew Cooper, Ian Jackson, Tim Deegan, Jan Beulich, xen-devel,
	Roger Pau Monne

On 2019/4/17 23:04, Wei Liu wrote:
> On Sat, Apr 13, 2019 at 12:14:14AM +0800, Pu Wen wrote:
>> On 2019/4/5 15:50, Jan Beulich wrote:
>>> On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
>>>> On 2019/4/4 22:07, Andrew Cooper wrote:
>>>>> This needs the following hunk folding in
>>>>> which can be done on commit to avoid sending yet another version.
>>>>
>>>> Do you mean I need to send a individual patch for this file instead of
>>>> reworking the whole series?
>>>
>>> I don't think that's necessary, unless other reasons arise for there
>>> to be yet another round necessary. As Andrew says - this can easily
>>> be done while committing.
>>
>> Hi Jan and Andrew,
>>
>> How about the patches till now? Are they acceptable to commit?
> 
> FYI we're trying to sort out issues with upstream CI system, so
> committing these patches need to wait a bit. But don't worry, they will
> eventually be committed (assuming all the acks and Rbs are in place).

Okay, thanks! But there's still no acks for this patch of the whole 
series, so I just worry about it. Could someone offer Acked-by tag for it?

-- 
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-18  9:14                 ` Wei Liu
  0 siblings, 0 replies; 37+ messages in thread
From: Wei Liu @ 2019-04-18  9:14 UTC (permalink / raw)
  To: Pu Wen
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Andrew Cooper, Ian Jackson, Tim Deegan,
	Jan Beulich, xen-devel, Roger Pau Monne

On Thu, Apr 18, 2019 at 10:15:05AM +0800, Pu Wen wrote:
> On 2019/4/17 23:04, Wei Liu wrote:
> > On Sat, Apr 13, 2019 at 12:14:14AM +0800, Pu Wen wrote:
> > > On 2019/4/5 15:50, Jan Beulich wrote:
> > > > On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
> > > > > On 2019/4/4 22:07, Andrew Cooper wrote:
> > > > > > This needs the following hunk folding in
> > > > > > which can be done on commit to avoid sending yet another version.
> > > > > 
> > > > > Do you mean I need to send a individual patch for this file instead of
> > > > > reworking the whole series?
> > > > 
> > > > I don't think that's necessary, unless other reasons arise for there
> > > > to be yet another round necessary. As Andrew says - this can easily
> > > > be done while committing.
> > > 
> > > Hi Jan and Andrew,
> > > 
> > > How about the patches till now? Are they acceptable to commit?
> > 
> > FYI we're trying to sort out issues with upstream CI system, so
> > committing these patches need to wait a bit. But don't worry, they will
> > eventually be committed (assuming all the acks and Rbs are in place).
> 
> Okay, thanks! But there's still no acks for this patch of the whole series,
> so I just worry about it. Could someone offer Acked-by tag for it?

It would be either Jan or Andrew who needs to ack this patch.  Jan is
away at the moment. And a lot of us in Europe have a long Easter weekend
this week.

From my reading of their comments, you don't need to worry about getting
an ack.

Wei.

> 
> -- 
> Regards,
> Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file
@ 2019-04-18  9:14                 ` Wei Liu
  0 siblings, 0 replies; 37+ messages in thread
From: Wei Liu @ 2019-04-18  9:14 UTC (permalink / raw)
  To: Pu Wen
  Cc: Stefano Stabellini, Wei Liu, Konrad Rzeszutek Wilk,
	George Dunlap, Andrew Cooper, Ian Jackson, Tim Deegan,
	Jan Beulich, xen-devel, Roger Pau Monne

On Thu, Apr 18, 2019 at 10:15:05AM +0800, Pu Wen wrote:
> On 2019/4/17 23:04, Wei Liu wrote:
> > On Sat, Apr 13, 2019 at 12:14:14AM +0800, Pu Wen wrote:
> > > On 2019/4/5 15:50, Jan Beulich wrote:
> > > > On 04.04.19 at 18:39, <puwen@hygon.cn> wrote:
> > > > > On 2019/4/4 22:07, Andrew Cooper wrote:
> > > > > > This needs the following hunk folding in
> > > > > > which can be done on commit to avoid sending yet another version.
> > > > > 
> > > > > Do you mean I need to send a individual patch for this file instead of
> > > > > reworking the whole series?
> > > > 
> > > > I don't think that's necessary, unless other reasons arise for there
> > > > to be yet another round necessary. As Andrew says - this can easily
> > > > be done while committing.
> > > 
> > > Hi Jan and Andrew,
> > > 
> > > How about the patches till now? Are they acceptable to commit?
> > 
> > FYI we're trying to sort out issues with upstream CI system, so
> > committing these patches need to wait a bit. But don't worry, they will
> > eventually be committed (assuming all the acks and Rbs are in place).
> 
> Okay, thanks! But there's still no acks for this patch of the whole series,
> so I just worry about it. Could someone offer Acked-by tag for it?

It would be either Jan or Andrew who needs to ack this patch.  Jan is
away at the moment. And a lot of us in Europe have a long Easter weekend
this week.

From my reading of their comments, you don't need to worry about getting
an ack.

Wei.

> 
> -- 
> Regards,
> Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
  2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
                   ` (15 preceding siblings ...)
  2019-04-04 13:53 ` [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Julien Grall
@ 2019-06-06 16:31 ` Andrew Cooper
       [not found] ` <201906070115.x571Fd9j014046@spam1.hygon.cn>
  17 siblings, 0 replies; 37+ messages in thread
From: Andrew Cooper @ 2019-06-06 16:31 UTC (permalink / raw)
  To: Pu Wen, xen-devel

On 04/04/2019 14:44, Pu Wen wrote:
> This patch series have been applied and tested successfully on Hygon
> Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
> It works fine and makes no harm to the existing code.

Hello,

Sorry for the delay.

I've rebased the patches over my CPUID work, and pushed the ones which
still apply cleanly to staging.  However, some don't apply cleanly any
more, so I left those alone.

Please could you check the current staging build (and in particular,
that I didn't accidentally break anything with the rebase), and rebase
the remainder of the series onto staging.

Thanks,

~Andrew

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
       [not found] ` <201906070115.x571Fd9j014046@spam1.hygon.cn>
@ 2019-06-07 15:54   ` Pu Wen
  2019-06-12 15:10   ` Pu Wen
  1 sibling, 0 replies; 37+ messages in thread
From: Pu Wen @ 2019-06-07 15:54 UTC (permalink / raw)
  To: Andrew Cooper, xen-devel

On 2019/6/7 0:31, Andrew Cooper wrote:
> I've rebased the patches over my CPUID work, and pushed the ones which
> still apply cleanly to staging.  However, some don't apply cleanly any

Thanks a lot.

> more, so I left those alone.
> 
> Please could you check the current staging build (and in particular,
> that I didn't accidentally break anything with the rebase), and rebase

Yes, the current staging build is OK and works on Hygon platform.
I'll check the functionalities more carefully.

> the remainder of the series onto staging.

I'll do this later on.

--
Regards,
Pu Wen


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
       [not found] ` <201906070115.x571Fd9j014046@spam1.hygon.cn>
  2019-06-07 15:54   ` Pu Wen
@ 2019-06-12 15:10   ` Pu Wen
  2019-06-12 15:58     ` Andrew Cooper
  1 sibling, 1 reply; 37+ messages in thread
From: Pu Wen @ 2019-06-12 15:10 UTC (permalink / raw)
  To: Andrew Cooper, JBeulich; +Cc: xen-devel

On 2019/6/7 0:31, Andrew Cooper wrote:
> I've rebased the patches over my CPUID work, and pushed the ones which
> still apply cleanly to staging.  However, some don't apply cleanly any
> more, so I left those alone.
>
> Please could you check the current staging build (and in particular,
> that I didn't accidentally break anything with the rebase), and rebase
> the remainder of the series onto staging.

I rebased the patches x86/acpi and x86/pv over 0cd07414 "x86/cpu:
Renumber X86_VENDOR_* to form a bitmap", and sent them out with version
v6. I dropped the patch x86/iommu for Hygon because it's no needed any
more since the commit 1b3cc800 "x86/IOMMU: introduce init-ops structure"
removed the vendor check.

I still hold Jan's Acked-by tags however the code is changed. Are the
tags still valid?

Thx.

--
Regards,
Pu Wen

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Xen-devel] [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor
  2019-06-12 15:10   ` Pu Wen
@ 2019-06-12 15:58     ` Andrew Cooper
  0 siblings, 0 replies; 37+ messages in thread
From: Andrew Cooper @ 2019-06-12 15:58 UTC (permalink / raw)
  To: Pu Wen, JBeulich; +Cc: xen-devel

On 12/06/2019 16:10, Pu Wen wrote:
> On 2019/6/7 0:31, Andrew Cooper wrote:
>> I've rebased the patches over my CPUID work, and pushed the ones which
>> still apply cleanly to staging.  However, some don't apply cleanly any
>> more, so I left those alone.
>>
>> Please could you check the current staging build (and in particular,
>> that I didn't accidentally break anything with the rebase), and rebase
>> the remainder of the series onto staging.
>
> I rebased the patches x86/acpi and x86/pv over 0cd07414 "x86/cpu:
> Renumber X86_VENDOR_* to form a bitmap", and sent them out with version
> v6. I dropped the patch x86/iommu for Hygon because it's no needed any
> more since the commit 1b3cc800 "x86/IOMMU: introduce init-ops structure"
> removed the vendor check.
>
> I still hold Jan's Acked-by tags however the code is changed. Are the
> tags still valid?

Yes.  The tags were still valid, because you're not fundamentally
changing the patch from how it was before.

I've committed the patches now.

~Andrew

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

^ permalink raw reply	[flat|nested] 37+ messages in thread

end of thread, other threads:[~2019-06-12 15:58 UTC | newest]

Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
2019-04-04 13:45 ` [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2019-04-04 14:02   ` Andrew Cooper
2019-04-04 16:39     ` Pu Wen
2019-04-05  7:49       ` Jan Beulich
2019-04-05  7:49         ` [Xen-devel] " Jan Beulich
2019-04-12 16:14         ` Pu Wen
2019-04-12 16:14           ` [Xen-devel] " Pu Wen
2019-04-17 15:03           ` Wei Liu
2019-04-17 15:03             ` [Xen-devel] " Wei Liu
2019-04-18  2:15             ` Pu Wen
2019-04-18  2:15               ` [Xen-devel] " Pu Wen
2019-04-18  9:14               ` Wei Liu
2019-04-18  9:14                 ` [Xen-devel] " Wei Liu
2019-04-04 13:45 ` [PATCH v5 02/15] x86/cpu: Fix common cpuid faulting probing for AMD and Hygon Pu Wen
2019-04-04 13:45 ` [PATCH v5 03/15] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 Pu Wen
2019-04-04 13:46 ` [PATCH v5 04/15] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU Pu Wen
2019-04-04 13:46 ` [PATCH v5 05/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure Pu Wen
2019-04-04 13:46 ` [PATCH v5 06/15] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery Pu Wen
2019-04-04 13:46 ` [PATCH v5 07/15] x86/apic: Add Hygon Dhyana support Pu Wen
2019-04-04 13:46 ` [PATCH v5 08/15] x86/acpi: " Pu Wen
2019-04-04 13:47 ` [PATCH v5 09/15] x86/iommu: " Pu Wen
2019-04-04 13:47 ` [PATCH v5 10/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access Pu Wen
2019-04-04 13:47 ` [PATCH v5 11/15] x86/domain: Add Hygon Dhyana support Pu Wen
2019-04-04 13:47 ` [PATCH v5 12/15] x86/domctl: " Pu Wen
2019-04-04 13:47 ` [PATCH v5 13/15] x86/traps: " Pu Wen
2019-04-04 13:48 ` [PATCH v5 14/15] x86/cpuid: " Pu Wen
2019-04-04 13:48 ` [PATCH v5 15/15] tools/libxc: " Pu Wen
2019-04-04 16:26   ` Wei Liu
2019-04-04 16:40     ` Pu Wen
2019-04-04 13:53 ` [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Julien Grall
2019-04-04 16:47   ` Pu Wen
2019-04-04 17:00     ` Julien Grall
2019-06-06 16:31 ` [Xen-devel] " Andrew Cooper
     [not found] ` <201906070115.x571Fd9j014046@spam1.hygon.cn>
2019-06-07 15:54   ` Pu Wen
2019-06-12 15:10   ` Pu Wen
2019-06-12 15:58     ` Andrew Cooper

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.