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[83.35.25.14]) by smtp.gmail.com with ESMTPSA id h1sm2564343wmb.7.2021.09.19.11.32.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 19 Sep 2021 11:32:12 -0700 (PDT) Message-ID: Date: Sun, 19 Sep 2021 20:32:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Subject: Re: [PATCH v2 27/41] target/i386: Implement x86_cpu_record_sigsegv Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20210918184527.408540-1-richard.henderson@linaro.org> <20210918184527.408540-28-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20210918184527.408540-28-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, CTE_8BIT_MISMATCH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/18/21 20:45, Richard Henderson wrote: > Record cr2, error_code, and exception_index. That last means > that we must exit to cpu_loop ourselves, instead of letting > exception_index being overwritten. > > Use the maperr parameter to properly set PG_ERROR_P_MASK. > > Signed-off-by: Richard Henderson > --- > target/i386/tcg/helper-tcg.h | 6 ++++++ > target/i386/tcg/tcg-cpu.c | 3 ++- > target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ > 3 files changed, 25 insertions(+), 7 deletions(-) > diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c > index a89b5228fd..cd507e2a1b 100644 > --- a/target/i386/tcg/user/excp_helper.c > +++ b/target/i386/tcg/user/excp_helper.c > @@ -22,18 +22,29 @@ > #include "exec/exec-all.h" > #include "tcg/helper-tcg.h" > > -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, > - MMUAccessType access_type, int mmu_idx, > - bool probe, uintptr_t retaddr) > +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, > + MMUAccessType access_type, > + bool maperr, uintptr_t ra) > { > X86CPU *cpu = X86_CPU(cs); > CPUX86State *env = &cpu->env; > > + /* > + * The error_code that hw reports as part of the exception frame > + * is copied to linux sigcontext.err. The exception_index is > + * copied to linux sigcontext.trapno. Short of inventing a new > + * place to store the trapno, we cannot let our caller raise the > + * signal and set exception_index to EXCP_INTERRUPT. > + */ > env->cr[2] = addr; > - env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; > - env->error_code |= PG_ERROR_U_MASK; > + env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) > + | (maperr ? 0 : PG_ERROR_P_MASK) > + | PG_ERROR_U_MASK; > cs->exception_index = EXCP0E_PAGE; > + > + /* Disable do_interrupt_user. */ > env->exception_is_int = 0; > env->exception_next_eip = -1; > - cpu_loop_exit_restore(cs, retaddr); > + > + cpu_loop_exit_restore(cs, ra); > } > Better have an x86 expert also review this, but to the best of my knowledge: Reviewed-by: Philippe Mathieu-Daudé And YAY! btw, thanks :>