From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 267B77B for ; Wed, 26 Oct 2022 22:32:55 +0000 (UTC) Received: by mail-lf1-f46.google.com with SMTP id f37so31781338lfv.8 for ; Wed, 26 Oct 2022 15:32:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:in-reply-to:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:from:to:cc:subject:date:message-id:reply-to; bh=avrg0p0zcjNQXnwku7LjBEc26ITlI2L8ZDmV7YUxLHk=; b=hNP1eWcSKtSWB1d/Pitcegm6aBvNbn9ZZwOPfvyAHeLfSpWgKviYSn4HdfxqpmVxLx 3hqUT8rGLCtA1WbTsRwnPe5u3UcMos9xSnD5TZv+rOmijKDGBBCh8NVOtzeenY0qOWJW oh4drqCKFAmxuzjfWyqczkgGVY4e/XY9DK8cne6pWop/CZJOjY5RUV1N/4OKtEk0nxJO UC4dx27z4ITheuTf5vkslf5rQZRUk0qCvLfi1+DCcHCbS9nB8ML9tKunPxRfZ0ivAOEf qxDLwB203CFgLYKKW5ACXrIXmtd/8O6FmrNt5N5n34ARyUZHAOHdwbczBPdcJL3R4Gsa ONMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=avrg0p0zcjNQXnwku7LjBEc26ITlI2L8ZDmV7YUxLHk=; b=L7sa+lc4oaxnOekjyhzhMgwBy5BId44yuvvWDFAI8vxduxzJZfN4ODT4A2j0mHRCY+ GId+hCKMLb/Sk8e592zjoE1uKTrnbQlduHtzV1/uhc7j3uasyGglidIFE5J9HFj02uc6 l/Zqjj55tisZpM2aolF3WaQp38zom0hbQnSm8V86exk5/yzAf3SjW6n4auQuBHFCSEKj 9x5/HVD+UNXB/GAM3Ln+Sq/nRw4w3JC3CMLIsRo5pW1Xs6YkY7Mv0zvJ9FD0CBZ2qiW7 33jTGs5GIcxirlMDIMWcxuQFeo6dFbd9vzK9DZQ9iH/jSXyDgWdP0tnD1y73R4xftMpy MVkA== X-Gm-Message-State: ACrzQf3zd1Z5xbFVdY6paxGRqzmuRHhhcnvxk33GVK8Ucxp1z7Rc40bX YbhP+u/Zv9nJoZ6vk7//u3M= X-Google-Smtp-Source: AMsMyM52ijLmTwWqEjQAFcbPkrpP0UqjyCZnJDRwDtXnieH2RtRbTOsPad5/gfZTaDZK85qSTqo5mQ== X-Received: by 2002:ac2:4c47:0:b0:4a2:c07b:4b62 with SMTP id o7-20020ac24c47000000b004a2c07b4b62mr15855128lfk.426.1666823572924; Wed, 26 Oct 2022 15:32:52 -0700 (PDT) Received: from ?IPV6:2a02:a31a:a240:1700:c898:de98:30b3:a07? ([2a02:a31a:a240:1700:c898:de98:30b3:a07]) by smtp.googlemail.com with ESMTPSA id n11-20020ac2490b000000b004979df1c1fasm994280lfi.61.2022.10.26.15.32.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 15:32:52 -0700 (PDT) From: Mateusz Kwiatkowski X-Google-Original-From: Mateusz Kwiatkowski Message-ID: Date: Thu, 27 Oct 2022 00:32:50 +0200 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards Content-Language: pl To: maxime@cerno.tech, Karol Herbst , Emma Anholt , Ben Skeggs , Chen-Yu Tsai , Rodrigo Vivi , Maarten Lankhorst , Jani Nikula , Daniel Vetter , Thomas Zimmermann , Tvrtko Ursulin , Samuel Holland , Jernej Skrabec , David Airlie , Maxime Ripard , Joonas Lahtinen , Lyude Paul Cc: linux-sunxi@lists.linux.dev, intel-gfx@lists.freedesktop.org, Phil Elwell , linux-arm-kernel@lists.infradead.org, nouveau@lists.freedesktop.org, Hans de Goede , Dom Cobley , dri-devel@lists.freedesktop.org, Dave Stevenson , linux-kernel@vger.kernel.org, =?UTF-8?Q?Noralf_Tr=c3=b8nnes?= , Geert Uytterhoeven References: <20220728-rpi-analog-tv-properties-v6-0-e7792734108f@cerno.tech> <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> In-Reply-To: <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Maxime, I've seen that you've incorporated my PAL60 patch. Thanks! I still yet need to test your v6 changes, but looking at this code with just my mental static analysis, it seems to me that the vc4_vec_encoder_atomic_check() should have the tv_mode validation. I should've added it to the PAL60 patch, but it somehow slipped my mind then. Anyway, I mentioned it previously here: https://lore.kernel.org/dri-devel/0f2beec2-ae8e-5579-f0b6-a73d9dae1af4@gmail.com/ It would look something like this, inside vc4_vec_encoder_atomic_check(): + const struct vc4_vec_tv_mode *tv_mode = + vc4_vec_tv_mode_lookup(conn_state->tv.mode); + + if (!tv_mode) + return -EINVAL; Without this, it's possible to set e.g. 480i mode and SECAM, which will fail - but with the current version it will only fail in vc4_vec_encoder_enable(), which cannot return an error, and in my experience that causes a rather lengthy lockup. But, like I said, I still need to actually test that with this version. Anyway, I was also thinking about adding support for the more "exotic" non-standard modes. NTSC-50 is, unfortunately, impossible with VEC, but PAL-N-60 and PAL-M-50 should work. The necessary vc4_vec_tv_modes entries would look something like: @@ -325,12 +325,28 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { .config0 = VEC_CONFIG0_PAL_M_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-M-50 */ + .mode = DRM_MODE_TV_MODE_PAL, + .expected_htotal = 864, + .config0 = VEC_CONFIG0_PAL_BDGHI_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21e6efe3, + }, { .mode = DRM_MODE_TV_MODE_PAL_N, .expected_htotal = 864, .config0 = VEC_CONFIG0_PAL_N_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-N-60 */ + .mode = DRM_MODE_TV_MODE_PAL_N, + .expected_htotal = 858, + .config0 = VEC_CONFIG0_PAL_M_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21f69446, + }, { .mode = DRM_MODE_TV_MODE_SECAM, .expected_htotal = 864, I'm not sure if we actually want to add that. The two arguments for doing so I can think of is 1. it should work, so "why not", 2. it means that more modes will result in _some_ kind of a valid signal, rather than erroring out, which is always a plus in my book. I can also think of a hypothetical use case, like someone in South America with an old PAL-N-only set that would nevertheless still sync at 60 Hz (perhaps with the help of messing with vertical hold knob), who would like to play retro games at 60 Hz in color. But on the other hand, I admit that this scenario is likely a stretch and the number of people who would actually use it is probably close to the proverbial two ;) So it's your call, I'm just leaving those settings here just in case. I'll get back in a couple of days when I do some testing of this v6 patchset. Best regards, Mateusz Kwiatkowski W dniu 26.10.2022 o 17:33, maxime@cerno.tech pisze: > From: Mateusz Kwiatkowski > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Acked-by: Noralf Trønnes > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > > --- > Changes in v6: > - Support PAL60 again > --- > drivers/gpu/drm/vc4/vc4_vec.c | 111 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 107 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c > index 1dda451c8def..d82aef168075 100644 > --- a/drivers/gpu/drm/vc4/vc4_vec.c > +++ b/drivers/gpu/drm/vc4/vc4_vec.c > @@ -46,6 +46,7 @@ > #define VEC_CONFIG0_YDEL(x) ((x) << 26) > #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) > #define VEC_CONFIG0_CDEL(x) ((x) << 24) > +#define VEC_CONFIG0_SECAM_STD BIT(21) > #define VEC_CONFIG0_PBPR_FIL BIT(18) > #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) > #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) > @@ -76,6 +77,27 @@ > #define VEC_SOFT_RESET 0x10c > #define VEC_CLMP0_START 0x144 > #define VEC_CLMP0_END 0x148 > + > +/* > + * These set the color subcarrier frequency > + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. > + * > + * VEC_FREQ1_0 contains the most significant 16-bit half-word, > + * VEC_FREQ3_2 contains the least significant 16-bit half-word. > + * 0x80000000 seems to be equivalent to the pixel clock > + * (which itself is the VEC clock divided by 8). > + * > + * Reference values (with the default pixel clock of 13.5 MHz): > + * > + * NTSC (3579545.[45] Hz) - 0x21F07C1F > + * PAL (4433618.75 Hz) - 0x2A098ACB > + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 > + * PAL-N (3582056.25 Hz) - 0x21F69446 > + * > + * NOTE: For SECAM, it is used as the Dr center frequency, > + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; > + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. > + */ > #define VEC_FREQ3_2 0x180 > #define VEC_FREQ1_0 0x184 > > @@ -118,6 +140,14 @@ > > #define VEC_INTERRUPT_CONTROL 0x190 > #define VEC_INTERRUPT_STATUS 0x194 > + > +/* > + * Db center frequency for SECAM; the clock for this is the same as for > + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. > + * > + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. > + * That is also the default value, so no need to set it explicitly. > + */ > #define VEC_FCW_SECAM_B 0x198 > #define VEC_SECAM_GAIN_VAL 0x19c > > @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { > VC4_VEC_TV_MODE_NTSC_J, > VC4_VEC_TV_MODE_PAL, > VC4_VEC_TV_MODE_PAL_M, > + VC4_VEC_TV_MODE_NTSC_443, > + VC4_VEC_TV_MODE_PAL_60, > + VC4_VEC_TV_MODE_PAL_N, > + VC4_VEC_TV_MODE_SECAM, > }; > > struct vc4_vec_tv_mode { > unsigned int mode; > + u16 expected_htotal; > u32 config0; > u32 config1; > u32 custom_freq; > @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { > static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { > { > .mode = DRM_MODE_TV_MODE_NTSC, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_NTSC_443, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_NTSC_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_NTSC_J, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > { > .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 864, > .config0 = VEC_CONFIG0_PAL_BDGHI_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + /* PAL-60 */ > + .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_PAL_M_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_PAL_M, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_PAL_M_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_PAL_N, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_PAL_N_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + }, > + { > + .mode = DRM_MODE_TV_MODE_SECAM, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_SECAM_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + .custom_freq = 0x29c71c72, > + }, > }; > > static inline const struct vc4_vec_tv_mode * > -vc4_vec_tv_mode_lookup(unsigned int mode) > +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) > { > unsigned int i; > > for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { > const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; > > - if (tv_mode->mode == mode) > + if (tv_mode->mode == mode && > + tv_mode->expected_htotal == htotal) > return tv_mode; > } > > @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) > > static const struct drm_prop_enum_list legacy_tv_mode_names[] = { > { VC4_VEC_TV_MODE_NTSC, "NTSC", }, > + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, > { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, > { VC4_VEC_TV_MODE_PAL, "PAL", }, > + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, > { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, > + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, > + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, > }; > > static enum drm_connector_status > @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_NTSC; > break; > > + case VC4_VEC_TV_MODE_NTSC_443: > + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; > + break; > + > case VC4_VEC_TV_MODE_NTSC_J: > state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; > break; > > case VC4_VEC_TV_MODE_PAL: > + case VC4_VEC_TV_MODE_PAL_60: > state->tv.mode = DRM_MODE_TV_MODE_PAL; > break; > > @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_PAL_M; > break; > > + case VC4_VEC_TV_MODE_PAL_N: > + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; > + break; > + > + case VC4_VEC_TV_MODE_SECAM: > + state->tv.mode = DRM_MODE_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_NTSC; > break; > > + case DRM_MODE_TV_MODE_NTSC_443: > + *val = VC4_VEC_TV_MODE_NTSC_443; > + break; > + > case DRM_MODE_TV_MODE_NTSC_J: > *val = VC4_VEC_TV_MODE_NTSC_J; > break; > @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_PAL_M; > break; > > + case DRM_MODE_TV_MODE_PAL_N: > + *val = VC4_VEC_TV_MODE_PAL_N; > + break; > + > + case DRM_MODE_TV_MODE_SECAM: > + *val = VC4_VEC_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, > struct drm_connector *connector = &vec->connector; > struct drm_connector_state *conn_state = > drm_atomic_get_new_connector_state(state, connector); > + struct drm_display_mode *adjusted_mode = > + &encoder->crtc->state->adjusted_mode; > const struct vc4_vec_tv_mode *tv_mode; > int idx, ret; > > if (!drm_dev_enter(drm, &idx)) > return; > > - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); > + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, > + adjusted_mode->htotal); > if (!tv_mode) > goto err_dev_exit; > > @@ -643,9 +743,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) > > ret = drm_mode_create_tv_properties(drm, > BIT(DRM_MODE_TV_MODE_NTSC) | > + BIT(DRM_MODE_TV_MODE_NTSC_443) | > BIT(DRM_MODE_TV_MODE_NTSC_J) | > BIT(DRM_MODE_TV_MODE_PAL) | > - BIT(DRM_MODE_TV_MODE_PAL_M)); > + BIT(DRM_MODE_TV_MODE_PAL_M) | > + BIT(DRM_MODE_TV_MODE_PAL_N) | > + BIT(DRM_MODE_TV_MODE_SECAM)); > if (ret) > return ret; > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75ADEC38A2D for ; Wed, 26 Oct 2022 22:33:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A46710E5A6; Wed, 26 Oct 2022 22:32:58 +0000 (UTC) Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAACC10E2A3; Wed, 26 Oct 2022 22:32:54 +0000 (UTC) Received: by mail-lf1-x132.google.com with SMTP id p8so31751353lfu.11; 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([2a02:a31a:a240:1700:c898:de98:30b3:a07]) by smtp.googlemail.com with ESMTPSA id n11-20020ac2490b000000b004979df1c1fasm994280lfi.61.2022.10.26.15.32.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 15:32:52 -0700 (PDT) From: Mateusz Kwiatkowski X-Google-Original-From: Mateusz Kwiatkowski Message-ID: Date: Thu, 27 Oct 2022 00:32:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Content-Language: pl To: maxime@cerno.tech, Karol Herbst , Emma Anholt , Ben Skeggs , Chen-Yu Tsai , Rodrigo Vivi , Maarten Lankhorst , Jani Nikula , Daniel Vetter , Thomas Zimmermann , Tvrtko Ursulin , Samuel Holland , Jernej Skrabec , David Airlie , Maxime Ripard , Joonas Lahtinen , Lyude Paul References: <20220728-rpi-analog-tv-properties-v6-0-e7792734108f@cerno.tech> <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> In-Reply-To: <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Nouveau] [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dom Cobley , nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Phil Elwell , Hans de Goede , =?UTF-8?Q?Noralf_Tr=c3=b8nnes?= , Geert Uytterhoeven , linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" Hi Maxime, I've seen that you've incorporated my PAL60 patch. Thanks! I still yet need to test your v6 changes, but looking at this code with just my mental static analysis, it seems to me that the vc4_vec_encoder_atomic_check() should have the tv_mode validation. I should've added it to the PAL60 patch, but it somehow slipped my mind then. Anyway, I mentioned it previously here: https://lore.kernel.org/dri-devel/0f2beec2-ae8e-5579-f0b6-a73d9dae1af4@gmail.com/ It would look something like this, inside vc4_vec_encoder_atomic_check(): + const struct vc4_vec_tv_mode *tv_mode = + vc4_vec_tv_mode_lookup(conn_state->tv.mode); + + if (!tv_mode) + return -EINVAL; Without this, it's possible to set e.g. 480i mode and SECAM, which will fail - but with the current version it will only fail in vc4_vec_encoder_enable(), which cannot return an error, and in my experience that causes a rather lengthy lockup. But, like I said, I still need to actually test that with this version. Anyway, I was also thinking about adding support for the more "exotic" non-standard modes. NTSC-50 is, unfortunately, impossible with VEC, but PAL-N-60 and PAL-M-50 should work. The necessary vc4_vec_tv_modes entries would look something like: @@ -325,12 +325,28 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { .config0 = VEC_CONFIG0_PAL_M_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-M-50 */ + .mode = DRM_MODE_TV_MODE_PAL, + .expected_htotal = 864, + .config0 = VEC_CONFIG0_PAL_BDGHI_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21e6efe3, + }, { .mode = DRM_MODE_TV_MODE_PAL_N, .expected_htotal = 864, .config0 = VEC_CONFIG0_PAL_N_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-N-60 */ + .mode = DRM_MODE_TV_MODE_PAL_N, + .expected_htotal = 858, + .config0 = VEC_CONFIG0_PAL_M_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21f69446, + }, { .mode = DRM_MODE_TV_MODE_SECAM, .expected_htotal = 864, I'm not sure if we actually want to add that. The two arguments for doing so I can think of is 1. it should work, so "why not", 2. it means that more modes will result in _some_ kind of a valid signal, rather than erroring out, which is always a plus in my book. I can also think of a hypothetical use case, like someone in South America with an old PAL-N-only set that would nevertheless still sync at 60 Hz (perhaps with the help of messing with vertical hold knob), who would like to play retro games at 60 Hz in color. But on the other hand, I admit that this scenario is likely a stretch and the number of people who would actually use it is probably close to the proverbial two ;) So it's your call, I'm just leaving those settings here just in case. I'll get back in a couple of days when I do some testing of this v6 patchset. Best regards, Mateusz Kwiatkowski W dniu 26.10.2022 o 17:33, maxime@cerno.tech pisze: > From: Mateusz Kwiatkowski > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Acked-by: Noralf Trønnes > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > > --- > Changes in v6: > - Support PAL60 again > --- > drivers/gpu/drm/vc4/vc4_vec.c | 111 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 107 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c > index 1dda451c8def..d82aef168075 100644 > --- a/drivers/gpu/drm/vc4/vc4_vec.c > +++ b/drivers/gpu/drm/vc4/vc4_vec.c > @@ -46,6 +46,7 @@ > #define VEC_CONFIG0_YDEL(x) ((x) << 26) > #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) > #define VEC_CONFIG0_CDEL(x) ((x) << 24) > +#define VEC_CONFIG0_SECAM_STD BIT(21) > #define VEC_CONFIG0_PBPR_FIL BIT(18) > #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) > #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) > @@ -76,6 +77,27 @@ > #define VEC_SOFT_RESET 0x10c > #define VEC_CLMP0_START 0x144 > #define VEC_CLMP0_END 0x148 > + > +/* > + * These set the color subcarrier frequency > + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. > + * > + * VEC_FREQ1_0 contains the most significant 16-bit half-word, > + * VEC_FREQ3_2 contains the least significant 16-bit half-word. > + * 0x80000000 seems to be equivalent to the pixel clock > + * (which itself is the VEC clock divided by 8). > + * > + * Reference values (with the default pixel clock of 13.5 MHz): > + * > + * NTSC (3579545.[45] Hz) - 0x21F07C1F > + * PAL (4433618.75 Hz) - 0x2A098ACB > + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 > + * PAL-N (3582056.25 Hz) - 0x21F69446 > + * > + * NOTE: For SECAM, it is used as the Dr center frequency, > + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; > + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. > + */ > #define VEC_FREQ3_2 0x180 > #define VEC_FREQ1_0 0x184 > > @@ -118,6 +140,14 @@ > > #define VEC_INTERRUPT_CONTROL 0x190 > #define VEC_INTERRUPT_STATUS 0x194 > + > +/* > + * Db center frequency for SECAM; the clock for this is the same as for > + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. > + * > + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. > + * That is also the default value, so no need to set it explicitly. > + */ > #define VEC_FCW_SECAM_B 0x198 > #define VEC_SECAM_GAIN_VAL 0x19c > > @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { > VC4_VEC_TV_MODE_NTSC_J, > VC4_VEC_TV_MODE_PAL, > VC4_VEC_TV_MODE_PAL_M, > + VC4_VEC_TV_MODE_NTSC_443, > + VC4_VEC_TV_MODE_PAL_60, > + VC4_VEC_TV_MODE_PAL_N, > + VC4_VEC_TV_MODE_SECAM, > }; > > struct vc4_vec_tv_mode { > unsigned int mode; > + u16 expected_htotal; > u32 config0; > u32 config1; > u32 custom_freq; > @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { > static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { > { > .mode = DRM_MODE_TV_MODE_NTSC, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_NTSC_443, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_NTSC_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_NTSC_J, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > { > .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 864, > .config0 = VEC_CONFIG0_PAL_BDGHI_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + /* PAL-60 */ > + .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_PAL_M_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_PAL_M, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_PAL_M_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_PAL_N, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_PAL_N_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + }, > + { > + .mode = DRM_MODE_TV_MODE_SECAM, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_SECAM_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + .custom_freq = 0x29c71c72, > + }, > }; > > static inline const struct vc4_vec_tv_mode * > -vc4_vec_tv_mode_lookup(unsigned int mode) > +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) > { > unsigned int i; > > for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { > const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; > > - if (tv_mode->mode == mode) > + if (tv_mode->mode == mode && > + tv_mode->expected_htotal == htotal) > return tv_mode; > } > > @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) > > static const struct drm_prop_enum_list legacy_tv_mode_names[] = { > { VC4_VEC_TV_MODE_NTSC, "NTSC", }, > + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, > { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, > { VC4_VEC_TV_MODE_PAL, "PAL", }, > + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, > { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, > + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, > + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, > }; > > static enum drm_connector_status > @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_NTSC; > break; > > + case VC4_VEC_TV_MODE_NTSC_443: > + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; > + break; > + > case VC4_VEC_TV_MODE_NTSC_J: > state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; > break; > > case VC4_VEC_TV_MODE_PAL: > + case VC4_VEC_TV_MODE_PAL_60: > state->tv.mode = DRM_MODE_TV_MODE_PAL; > break; > > @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_PAL_M; > break; > > + case VC4_VEC_TV_MODE_PAL_N: > + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; > + break; > + > + case VC4_VEC_TV_MODE_SECAM: > + state->tv.mode = DRM_MODE_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_NTSC; > break; > > + case DRM_MODE_TV_MODE_NTSC_443: > + *val = VC4_VEC_TV_MODE_NTSC_443; > + break; > + > case DRM_MODE_TV_MODE_NTSC_J: > *val = VC4_VEC_TV_MODE_NTSC_J; > break; > @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_PAL_M; > break; > > + case DRM_MODE_TV_MODE_PAL_N: > + *val = VC4_VEC_TV_MODE_PAL_N; > + break; > + > + case DRM_MODE_TV_MODE_SECAM: > + *val = VC4_VEC_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, > struct drm_connector *connector = &vec->connector; > struct drm_connector_state *conn_state = > drm_atomic_get_new_connector_state(state, connector); > + struct drm_display_mode *adjusted_mode = > + &encoder->crtc->state->adjusted_mode; > const struct vc4_vec_tv_mode *tv_mode; > int idx, ret; > > if (!drm_dev_enter(drm, &idx)) > return; > > - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); > + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, > + adjusted_mode->htotal); > if (!tv_mode) > goto err_dev_exit; > > @@ -643,9 +743,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) > > ret = drm_mode_create_tv_properties(drm, > BIT(DRM_MODE_TV_MODE_NTSC) | > + BIT(DRM_MODE_TV_MODE_NTSC_443) | > BIT(DRM_MODE_TV_MODE_NTSC_J) | > BIT(DRM_MODE_TV_MODE_PAL) | > - BIT(DRM_MODE_TV_MODE_PAL_M)); > + BIT(DRM_MODE_TV_MODE_PAL_M) | > + BIT(DRM_MODE_TV_MODE_PAL_N) | > + BIT(DRM_MODE_TV_MODE_SECAM)); > if (ret) > return ret; > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F555C38A2D for ; Wed, 26 Oct 2022 22:33:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C5E010E5A1; Wed, 26 Oct 2022 22:32:58 +0000 (UTC) Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAACC10E2A3; Wed, 26 Oct 2022 22:32:54 +0000 (UTC) Received: by mail-lf1-x132.google.com with SMTP id p8so31751353lfu.11; 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([2a02:a31a:a240:1700:c898:de98:30b3:a07]) by smtp.googlemail.com with ESMTPSA id n11-20020ac2490b000000b004979df1c1fasm994280lfi.61.2022.10.26.15.32.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 15:32:52 -0700 (PDT) From: Mateusz Kwiatkowski X-Google-Original-From: Mateusz Kwiatkowski Message-ID: Date: Thu, 27 Oct 2022 00:32:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards Content-Language: pl To: maxime@cerno.tech, Karol Herbst , Emma Anholt , Ben Skeggs , Chen-Yu Tsai , Rodrigo Vivi , Maarten Lankhorst , Jani Nikula , Daniel Vetter , Thomas Zimmermann , Tvrtko Ursulin , Samuel Holland , Jernej Skrabec , David Airlie , Maxime Ripard , Joonas Lahtinen , Lyude Paul References: <20220728-rpi-analog-tv-properties-v6-0-e7792734108f@cerno.tech> <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> In-Reply-To: <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dom Cobley , Dave Stevenson , nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Phil Elwell , Hans de Goede , =?UTF-8?Q?Noralf_Tr=c3=b8nnes?= , Geert Uytterhoeven , linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Maxime, I've seen that you've incorporated my PAL60 patch. Thanks! I still yet need to test your v6 changes, but looking at this code with just my mental static analysis, it seems to me that the vc4_vec_encoder_atomic_check() should have the tv_mode validation. I should've added it to the PAL60 patch, but it somehow slipped my mind then. Anyway, I mentioned it previously here: https://lore.kernel.org/dri-devel/0f2beec2-ae8e-5579-f0b6-a73d9dae1af4@gmail.com/ It would look something like this, inside vc4_vec_encoder_atomic_check(): + const struct vc4_vec_tv_mode *tv_mode = + vc4_vec_tv_mode_lookup(conn_state->tv.mode); + + if (!tv_mode) + return -EINVAL; Without this, it's possible to set e.g. 480i mode and SECAM, which will fail - but with the current version it will only fail in vc4_vec_encoder_enable(), which cannot return an error, and in my experience that causes a rather lengthy lockup. But, like I said, I still need to actually test that with this version. Anyway, I was also thinking about adding support for the more "exotic" non-standard modes. NTSC-50 is, unfortunately, impossible with VEC, but PAL-N-60 and PAL-M-50 should work. The necessary vc4_vec_tv_modes entries would look something like: @@ -325,12 +325,28 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { .config0 = VEC_CONFIG0_PAL_M_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-M-50 */ + .mode = DRM_MODE_TV_MODE_PAL, + .expected_htotal = 864, + .config0 = VEC_CONFIG0_PAL_BDGHI_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21e6efe3, + }, { .mode = DRM_MODE_TV_MODE_PAL_N, .expected_htotal = 864, .config0 = VEC_CONFIG0_PAL_N_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-N-60 */ + .mode = DRM_MODE_TV_MODE_PAL_N, + .expected_htotal = 858, + .config0 = VEC_CONFIG0_PAL_M_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21f69446, + }, { .mode = DRM_MODE_TV_MODE_SECAM, .expected_htotal = 864, I'm not sure if we actually want to add that. The two arguments for doing so I can think of is 1. it should work, so "why not", 2. it means that more modes will result in _some_ kind of a valid signal, rather than erroring out, which is always a plus in my book. I can also think of a hypothetical use case, like someone in South America with an old PAL-N-only set that would nevertheless still sync at 60 Hz (perhaps with the help of messing with vertical hold knob), who would like to play retro games at 60 Hz in color. But on the other hand, I admit that this scenario is likely a stretch and the number of people who would actually use it is probably close to the proverbial two ;) So it's your call, I'm just leaving those settings here just in case. I'll get back in a couple of days when I do some testing of this v6 patchset. Best regards, Mateusz Kwiatkowski W dniu 26.10.2022 o 17:33, maxime@cerno.tech pisze: > From: Mateusz Kwiatkowski > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Acked-by: Noralf Trønnes > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > > --- > Changes in v6: > - Support PAL60 again > --- > drivers/gpu/drm/vc4/vc4_vec.c | 111 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 107 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c > index 1dda451c8def..d82aef168075 100644 > --- a/drivers/gpu/drm/vc4/vc4_vec.c > +++ b/drivers/gpu/drm/vc4/vc4_vec.c > @@ -46,6 +46,7 @@ > #define VEC_CONFIG0_YDEL(x) ((x) << 26) > #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) > #define VEC_CONFIG0_CDEL(x) ((x) << 24) > +#define VEC_CONFIG0_SECAM_STD BIT(21) > #define VEC_CONFIG0_PBPR_FIL BIT(18) > #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) > #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) > @@ -76,6 +77,27 @@ > #define VEC_SOFT_RESET 0x10c > #define VEC_CLMP0_START 0x144 > #define VEC_CLMP0_END 0x148 > + > +/* > + * These set the color subcarrier frequency > + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. > + * > + * VEC_FREQ1_0 contains the most significant 16-bit half-word, > + * VEC_FREQ3_2 contains the least significant 16-bit half-word. > + * 0x80000000 seems to be equivalent to the pixel clock > + * (which itself is the VEC clock divided by 8). > + * > + * Reference values (with the default pixel clock of 13.5 MHz): > + * > + * NTSC (3579545.[45] Hz) - 0x21F07C1F > + * PAL (4433618.75 Hz) - 0x2A098ACB > + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 > + * PAL-N (3582056.25 Hz) - 0x21F69446 > + * > + * NOTE: For SECAM, it is used as the Dr center frequency, > + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; > + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. > + */ > #define VEC_FREQ3_2 0x180 > #define VEC_FREQ1_0 0x184 > > @@ -118,6 +140,14 @@ > > #define VEC_INTERRUPT_CONTROL 0x190 > #define VEC_INTERRUPT_STATUS 0x194 > + > +/* > + * Db center frequency for SECAM; the clock for this is the same as for > + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. > + * > + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. > + * That is also the default value, so no need to set it explicitly. > + */ > #define VEC_FCW_SECAM_B 0x198 > #define VEC_SECAM_GAIN_VAL 0x19c > > @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { > VC4_VEC_TV_MODE_NTSC_J, > VC4_VEC_TV_MODE_PAL, > VC4_VEC_TV_MODE_PAL_M, > + VC4_VEC_TV_MODE_NTSC_443, > + VC4_VEC_TV_MODE_PAL_60, > + VC4_VEC_TV_MODE_PAL_N, > + VC4_VEC_TV_MODE_SECAM, > }; > > struct vc4_vec_tv_mode { > unsigned int mode; > + u16 expected_htotal; > u32 config0; > u32 config1; > u32 custom_freq; > @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { > static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { > { > .mode = DRM_MODE_TV_MODE_NTSC, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_NTSC_443, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_NTSC_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_NTSC_J, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > { > .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 864, > .config0 = VEC_CONFIG0_PAL_BDGHI_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + /* PAL-60 */ > + .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_PAL_M_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_PAL_M, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_PAL_M_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_PAL_N, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_PAL_N_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + }, > + { > + .mode = DRM_MODE_TV_MODE_SECAM, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_SECAM_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + .custom_freq = 0x29c71c72, > + }, > }; > > static inline const struct vc4_vec_tv_mode * > -vc4_vec_tv_mode_lookup(unsigned int mode) > +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) > { > unsigned int i; > > for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { > const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; > > - if (tv_mode->mode == mode) > + if (tv_mode->mode == mode && > + tv_mode->expected_htotal == htotal) > return tv_mode; > } > > @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) > > static const struct drm_prop_enum_list legacy_tv_mode_names[] = { > { VC4_VEC_TV_MODE_NTSC, "NTSC", }, > + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, > { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, > { VC4_VEC_TV_MODE_PAL, "PAL", }, > + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, > { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, > + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, > + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, > }; > > static enum drm_connector_status > @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_NTSC; > break; > > + case VC4_VEC_TV_MODE_NTSC_443: > + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; > + break; > + > case VC4_VEC_TV_MODE_NTSC_J: > state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; > break; > > case VC4_VEC_TV_MODE_PAL: > + case VC4_VEC_TV_MODE_PAL_60: > state->tv.mode = DRM_MODE_TV_MODE_PAL; > break; > > @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_PAL_M; > break; > > + case VC4_VEC_TV_MODE_PAL_N: > + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; > + break; > + > + case VC4_VEC_TV_MODE_SECAM: > + state->tv.mode = DRM_MODE_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_NTSC; > break; > > + case DRM_MODE_TV_MODE_NTSC_443: > + *val = VC4_VEC_TV_MODE_NTSC_443; > + break; > + > case DRM_MODE_TV_MODE_NTSC_J: > *val = VC4_VEC_TV_MODE_NTSC_J; > break; > @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_PAL_M; > break; > > + case DRM_MODE_TV_MODE_PAL_N: > + *val = VC4_VEC_TV_MODE_PAL_N; > + break; > + > + case DRM_MODE_TV_MODE_SECAM: > + *val = VC4_VEC_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, > struct drm_connector *connector = &vec->connector; > struct drm_connector_state *conn_state = > drm_atomic_get_new_connector_state(state, connector); > + struct drm_display_mode *adjusted_mode = > + &encoder->crtc->state->adjusted_mode; > const struct vc4_vec_tv_mode *tv_mode; > int idx, ret; > > if (!drm_dev_enter(drm, &idx)) > return; > > - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); > + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, > + adjusted_mode->htotal); > if (!tv_mode) > goto err_dev_exit; > > @@ -643,9 +743,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) > > ret = drm_mode_create_tv_properties(drm, > BIT(DRM_MODE_TV_MODE_NTSC) | > + BIT(DRM_MODE_TV_MODE_NTSC_443) | > BIT(DRM_MODE_TV_MODE_NTSC_J) | > BIT(DRM_MODE_TV_MODE_PAL) | > - BIT(DRM_MODE_TV_MODE_PAL_M)); > + BIT(DRM_MODE_TV_MODE_PAL_M) | > + BIT(DRM_MODE_TV_MODE_PAL_N) | > + BIT(DRM_MODE_TV_MODE_SECAM)); > if (ret) > return ret; > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 782A1C433FE for ; Wed, 26 Oct 2022 22:32:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB15210E2A3; Wed, 26 Oct 2022 22:32:57 +0000 (UTC) Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAACC10E2A3; Wed, 26 Oct 2022 22:32:54 +0000 (UTC) Received: by mail-lf1-x132.google.com with SMTP id p8so31751353lfu.11; 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([2a02:a31a:a240:1700:c898:de98:30b3:a07]) by smtp.googlemail.com with ESMTPSA id n11-20020ac2490b000000b004979df1c1fasm994280lfi.61.2022.10.26.15.32.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 15:32:52 -0700 (PDT) From: Mateusz Kwiatkowski X-Google-Original-From: Mateusz Kwiatkowski Message-ID: Date: Thu, 27 Oct 2022 00:32:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Content-Language: pl To: maxime@cerno.tech, Karol Herbst , Emma Anholt , Ben Skeggs , Chen-Yu Tsai , Rodrigo Vivi , Maarten Lankhorst , Jani Nikula , Daniel Vetter , Thomas Zimmermann , Tvrtko Ursulin , Samuel Holland , Jernej Skrabec , David Airlie , Maxime Ripard , Joonas Lahtinen , Lyude Paul References: <20220728-rpi-analog-tv-properties-v6-0-e7792734108f@cerno.tech> <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> In-Reply-To: <20220728-rpi-analog-tv-properties-v6-22-e7792734108f@cerno.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dom Cobley , Dave Stevenson , nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Phil Elwell , Hans de Goede , =?UTF-8?Q?Noralf_Tr=c3=b8nnes?= , Geert Uytterhoeven , linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Maxime, I've seen that you've incorporated my PAL60 patch. Thanks! I still yet need to test your v6 changes, but looking at this code with just my mental static analysis, it seems to me that the vc4_vec_encoder_atomic_check() should have the tv_mode validation. I should've added it to the PAL60 patch, but it somehow slipped my mind then. Anyway, I mentioned it previously here: https://lore.kernel.org/dri-devel/0f2beec2-ae8e-5579-f0b6-a73d9dae1af4@gmail.com/ It would look something like this, inside vc4_vec_encoder_atomic_check(): + const struct vc4_vec_tv_mode *tv_mode = + vc4_vec_tv_mode_lookup(conn_state->tv.mode); + + if (!tv_mode) + return -EINVAL; Without this, it's possible to set e.g. 480i mode and SECAM, which will fail - but with the current version it will only fail in vc4_vec_encoder_enable(), which cannot return an error, and in my experience that causes a rather lengthy lockup. But, like I said, I still need to actually test that with this version. Anyway, I was also thinking about adding support for the more "exotic" non-standard modes. NTSC-50 is, unfortunately, impossible with VEC, but PAL-N-60 and PAL-M-50 should work. The necessary vc4_vec_tv_modes entries would look something like: @@ -325,12 +325,28 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { .config0 = VEC_CONFIG0_PAL_M_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-M-50 */ + .mode = DRM_MODE_TV_MODE_PAL, + .expected_htotal = 864, + .config0 = VEC_CONFIG0_PAL_BDGHI_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21e6efe3, + }, { .mode = DRM_MODE_TV_MODE_PAL_N, .expected_htotal = 864, .config0 = VEC_CONFIG0_PAL_N_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-N-60 */ + .mode = DRM_MODE_TV_MODE_PAL_N, + .expected_htotal = 858, + .config0 = VEC_CONFIG0_PAL_M_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x21f69446, + }, { .mode = DRM_MODE_TV_MODE_SECAM, .expected_htotal = 864, I'm not sure if we actually want to add that. The two arguments for doing so I can think of is 1. it should work, so "why not", 2. it means that more modes will result in _some_ kind of a valid signal, rather than erroring out, which is always a plus in my book. I can also think of a hypothetical use case, like someone in South America with an old PAL-N-only set that would nevertheless still sync at 60 Hz (perhaps with the help of messing with vertical hold knob), who would like to play retro games at 60 Hz in color. But on the other hand, I admit that this scenario is likely a stretch and the number of people who would actually use it is probably close to the proverbial two ;) So it's your call, I'm just leaving those settings here just in case. I'll get back in a couple of days when I do some testing of this v6 patchset. Best regards, Mateusz Kwiatkowski W dniu 26.10.2022 o 17:33, maxime@cerno.tech pisze: > From: Mateusz Kwiatkowski > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Acked-by: Noralf Trønnes > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > > --- > Changes in v6: > - Support PAL60 again > --- > drivers/gpu/drm/vc4/vc4_vec.c | 111 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 107 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c > index 1dda451c8def..d82aef168075 100644 > --- a/drivers/gpu/drm/vc4/vc4_vec.c > +++ b/drivers/gpu/drm/vc4/vc4_vec.c > @@ -46,6 +46,7 @@ > #define VEC_CONFIG0_YDEL(x) ((x) << 26) > #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) > #define VEC_CONFIG0_CDEL(x) ((x) << 24) > +#define VEC_CONFIG0_SECAM_STD BIT(21) > #define VEC_CONFIG0_PBPR_FIL BIT(18) > #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) > #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) > @@ -76,6 +77,27 @@ > #define VEC_SOFT_RESET 0x10c > #define VEC_CLMP0_START 0x144 > #define VEC_CLMP0_END 0x148 > + > +/* > + * These set the color subcarrier frequency > + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. > + * > + * VEC_FREQ1_0 contains the most significant 16-bit half-word, > + * VEC_FREQ3_2 contains the least significant 16-bit half-word. > + * 0x80000000 seems to be equivalent to the pixel clock > + * (which itself is the VEC clock divided by 8). > + * > + * Reference values (with the default pixel clock of 13.5 MHz): > + * > + * NTSC (3579545.[45] Hz) - 0x21F07C1F > + * PAL (4433618.75 Hz) - 0x2A098ACB > + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 > + * PAL-N (3582056.25 Hz) - 0x21F69446 > + * > + * NOTE: For SECAM, it is used as the Dr center frequency, > + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; > + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. > + */ > #define VEC_FREQ3_2 0x180 > #define VEC_FREQ1_0 0x184 > > @@ -118,6 +140,14 @@ > > #define VEC_INTERRUPT_CONTROL 0x190 > #define VEC_INTERRUPT_STATUS 0x194 > + > +/* > + * Db center frequency for SECAM; the clock for this is the same as for > + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. > + * > + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. > + * That is also the default value, so no need to set it explicitly. > + */ > #define VEC_FCW_SECAM_B 0x198 > #define VEC_SECAM_GAIN_VAL 0x19c > > @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { > VC4_VEC_TV_MODE_NTSC_J, > VC4_VEC_TV_MODE_PAL, > VC4_VEC_TV_MODE_PAL_M, > + VC4_VEC_TV_MODE_NTSC_443, > + VC4_VEC_TV_MODE_PAL_60, > + VC4_VEC_TV_MODE_PAL_N, > + VC4_VEC_TV_MODE_SECAM, > }; > > struct vc4_vec_tv_mode { > unsigned int mode; > + u16 expected_htotal; > u32 config0; > u32 config1; > u32 custom_freq; > @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { > static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { > { > .mode = DRM_MODE_TV_MODE_NTSC, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_NTSC_443, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_NTSC_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_NTSC_J, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > { > .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 864, > .config0 = VEC_CONFIG0_PAL_BDGHI_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + /* PAL-60 */ > + .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_PAL_M_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_PAL_M, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_PAL_M_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_PAL_N, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_PAL_N_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + }, > + { > + .mode = DRM_MODE_TV_MODE_SECAM, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_SECAM_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + .custom_freq = 0x29c71c72, > + }, > }; > > static inline const struct vc4_vec_tv_mode * > -vc4_vec_tv_mode_lookup(unsigned int mode) > +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) > { > unsigned int i; > > for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { > const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; > > - if (tv_mode->mode == mode) > + if (tv_mode->mode == mode && > + tv_mode->expected_htotal == htotal) > return tv_mode; > } > > @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) > > static const struct drm_prop_enum_list legacy_tv_mode_names[] = { > { VC4_VEC_TV_MODE_NTSC, "NTSC", }, > + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, > { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, > { VC4_VEC_TV_MODE_PAL, "PAL", }, > + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, > { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, > + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, > + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, > }; > > static enum drm_connector_status > @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_NTSC; > break; > > + case VC4_VEC_TV_MODE_NTSC_443: > + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; > + break; > + > case VC4_VEC_TV_MODE_NTSC_J: > state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; > break; > > case VC4_VEC_TV_MODE_PAL: > + case VC4_VEC_TV_MODE_PAL_60: > state->tv.mode = DRM_MODE_TV_MODE_PAL; > break; > > @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_PAL_M; > break; > > + case VC4_VEC_TV_MODE_PAL_N: > + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; > + break; > + > + case VC4_VEC_TV_MODE_SECAM: > + state->tv.mode = DRM_MODE_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_NTSC; > break; > > + case DRM_MODE_TV_MODE_NTSC_443: > + *val = VC4_VEC_TV_MODE_NTSC_443; > + break; > + > case DRM_MODE_TV_MODE_NTSC_J: > *val = VC4_VEC_TV_MODE_NTSC_J; > break; > @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_PAL_M; > break; > > + case DRM_MODE_TV_MODE_PAL_N: > + *val = VC4_VEC_TV_MODE_PAL_N; > + break; > + > + case DRM_MODE_TV_MODE_SECAM: > + *val = VC4_VEC_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, > struct drm_connector *connector = &vec->connector; > struct drm_connector_state *conn_state = > drm_atomic_get_new_connector_state(state, connector); > + struct drm_display_mode *adjusted_mode = > + &encoder->crtc->state->adjusted_mode; > const struct vc4_vec_tv_mode *tv_mode; > int idx, ret; > > if (!drm_dev_enter(drm, &idx)) > return; > > - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); > + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, > + adjusted_mode->htotal); > if (!tv_mode) > goto err_dev_exit; > > @@ -643,9 +743,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) > > ret = drm_mode_create_tv_properties(drm, > BIT(DRM_MODE_TV_MODE_NTSC) | > + BIT(DRM_MODE_TV_MODE_NTSC_443) | > BIT(DRM_MODE_TV_MODE_NTSC_J) | > BIT(DRM_MODE_TV_MODE_PAL) | > - BIT(DRM_MODE_TV_MODE_PAL_M)); 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([2a02:a31a:a240:1700:c898:de98:30b3:a07]) by smtp.googlemail.com with ESMTPSA id n11-20020ac2490b000000b004979df1c1fasm994280lfi.61.2022.10.26.15.32.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 15:32:52 -0700 (PDT) From: Mateusz Kwiatkowski X-Google-Original-From: Mateusz Kwiatkowski Message-ID: Date: Thu, 27 Oct 2022 00:32:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards Content-Language: pl To: maxime@cerno.tech, Karol Herbst , Emma Anholt , Ben Skeggs , Chen-Yu Tsai , Rodrigo Vivi , Maarten Lankhorst , Jani Nikula , Daniel Vetter , Thomas Zimmermann , Tvrtko Ursulin , Samuel Holland , Jernej Skrabec , David Airlie , Maxime Ripard , Joonas Lahtinen , Lyude Paul Cc: linux-sunxi@lists.linux.dev, intel-gfx@lists.freedesktop.org, Phil Elwell , linux-arm-kernel@lists.infradead.org, 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SGkgTWF4aW1lLAoKSSd2ZSBzZWVuIHRoYXQgeW91J3ZlIGluY29ycG9yYXRlZCBteSBQQUw2MCBw YXRjaC4gVGhhbmtzIQoKSSBzdGlsbCB5ZXQgbmVlZCB0byB0ZXN0IHlvdXIgdjYgY2hhbmdlcywg YnV0IGxvb2tpbmcgYXQgdGhpcyBjb2RlIHdpdGgganVzdCBteQptZW50YWwgc3RhdGljIGFuYWx5 c2lzLCBpdCBzZWVtcyB0byBtZSB0aGF0IHRoZSB2YzRfdmVjX2VuY29kZXJfYXRvbWljX2NoZWNr KCkKc2hvdWxkIGhhdmUgdGhlIHR2X21vZGUgdmFsaWRhdGlvbi4gSSBzaG91bGQndmUgYWRkZWQg aXQgdG8gdGhlIFBBTDYwIHBhdGNoLApidXQgaXQgc29tZWhvdyBzbGlwcGVkIG15IG1pbmQgdGhl bi4KCkFueXdheSwgSSBtZW50aW9uZWQgaXQgcHJldmlvdXNseSBoZXJlOgpodHRwczovL2xvcmUu a2VybmVsLm9yZy9kcmktZGV2ZWwvMGYyYmVlYzItYWU4ZS01NTc5LWYwYjYtYTczZDlkYWUxYWY0 QGdtYWlsLmNvbS8KCkl0IHdvdWxkIGxvb2sgc29tZXRoaW5nIGxpa2UgdGhpcywgaW5zaWRlIHZj NF92ZWNfZW5jb2Rlcl9hdG9taWNfY2hlY2soKToKCisJY29uc3Qgc3RydWN0IHZjNF92ZWNfdHZf bW9kZSAqdHZfbW9kZSA9CisJCXZjNF92ZWNfdHZfbW9kZV9sb29rdXAoY29ubl9zdGF0ZS0+dHYu bW9kZSk7CisKKwlpZiAoIXR2X21vZGUpCisJCXJldHVybiAtRUlOVkFMOwoKV2l0aG91dCB0aGlz LCBpdCdzIHBvc3NpYmxlIHRvIHNldCBlLmcuIDQ4MGkgbW9kZSBhbmQgU0VDQU0sIHdoaWNoIHdp bGwgZmFpbCAtCmJ1dCB3aXRoIHRoZSBjdXJyZW50IHZlcnNpb24gaXQgd2lsbCBvbmx5IGZhaWwg aW4gdmM0X3ZlY19lbmNvZGVyX2VuYWJsZSgpLAp3aGljaCBjYW5ub3QgcmV0dXJuIGFuIGVycm9y LCBhbmQgaW4gbXkgZXhwZXJpZW5jZSB0aGF0IGNhdXNlcyBhIHJhdGhlciBsZW5ndGh5CmxvY2t1 cC4KCkJ1dCwgbGlrZSBJIHNhaWQsIEkgc3RpbGwgbmVlZCB0byBhY3R1YWxseSB0ZXN0IHRoYXQg d2l0aCB0aGlzIHZlcnNpb24uCgpBbnl3YXksIEkgd2FzIGFsc28gdGhpbmtpbmcgYWJvdXQgYWRk aW5nIHN1cHBvcnQgZm9yIHRoZSBtb3JlICJleG90aWMiCm5vbi1zdGFuZGFyZCBtb2Rlcy4gTlRT Qy01MCBpcywgdW5mb3J0dW5hdGVseSwgaW1wb3NzaWJsZSB3aXRoIFZFQywgYnV0ClBBTC1OLTYw IGFuZCBQQUwtTS01MCBzaG91bGQgd29yay4gVGhlIG5lY2Vzc2FyeSB2YzRfdmVjX3R2X21vZGVz IGVudHJpZXMgd291bGQKbG9vayBzb21ldGhpbmcgbGlrZToKCkBAIC0zMjUsMTIgKzMyNSwyOCBA QCBzdGF0aWMgY29uc3Qgc3RydWN0IHZjNF92ZWNfdHZfbW9kZSB2YzRfdmVjX3R2X21vZGVzW10g PSB7CiAJCS5jb25maWcwID0gVkVDX0NPTkZJRzBfUEFMX01fU1RELAogCQkuY29uZmlnMSA9IFZF Q19DT05GSUcxX0NfQ1ZCU19DVkJTLAogCX0sCisJeworCQkvKiBQQUwtTS01MCAqLworCQkubW9k ZSA9IERSTV9NT0RFX1RWX01PREVfUEFMLAorCQkuZXhwZWN0ZWRfaHRvdGFsID0gODY0LAorCQku Y29uZmlnMCA9IFZFQ19DT05GSUcwX1BBTF9CREdISV9TVEQsCisJCS5jb25maWcxID0gVkVDX0NP TkZJRzFfQ19DVkJTX0NWQlMgfCBWRUNfQ09ORklHMV9DVVNUT01fRlJFUSwKKwkJLmN1c3RvbV9m cmVxID0gMHgyMWU2ZWZlMywKKwl9LAogCXsKIAkJLm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX1BB TF9OLAogCQkuZXhwZWN0ZWRfaHRvdGFsID0gODY0LAogCQkuY29uZmlnMCA9IFZFQ19DT05GSUcw X1BBTF9OX1NURCwKIAkJLmNvbmZpZzEgPSBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUywKIAl9LAor CXsKKwkJLyogUEFMLU4tNjAgKi8KKwkJLm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX1BBTF9OLAor CQkuZXhwZWN0ZWRfaHRvdGFsID0gODU4LAorCQkuY29uZmlnMCA9IFZFQ19DT05GSUcwX1BBTF9N X1NURCwKKwkJLmNvbmZpZzEgPSBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUyB8IFZFQ19DT05GSUcx X0NVU1RPTV9GUkVRLAorCQkuY3VzdG9tX2ZyZXEgPSAweDIxZjY5NDQ2LAorCX0sCiAJewogCQku bW9kZSA9IERSTV9NT0RFX1RWX01PREVfU0VDQU0sCiAJCS5leHBlY3RlZF9odG90YWwgPSA4NjQs CgpJJ20gbm90IHN1cmUgaWYgd2UgYWN0dWFsbHkgd2FudCB0byBhZGQgdGhhdC4gVGhlIHR3byBh cmd1bWVudHMgZm9yIGRvaW5nIHNvCkkgY2FuIHRoaW5rIG9mIGlzIDEuIGl0IHNob3VsZCB3b3Jr LCBzbyAid2h5IG5vdCIsIDIuIGl0IG1lYW5zIHRoYXQgbW9yZSBtb2Rlcwp3aWxsIHJlc3VsdCBp biBfc29tZV8ga2luZCBvZiBhIHZhbGlkIHNpZ25hbCwgcmF0aGVyIHRoYW4gZXJyb3Jpbmcgb3V0 LCB3aGljaAppcyBhbHdheXMgYSBwbHVzIGluIG15IGJvb2suIEkgY2FuIGFsc28gdGhpbmsgb2Yg YSBoeXBvdGhldGljYWwgdXNlIGNhc2UsIGxpa2UKc29tZW9uZSBpbiBTb3V0aCBBbWVyaWNhIHdp dGggYW4gb2xkIFBBTC1OLW9ubHkgc2V0IHRoYXQgd291bGQgbmV2ZXJ0aGVsZXNzCnN0aWxsIHN5 bmMgYXQgNjAgSHogKHBlcmhhcHMgd2l0aCB0aGUgaGVscCBvZiBtZXNzaW5nIHdpdGggdmVydGlj YWwgaG9sZCBrbm9iKSwKd2hvIHdvdWxkIGxpa2UgdG8gcGxheSByZXRybyBnYW1lcyBhdCA2MCBI eiBpbiBjb2xvci4KCkJ1dCBvbiB0aGUgb3RoZXIgaGFuZCwgSSBhZG1pdCB0aGF0IHRoaXMgc2Nl bmFyaW8gaXMgbGlrZWx5IGEgc3RyZXRjaCBhbmQgdGhlCm51bWJlciBvZiBwZW9wbGUgd2hvIHdv dWxkIGFjdHVhbGx5IHVzZSBpdCBpcyBwcm9iYWJseSBjbG9zZSB0byB0aGUgcHJvdmVyYmlhbAp0 d28gOykgU28gaXQncyB5b3VyIGNhbGwsIEknbSBqdXN0IGxlYXZpbmcgdGhvc2Ugc2V0dGluZ3Mg aGVyZSBqdXN0IGluIGNhc2UuCgpJJ2xsIGdldCBiYWNrIGluIGEgY291cGxlIG9mIGRheXMgd2hl biBJIGRvIHNvbWUgdGVzdGluZyBvZiB0aGlzIHY2IHBhdGNoc2V0LgoKQmVzdCByZWdhcmRzLApN YXRldXN6IEt3aWF0a293c2tpCgpXIGRuaXUgMjYuMTAuMjAyMiBvIDE3OjMzLCBtYXhpbWVAY2Vy bm8udGVjaCBwaXN6ZToKPiBGcm9tOiBNYXRldXN6IEt3aWF0a293c2tpIDxrZnlhdGVrK3B1Ymxp Y2dpdEBnbWFpbC5jb20+Cj4KPiBBZGQgc3VwcG9ydCBmb3IgdGhlIGZvbGxvd2luZyBjb21wb3Np dGUgb3V0cHV0IG1vZGVzIChhbGwgb2YgdGhlbSBhcmUKPiBzb21ld2hhdCBtb3JlIG9ic2N1cmUg dGhhbiB0aGUgcHJldmlvdXNseSBkZWZpbmVkIG9uZXMpOgo+Cj4gLSBOVFNDXzQ0MyAtIE5UU0Mt c3R5bGUgc2lnbmFsIHdpdGggdGhlIGNocm9tYSBzdWJjYXJyaWVyIHNoaWZ0ZWQgdG8KPiAgIDQu NDMzNjE4NzUgTUh6ICh0aGUgUEFMIHN1YmNhcnJpZXIgZnJlcXVlbmN5KS4gTmV2ZXIgdXNlZCBm b3IKPiAgIGJyb2FkY2FzdGluZywgYnV0IHNvbWV0aW1lcyB1c2VkIGFzIGEgaGFjayB0byBwbGF5 IE5UU0MgY29udGVudCBpbiBQQUwKPiAgIHJlZ2lvbnMgKGUuZy4gb24gVkNScykuCj4gLSBQQUxf TiAtIFBBTCB3aXRoIGFsdGVybmF0aXZlIGNocm9tYSBzdWJjYXJyaWVyIGZyZXF1ZW5jeSwKPiAg IDMuNTgyMDU2MjUgTUh6LiBVc2VkIGFzIGEgYnJvYWRjYXN0IHN0YW5kYXJkIGluIEFyZ2VudGlu YSwgUGFyYWd1YXkKPiAgIGFuZCBVcnVndWF5IHRvIGZpdCA1NzZpNTAgd2l0aCBjb2xvdXIgaW4g NiBNSHogY2hhbm5lbCByYXN0ZXIuCj4gLSBQQUw2MCAtIDQ4MGk2MCBzaWduYWwgd2l0aCBQQUwt c3R5bGUgY29sb3IgYXQgbm9ybWFsIEV1cm9wZWFuIFBBTAo+ICAgZnJlcXVlbmN5LiBBbm90aGVy IG5vbi1zdGFuZGFyZCwgbm9uLWJyb2FkY2FzdCBtb2RlLCB1c2VkIGluIHNpbWlsYXIKPiAgIGNv bnRleHRzIGFzIE5UU0NfNDQzLiBTb21lIGRpc3BsYXlzIHN1cHBvcnQgb25lIGJ1dCBub3QgdGhl IG90aGVyLgo+IC0gU0VDQU0gLSBGcmVuY2ggZnJlcXVlbmN5LW1vZHVsYXRlZCBhbmFsb2cgY29s b3Igc3RhbmRhcmQ7IGFsc28gaGF2ZQo+ICAgYmVlbiBicm9hZGNhc3QgaW4gRWFzdGVybiBFdXJv cGUgYW5kIHZhcmlvdXMgcGFydHMgb2YgQWZyaWNhIGFuZCBBc2lhLgo+ICAgVXNlcyB0aGUgc2Ft ZSA1NzZpNTAgdGltaW5ncyBhcyBQQUwuCj4KPiBBbHNvIGFkZGVkIHNvbWUgY29tbWVudHMgZXhw bGFpbmluZyBjb2xvciBzdWJjYXJyaWVyIGZyZXF1ZW5jeQo+IHJlZ2lzdGVycy4KPgo+IEFja2Vk LWJ5OiBOb3JhbGYgVHLDuG5uZXMgPG5vcmFsZkB0cm9ubmVzLm9yZz4KPiBTaWduZWQtb2ZmLWJ5 OiBNYXRldXN6IEt3aWF0a293c2tpIDxrZnlhdGVrK3B1YmxpY2dpdEBnbWFpbC5jb20+Cj4gU2ln bmVkLW9mZi1ieTogTWF4aW1lIFJpcGFyZCA8bWF4aW1lQGNlcm5vLnRlY2g+Cj4KPiAtLS0KPiBD aGFuZ2VzIGluIHY2Ogo+IC0gU3VwcG9ydCBQQUw2MCBhZ2Fpbgo+IC0tLQo+ICBkcml2ZXJzL2dw dS9kcm0vdmM0L3ZjNF92ZWMuYyB8IDExMSArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDEwNyBpbnNlcnRpb25zKCspLCA0IGRlbGV0 aW9ucygtKQo+Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3ZlYy5jIGIv ZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfdmVjLmMKPiBpbmRleCAxZGRhNDUxYzhkZWYuLmQ4MmFl ZjE2ODA3NSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF92ZWMuYwo+ICsr KyBiL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3ZlYy5jCj4gQEAgLTQ2LDYgKzQ2LDcgQEAKPiAg I2RlZmluZSBWRUNfQ09ORklHMF9ZREVMKHgpCQkoKHgpIDw8IDI2KQo+ICAjZGVmaW5lIFZFQ19D T05GSUcwX0NERUxfTUFTSwkJR0VOTUFTSygyNSwgMjQpCj4gICNkZWZpbmUgVkVDX0NPTkZJRzBf Q0RFTCh4KQkJKCh4KSA8PCAyNCkKPiArI2RlZmluZSBWRUNfQ09ORklHMF9TRUNBTV9TVEQJCUJJ VCgyMSkKPiAgI2RlZmluZSBWRUNfQ09ORklHMF9QQlBSX0ZJTAkJQklUKDE4KQo+ICAjZGVmaW5l IFZFQ19DT05GSUcwX0NIUk9NQV9HQUlOX01BU0sJR0VOTUFTSygxNywgMTYpCj4gICNkZWZpbmUg VkVDX0NPTkZJRzBfQ0hST01BX0dBSU5fVU5JVFkJKDAgPDwgMTYpCj4gQEAgLTc2LDYgKzc3LDI3 IEBACj4gICNkZWZpbmUgVkVDX1NPRlRfUkVTRVQJCQkweDEwYwo+ICAjZGVmaW5lIFZFQ19DTE1Q MF9TVEFSVAkJCTB4MTQ0Cj4gICNkZWZpbmUgVkVDX0NMTVAwX0VORAkJCTB4MTQ4Cj4gKwo+ICsv Kgo+ICsgKiBUaGVzZSBzZXQgdGhlIGNvbG9yIHN1YmNhcnJpZXIgZnJlcXVlbmN5Cj4gKyAqIGlm IFZFQ19DT05GSUcxX0NVU1RPTV9GUkVRIGlzIGVuYWJsZWQuCj4gKyAqCj4gKyAqIFZFQ19GUkVR MV8wIGNvbnRhaW5zIHRoZSBtb3N0IHNpZ25pZmljYW50IDE2LWJpdCBoYWxmLXdvcmQsCj4gKyAq IFZFQ19GUkVRM18yIGNvbnRhaW5zIHRoZSBsZWFzdCBzaWduaWZpY2FudCAxNi1iaXQgaGFsZi13 b3JkLgo+ICsgKiAweDgwMDAwMDAwIHNlZW1zIHRvIGJlIGVxdWl2YWxlbnQgdG8gdGhlIHBpeGVs IGNsb2NrCj4gKyAqICh3aGljaCBpdHNlbGYgaXMgdGhlIFZFQyBjbG9jayBkaXZpZGVkIGJ5IDgp Lgo+ICsgKgo+ICsgKiBSZWZlcmVuY2UgdmFsdWVzICh3aXRoIHRoZSBkZWZhdWx0IHBpeGVsIGNs b2NrIG9mIDEzLjUgTUh6KToKPiArICoKPiArICogTlRTQyAgKDM1Nzk1NDUuWzQ1XSBIeikgICAg IC0gMHgyMUYwN0MxRgo+ICsgKiBQQUwgICAoNDQzMzYxOC43NSBIeikgICAgICAgLSAweDJBMDk4 QUNCCj4gKyAqIFBBTC1NICgzNTc1NjExLls4ODgxMTFdIEh6KSAtIDB4MjFFNkVGRTMKPiArICog UEFMLU4gKDM1ODIwNTYuMjUgSHopICAgICAgIC0gMHgyMUY2OTQ0Ngo+ICsgKgo+ICsgKiBOT1RF OiBGb3IgU0VDQU0sIGl0IGlzIHVzZWQgYXMgdGhlIERyIGNlbnRlciBmcmVxdWVuY3ksCj4gKyAq IHJlZ2FyZGxlc3Mgb2Ygd2hldGhlciBWRUNfQ09ORklHMV9DVVNUT01fRlJFUSBpcyBlbmFibGVk IG9yIG5vdDsKPiArICogdGhhdCBpcyBzcGVjaWZpZWQgYXMgNDQwNjI1MCBIeiwgd2hpY2ggY29y cmVzcG9uZHMgdG8gMHgyOUM3MUM3Mi4KPiArICovCj4gICNkZWZpbmUgVkVDX0ZSRVEzXzIJCQkw eDE4MAo+ICAjZGVmaW5lIFZFQ19GUkVRMV8wCQkJMHgxODQKPiAgCj4gQEAgLTExOCw2ICsxNDAs MTQgQEAKPiAgCj4gICNkZWZpbmUgVkVDX0lOVEVSUlVQVF9DT05UUk9MCQkweDE5MAo+ICAjZGVm aW5lIFZFQ19JTlRFUlJVUFRfU1RBVFVTCQkweDE5NAo+ICsKPiArLyoKPiArICogRGIgY2VudGVy IGZyZXF1ZW5jeSBmb3IgU0VDQU07IHRoZSBjbG9jayBmb3IgdGhpcyBpcyB0aGUgc2FtZSBhcyBm b3IKPiArICogVkVDX0ZSRVEzXzIvVkVDX0ZSRVExXzAsIHdoaWNoIGlzIHVzZWQgZm9yIERyIGNl bnRlciBmcmVxdWVuY3kuCj4gKyAqCj4gKyAqIFRoaXMgaXMgc3BlY2lmaWVkIGFzIDQyNTAwMDAg SHosIHdoaWNoIGNvcnJlc3BvbmRzIHRvIDB4Mjg0QkRBMTMuCj4gKyAqIFRoYXQgaXMgYWxzbyB0 aGUgZGVmYXVsdCB2YWx1ZSwgc28gbm8gbmVlZCB0byBzZXQgaXQgZXhwbGljaXRseS4KPiArICov Cj4gICNkZWZpbmUgVkVDX0ZDV19TRUNBTV9CCQkJMHgxOTgKPiAgI2RlZmluZSBWRUNfU0VDQU1f R0FJTl9WQUwJCTB4MTljCj4gIAo+IEBAIC0xOTcsMTAgKzIyNywxNSBAQCBlbnVtIHZjNF92ZWNf dHZfbW9kZV9pZCB7Cj4gIAlWQzRfVkVDX1RWX01PREVfTlRTQ19KLAo+ICAJVkM0X1ZFQ19UVl9N T0RFX1BBTCwKPiAgCVZDNF9WRUNfVFZfTU9ERV9QQUxfTSwKPiArCVZDNF9WRUNfVFZfTU9ERV9O VFNDXzQ0MywKPiArCVZDNF9WRUNfVFZfTU9ERV9QQUxfNjAsCj4gKwlWQzRfVkVDX1RWX01PREVf UEFMX04sCj4gKwlWQzRfVkVDX1RWX01PREVfU0VDQU0sCj4gIH07Cj4gIAo+ICBzdHJ1Y3QgdmM0 X3ZlY190dl9tb2RlIHsKPiAgCXVuc2lnbmVkIGludCBtb2RlOwo+ICsJdTE2IGV4cGVjdGVkX2h0 b3RhbDsKPiAgCXUzMiBjb25maWcwOwo+ICAJdTMyIGNvbmZpZzE7Cj4gIAl1MzIgY3VzdG9tX2Zy ZXE7Cj4gQEAgLTIzNiwzNSArMjcxLDY4IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZGVidWdmc19y ZWczMiB2ZWNfcmVnc1tdID0gewo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IHZjNF92ZWNfdHZfbW9k ZSB2YzRfdmVjX3R2X21vZGVzW10gPSB7Cj4gIAl7Cj4gIAkJLm1vZGUgPSBEUk1fTU9ERV9UVl9N T0RFX05UU0MsCj4gKwkJLmV4cGVjdGVkX2h0b3RhbCA9IDg1OCwKPiAgCQkuY29uZmlnMCA9IFZF Q19DT05GSUcwX05UU0NfU1REIHwgVkVDX0NPTkZJRzBfUERFTiwKPiAgCQkuY29uZmlnMSA9IFZF Q19DT05GSUcxX0NfQ1ZCU19DVkJTLAo+ICAJfSwKPiArCXsKPiArCQkubW9kZSA9IERSTV9NT0RF X1RWX01PREVfTlRTQ180NDMsCj4gKwkJLmV4cGVjdGVkX2h0b3RhbCA9IDg1OCwKPiArCQkuY29u ZmlnMCA9IFZFQ19DT05GSUcwX05UU0NfU1RELAo+ICsJCS5jb25maWcxID0gVkVDX0NPTkZJRzFf Q19DVkJTX0NWQlMgfCBWRUNfQ09ORklHMV9DVVNUT01fRlJFUSwKPiArCQkuY3VzdG9tX2ZyZXEg PSAweDJhMDk4YWNiLAo+ICsJfSwKPiAgCXsKPiAgCQkubW9kZSA9IERSTV9NT0RFX1RWX01PREVf TlRTQ19KLAo+ICsJCS5leHBlY3RlZF9odG90YWwgPSA4NTgsCj4gIAkJLmNvbmZpZzAgPSBWRUNf Q09ORklHMF9OVFNDX1NURCwKPiAgCQkuY29uZmlnMSA9IFZFQ19DT05GSUcxX0NfQ1ZCU19DVkJT LAo+ICAJfSwKPiAgCXsKPiAgCQkubW9kZSA9IERSTV9NT0RFX1RWX01PREVfUEFMLAo+ICsJCS5l eHBlY3RlZF9odG90YWwgPSA4NjQsCj4gIAkJLmNvbmZpZzAgPSBWRUNfQ09ORklHMF9QQUxfQkRH SElfU1RELAo+ICAJCS5jb25maWcxID0gVkVDX0NPTkZJRzFfQ19DVkJTX0NWQlMsCj4gIAl9LAo+ ICsJewo+ICsJCS8qIFBBTC02MCAqLwo+ICsJCS5tb2RlID0gRFJNX01PREVfVFZfTU9ERV9QQUws Cj4gKwkJLmV4cGVjdGVkX2h0b3RhbCA9IDg1OCwKPiArCQkuY29uZmlnMCA9IFZFQ19DT05GSUcw X1BBTF9NX1NURCwKPiArCQkuY29uZmlnMSA9IFZFQ19DT05GSUcxX0NfQ1ZCU19DVkJTIHwgVkVD X0NPTkZJRzFfQ1VTVE9NX0ZSRVEsCj4gKwkJLmN1c3RvbV9mcmVxID0gMHgyYTA5OGFjYiwKPiAr CX0sCj4gIAl7Cj4gIAkJLm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX1BBTF9NLAo+ICsJCS5leHBl Y3RlZF9odG90YWwgPSA4NTgsCj4gIAkJLmNvbmZpZzAgPSBWRUNfQ09ORklHMF9QQUxfTV9TVEQs Cj4gIAkJLmNvbmZpZzEgPSBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUywKPiAgCX0sCj4gKwl7Cj4g KwkJLm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX1BBTF9OLAo+ICsJCS5leHBlY3RlZF9odG90YWwg PSA4NjQsCj4gKwkJLmNvbmZpZzAgPSBWRUNfQ09ORklHMF9QQUxfTl9TVEQsCj4gKwkJLmNvbmZp ZzEgPSBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUywKPiArCX0sCj4gKwl7Cj4gKwkJLm1vZGUgPSBE Uk1fTU9ERV9UVl9NT0RFX1NFQ0FNLAo+ICsJCS5leHBlY3RlZF9odG90YWwgPSA4NjQsCj4gKwkJ LmNvbmZpZzAgPSBWRUNfQ09ORklHMF9TRUNBTV9TVEQsCj4gKwkJLmNvbmZpZzEgPSBWRUNfQ09O RklHMV9DX0NWQlNfQ1ZCUywKPiArCQkuY3VzdG9tX2ZyZXEgPSAweDI5YzcxYzcyLAo+ICsJfSwK PiAgfTsKPiAgCj4gIHN0YXRpYyBpbmxpbmUgY29uc3Qgc3RydWN0IHZjNF92ZWNfdHZfbW9kZSAq Cj4gLXZjNF92ZWNfdHZfbW9kZV9sb29rdXAodW5zaWduZWQgaW50IG1vZGUpCj4gK3ZjNF92ZWNf dHZfbW9kZV9sb29rdXAodW5zaWduZWQgaW50IG1vZGUsIHUxNiBodG90YWwpCj4gIHsKPiAgCXVu c2lnbmVkIGludCBpOwo+ICAKPiAgCWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHZjNF92ZWNf dHZfbW9kZXMpOyBpKyspIHsKPiAgCQljb25zdCBzdHJ1Y3QgdmM0X3ZlY190dl9tb2RlICp0dl9t b2RlID0gJnZjNF92ZWNfdHZfbW9kZXNbaV07Cj4gIAo+IC0JCWlmICh0dl9tb2RlLT5tb2RlID09 IG1vZGUpCj4gKwkJaWYgKHR2X21vZGUtPm1vZGUgPT0gbW9kZSAmJgo+ICsJCSAgICB0dl9tb2Rl LT5leHBlY3RlZF9odG90YWwgPT0gaHRvdGFsKQo+ICAJCQlyZXR1cm4gdHZfbW9kZTsKPiAgCX0K PiAgCj4gQEAgLTI3Myw5ICszNDEsMTMgQEAgdmM0X3ZlY190dl9tb2RlX2xvb2t1cCh1bnNpZ25l ZCBpbnQgbW9kZSkKPiAgCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX3Byb3BfZW51bV9saXN0 IGxlZ2FjeV90dl9tb2RlX25hbWVzW10gPSB7Cj4gIAl7IFZDNF9WRUNfVFZfTU9ERV9OVFNDLCAi TlRTQyIsIH0sCj4gKwl7IFZDNF9WRUNfVFZfTU9ERV9OVFNDXzQ0MywgIk5UU0MtNDQzIiwgfSwK PiAgCXsgVkM0X1ZFQ19UVl9NT0RFX05UU0NfSiwgIk5UU0MtSiIsIH0sCj4gIAl7IFZDNF9WRUNf VFZfTU9ERV9QQUwsICJQQUwiLCB9LAo+ICsJeyBWQzRfVkVDX1RWX01PREVfUEFMXzYwLCAiUEFM LTYwIiwgfSwKPiAgCXsgVkM0X1ZFQ19UVl9NT0RFX1BBTF9NLCAiUEFMLU0iLCB9LAo+ICsJeyBW QzRfVkVDX1RWX01PREVfUEFMX04sICJQQUwtTiIsIH0sCj4gKwl7IFZDNF9WRUNfVFZfTU9ERV9T RUNBTSwgIlNFQ0FNIiwgfSwKPiAgfTsKPiAgCj4gIHN0YXRpYyBlbnVtIGRybV9jb25uZWN0b3Jf c3RhdHVzCj4gQEAgLTMwNiwxMSArMzc4LDE2IEBAIHZjNF92ZWNfY29ubmVjdG9yX3NldF9wcm9w ZXJ0eShzdHJ1Y3QgZHJtX2Nvbm5lY3RvciAqY29ubmVjdG9yLAo+ICAJCXN0YXRlLT50di5tb2Rl ID0gRFJNX01PREVfVFZfTU9ERV9OVFNDOwo+ICAJCWJyZWFrOwo+ICAKPiArCWNhc2UgVkM0X1ZF Q19UVl9NT0RFX05UU0NfNDQzOgo+ICsJCXN0YXRlLT50di5tb2RlID0gRFJNX01PREVfVFZfTU9E RV9OVFNDXzQ0MzsKPiArCQlicmVhazsKPiArCj4gIAljYXNlIFZDNF9WRUNfVFZfTU9ERV9OVFND X0o6Cj4gIAkJc3RhdGUtPnR2Lm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX05UU0NfSjsKPiAgCQli cmVhazsKPiAgCj4gIAljYXNlIFZDNF9WRUNfVFZfTU9ERV9QQUw6Cj4gKwljYXNlIFZDNF9WRUNf VFZfTU9ERV9QQUxfNjA6Cj4gIAkJc3RhdGUtPnR2Lm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX1BB TDsKPiAgCQlicmVhazsKPiAgCj4gQEAgLTMxOCw2ICszOTUsMTQgQEAgdmM0X3ZlY19jb25uZWN0 b3Jfc2V0X3Byb3BlcnR5KHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3IsCj4gIAkJc3Rh dGUtPnR2Lm1vZGUgPSBEUk1fTU9ERV9UVl9NT0RFX1BBTF9NOwo+ICAJCWJyZWFrOwo+ICAKPiAr CWNhc2UgVkM0X1ZFQ19UVl9NT0RFX1BBTF9OOgo+ICsJCXN0YXRlLT50di5tb2RlID0gRFJNX01P REVfVFZfTU9ERV9QQUxfTjsKPiArCQlicmVhazsKPiArCj4gKwljYXNlIFZDNF9WRUNfVFZfTU9E RV9TRUNBTToKPiArCQlzdGF0ZS0+dHYubW9kZSA9IERSTV9NT0RFX1RWX01PREVfU0VDQU07Cj4g KwkJYnJlYWs7Cj4gKwo+ICAJZGVmYXVsdDoKPiAgCQlyZXR1cm4gLUVJTlZBTDsKPiAgCX0KPiBA QCAtMzQxLDYgKzQyNiwxMCBAQCB2YzRfdmVjX2Nvbm5lY3Rvcl9nZXRfcHJvcGVydHkoc3RydWN0 IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvciwKPiAgCQkqdmFsID0gVkM0X1ZFQ19UVl9NT0RFX05U U0M7Cj4gIAkJYnJlYWs7Cj4gIAo+ICsJY2FzZSBEUk1fTU9ERV9UVl9NT0RFX05UU0NfNDQzOgo+ ICsJCSp2YWwgPSBWQzRfVkVDX1RWX01PREVfTlRTQ180NDM7Cj4gKwkJYnJlYWs7Cj4gKwo+ICAJ Y2FzZSBEUk1fTU9ERV9UVl9NT0RFX05UU0NfSjoKPiAgCQkqdmFsID0gVkM0X1ZFQ19UVl9NT0RF X05UU0NfSjsKPiAgCQlicmVhazsKPiBAQCAtMzUzLDYgKzQ0MiwxNCBAQCB2YzRfdmVjX2Nvbm5l Y3Rvcl9nZXRfcHJvcGVydHkoc3RydWN0IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvciwKPiAgCQkq dmFsID0gVkM0X1ZFQ19UVl9NT0RFX1BBTF9NOwo+ICAJCWJyZWFrOwo+ICAKPiArCWNhc2UgRFJN X01PREVfVFZfTU9ERV9QQUxfTjoKPiArCQkqdmFsID0gVkM0X1ZFQ19UVl9NT0RFX1BBTF9OOwo+ ICsJCWJyZWFrOwo+ICsKPiArCWNhc2UgRFJNX01PREVfVFZfTU9ERV9TRUNBTToKPiArCQkqdmFs ID0gVkM0X1ZFQ19UVl9NT0RFX1NFQ0FNOwo+ICsJCWJyZWFrOwo+ICsKPiAgCWRlZmF1bHQ6Cj4g IAkJcmV0dXJuIC1FSU5WQUw7Cj4gIAl9Cj4gQEAgLTQ0OCwxMyArNTQ1LDE2IEBAIHN0YXRpYyB2 b2lkIHZjNF92ZWNfZW5jb2Rlcl9lbmFibGUoc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyLAo+ ICAJc3RydWN0IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvciA9ICZ2ZWMtPmNvbm5lY3RvcjsKPiAg CXN0cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlICpjb25uX3N0YXRlID0KPiAgCQlkcm1fYXRvbWlj X2dldF9uZXdfY29ubmVjdG9yX3N0YXRlKHN0YXRlLCBjb25uZWN0b3IpOwo+ICsJc3RydWN0IGRy bV9kaXNwbGF5X21vZGUgKmFkanVzdGVkX21vZGUgPQo+ICsJCSZlbmNvZGVyLT5jcnRjLT5zdGF0 ZS0+YWRqdXN0ZWRfbW9kZTsKPiAgCWNvbnN0IHN0cnVjdCB2YzRfdmVjX3R2X21vZGUgKnR2X21v ZGU7Cj4gIAlpbnQgaWR4LCByZXQ7Cj4gIAo+ICAJaWYgKCFkcm1fZGV2X2VudGVyKGRybSwgJmlk eCkpCj4gIAkJcmV0dXJuOwo+ICAKPiAtCXR2X21vZGUgPSB2YzRfdmVjX3R2X21vZGVfbG9va3Vw KGNvbm5fc3RhdGUtPnR2Lm1vZGUpOwo+ICsJdHZfbW9kZSA9IHZjNF92ZWNfdHZfbW9kZV9sb29r dXAoY29ubl9zdGF0ZS0+dHYubW9kZSwKPiArCQkJCQkgYWRqdXN0ZWRfbW9kZS0+aHRvdGFsKTsK PiAgCWlmICghdHZfbW9kZSkKPiAgCQlnb3RvIGVycl9kZXZfZXhpdDsKPiAgCj4gQEAgLTY0Myw5 ICs3NDMsMTIgQEAgc3RhdGljIGludCB2YzRfdmVjX2JpbmQoc3RydWN0IGRldmljZSAqZGV2LCBz dHJ1Y3QgZGV2aWNlICptYXN0ZXIsIHZvaWQgKmRhdGEpCj4gIAo+ICAJcmV0ID0gZHJtX21vZGVf Y3JlYXRlX3R2X3Byb3BlcnRpZXMoZHJtLAo+ICAJCQkJCSAgICBCSVQoRFJNX01PREVfVFZfTU9E RV9OVFNDKSB8Cj4gKwkJCQkJICAgIEJJVChEUk1fTU9ERV9UVl9NT0RFX05UU0NfNDQzKSB8Cj4g IAkJCQkJICAgIEJJVChEUk1fTU9ERV9UVl9NT0RFX05UU0NfSikgfAo+ICAJCQkJCSAgICBCSVQo RFJNX01PREVfVFZfTU9ERV9QQUwpIHwKPiAtCQkJCQkgICAgQklUKERSTV9NT0RFX1RWX01PREVf UEFMX00pKTsKPiArCQkJCQkgICAgQklUKERSTV9NT0RFX1RWX01PREVfUEFMX00pIHwKPiArCQkJ CQkgICAgQklUKERSTV9NT0RFX1RWX01PREVfUEFMX04pIHwKPiArCQkJCQkgICAgQklUKERSTV9N T0RFX1RWX01PREVfU0VDQU0pKTsKPiAgCWlmIChyZXQpCj4gIAkJcmV0dXJuIHJldDsKPiAgCj4K CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1h cm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5v cmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0t a2VybmVsCg==