* [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-28 20:10 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:10 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180528-v4.17-rc7' tag. We're adding the R8A77980 I2C nodes
and then describing 2 PCA9654 I/O expanders connected to the I2C0 bus on
the Condor board.
[1/2] arm64: dts: renesas: r8a77980: add I2C support
[2/2] arm64: dts: renesas: condor: add I2C0 support
WBR, Sergei
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-28 20:10 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:10 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180528-v4.17-rc7' tag. We're adding the R8A77980 I2C nodes
and then describing 2 PCA9654 I/O expanders connected to the I2C0 bus on
the Condor board.
[1/2] arm64: dts: renesas: r8a77980: add I2C support
[2/2] arm64: dts: renesas: condor: add I2C0 support
WBR, Sergei
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-28 20:10 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:10 UTC (permalink / raw)
To: linux-arm-kernel
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180528-v4.17-rc7' tag. We're adding the R8A77980 I2C nodes
and then describing 2 PCA9654 I/O expanders connected to the I2C0 bus on
the Condor board.
[1/2] arm64: dts: renesas: r8a77980: add I2C support
[2/2] arm64: dts: renesas: condor: add I2C0 support
WBR, Sergei
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
2018-05-28 20:10 ` Sergei Shtylyov
(?)
@ 2018-05-28 20:13 ` Sergei Shtylyov
-1 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:13 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Define the generic R8A77980 parts of the I2C[0-5] device node.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -16,6 +16,15 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -135,6 +144,108 @@
#power-domain-cells = <1>;
};
+ i2c0: i2c@e6500000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6510000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac1 0x97>, <&dmac1 0x96>,
+ <&dmac2 0x97>, <&dmac2 0x96>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e66d8000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ dmas = <&dmac1 0x99>, <&dmac1 0x98>,
+ <&dmac2 0x99>, <&dmac2 0x98>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e66e0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66e0000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
+ <&dmac2 0x9b>, <&dmac2 0x9a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a77980",
"renesas,rcar-gen3-hscif",
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-28 20:13 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:13 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Define the generic R8A77980 parts of the I2C[0-5] device node.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -16,6 +16,15 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -135,6 +144,108 @@
#power-domain-cells = <1>;
};
+ i2c0: i2c@e6500000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6510000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac1 0x97>, <&dmac1 0x96>,
+ <&dmac2 0x97>, <&dmac2 0x96>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e66d8000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ dmas = <&dmac1 0x99>, <&dmac1 0x98>,
+ <&dmac2 0x99>, <&dmac2 0x98>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e66e0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66e0000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
+ <&dmac2 0x9b>, <&dmac2 0x9a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a77980",
"renesas,rcar-gen3-hscif",
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-28 20:13 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:13 UTC (permalink / raw)
To: linux-arm-kernel
Define the generic R8A77980 parts of the I2C[0-5] device node.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -16,6 +16,15 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -135,6 +144,108 @@
#power-domain-cells = <1>;
};
+ i2c0: i2c at e6500000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at e6508000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at e6510000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at e66d0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac1 0x97>, <&dmac1 0x96>,
+ <&dmac2 0x97>, <&dmac2 0x96>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at e66d8000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ dmas = <&dmac1 0x99>, <&dmac1 0x98>,
+ <&dmac2 0x99>, <&dmac2 0x98>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c at e66e0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66e0000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
+ <&dmac2 0x9b>, <&dmac2 0x9a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
hscif0: serial at e6540000 {
compatible = "renesas,hscif-r8a77980",
"renesas,rcar-gen3-hscif",
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
2018-05-28 20:10 ` Sergei Shtylyov
(?)
@ 2018-05-28 20:14 ` Sergei Shtylyov
-1 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:14 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Define the Condor board dependent part of the I2C0 device node.
The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
and Analog Devices ADV7511W HDMI transmitter (but we're only describing
the former chips now).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -80,6 +80,28 @@
clock-frequency = <32768>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ io_expander0: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ io_expander1: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
@@ -104,6 +126,11 @@
function = "canfd0";
};
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-28 20:14 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:14 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Define the Condor board dependent part of the I2C0 device node.
The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
and Analog Devices ADV7511W HDMI transmitter (but we're only describing
the former chips now).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -80,6 +80,28 @@
clock-frequency = <32768>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ io_expander0: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ io_expander1: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
@@ -104,6 +126,11 @@
function = "canfd0";
};
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-28 20:14 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:14 UTC (permalink / raw)
To: linux-arm-kernel
Define the Condor board dependent part of the I2C0 device node.
The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
and Analog Devices ADV7511W HDMI transmitter (but we're only describing
the former chips now).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -80,6 +80,28 @@
clock-frequency = <32768>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ io_expander0: gpio at 20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ io_expander1: gpio at 21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
@@ -104,6 +126,11 @@
function = "canfd0";
};
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 0/2] Add R8A77980/Condor I2C support
2018-05-28 20:10 ` Sergei Shtylyov
(?)
@ 2018-05-28 20:16 ` Sergei Shtylyov
-1 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:16 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Sorry, "v3" shouldn't be there in the subject...
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-28 20:16 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:16 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Sorry, "v3" shouldn't be there in the subject...
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-28 20:16 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-28 20:16 UTC (permalink / raw)
To: linux-arm-kernel
Sorry, "v3" shouldn't be there in the subject...
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
2018-05-28 20:13 ` Sergei Shtylyov
(?)
@ 2018-05-29 13:05 ` Simon Horman
-1 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:05 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -16,6 +16,15 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -135,6 +144,108 @@
> #power-domain-cells = <1>;
> };
>
> + i2c0: i2c@e6500000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6500000 0 0x40>;
> + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 931>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 931>;
> + dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> + <&dmac2 0x91>, <&dmac2 0x90>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@e6508000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6508000 0 0x40>;
> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 930>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 930>;
> + dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> + <&dmac2 0x93>, <&dmac2 0x92>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@e6510000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6510000 0 0x40>;
> + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 929>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 929>;
> + dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> + <&dmac2 0x95>, <&dmac2 0x94>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@e66d0000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66d0000 0 0x40>;
> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 928>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 928>;
> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
> + <&dmac2 0x97>, <&dmac2 0x96>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
Although what is described here does match v0.55E of the User's Manual.
Have you been able to confirm what is correct here?
Other than that this patch looks fine to me.
> +
> + i2c4: i2c@e66d8000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66d8000 0 0x40>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 927>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 927>;
> + dmas = <&dmac1 0x99>, <&dmac1 0x98>,
> + <&dmac2 0x99>, <&dmac2 0x98>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@e66e0000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66e0000 0 0x40>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 919>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 919>;
> + dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
> + <&dmac2 0x9b>, <&dmac2 0x9a>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> hscif0: serial@e6540000 {
> compatible = "renesas,hscif-r8a77980",
> "renesas,rcar-gen3-hscif",
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 13:05 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:05 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -16,6 +16,15 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -135,6 +144,108 @@
> #power-domain-cells = <1>;
> };
>
> + i2c0: i2c@e6500000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6500000 0 0x40>;
> + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 931>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 931>;
> + dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> + <&dmac2 0x91>, <&dmac2 0x90>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@e6508000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6508000 0 0x40>;
> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 930>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 930>;
> + dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> + <&dmac2 0x93>, <&dmac2 0x92>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@e6510000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6510000 0 0x40>;
> + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 929>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 929>;
> + dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> + <&dmac2 0x95>, <&dmac2 0x94>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@e66d0000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66d0000 0 0x40>;
> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 928>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 928>;
> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
> + <&dmac2 0x97>, <&dmac2 0x96>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
Although what is described here does match v0.55E of the User's Manual.
Have you been able to confirm what is correct here?
Other than that this patch looks fine to me.
> +
> + i2c4: i2c@e66d8000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66d8000 0 0x40>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 927>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 927>;
> + dmas = <&dmac1 0x99>, <&dmac1 0x98>,
> + <&dmac2 0x99>, <&dmac2 0x98>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@e66e0000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66e0000 0 0x40>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 919>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 919>;
> + dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
> + <&dmac2 0x9b>, <&dmac2 0x9a>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> hscif0: serial@e6540000 {
> compatible = "renesas,hscif-r8a77980",
> "renesas,rcar-gen3-hscif",
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 13:05 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:05 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -16,6 +16,15 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -135,6 +144,108 @@
> #power-domain-cells = <1>;
> };
>
> + i2c0: i2c at e6500000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6500000 0 0x40>;
> + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 931>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 931>;
> + dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> + <&dmac2 0x91>, <&dmac2 0x90>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c at e6508000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6508000 0 0x40>;
> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 930>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 930>;
> + dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> + <&dmac2 0x93>, <&dmac2 0x92>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c at e6510000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe6510000 0 0x40>;
> + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 929>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 929>;
> + dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> + <&dmac2 0x95>, <&dmac2 0x94>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c at e66d0000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66d0000 0 0x40>;
> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 928>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 928>;
> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
> + <&dmac2 0x97>, <&dmac2 0x96>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
Although what is described here does match v0.55E of the User's Manual.
Have you been able to confirm what is correct here?
Other than that this patch looks fine to me.
> +
> + i2c4: i2c at e66d8000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66d8000 0 0x40>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 927>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 927>;
> + dmas = <&dmac1 0x99>, <&dmac1 0x98>,
> + <&dmac2 0x99>, <&dmac2 0x98>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c at e66e0000 {
> + compatible = "renesas,i2c-r8a77980",
> + "renesas,rcar-gen3-i2c";
> + reg = <0 0xe66e0000 0 0x40>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 919>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 919>;
> + dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
> + <&dmac2 0x9b>, <&dmac2 0x9a>;
> + dma-names = "tx", "rx", "tx", "rx";
> + i2c-scl-internal-delay-ns = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> hscif0: serial at e6540000 {
> compatible = "renesas,hscif-r8a77980",
> "renesas,rcar-gen3-hscif",
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
2018-05-28 20:14 ` Sergei Shtylyov
(?)
@ 2018-05-29 13:10 ` Simon Horman
-1 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio@20 {
Hi Sergei,
I'm a little confused about where 0x20 and 0x21 are derived from.
Could you explain a little?
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + io_expander1: gpio@21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-0 = <&mmc_pins>;
> pinctrl-1 = <&mmc_pins_uhs>;
> @@ -104,6 +126,11 @@
> function = "canfd0";
> };
>
> + i2c0_pins: i2c0 {
> + groups = "i2c0";
> + function = "i2c0";
> + };
> +
> mmc_pins: mmc {
> groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> function = "mmc";
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-29 13:10 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio@20 {
Hi Sergei,
I'm a little confused about where 0x20 and 0x21 are derived from.
Could you explain a little?
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + io_expander1: gpio@21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-0 = <&mmc_pins>;
> pinctrl-1 = <&mmc_pins_uhs>;
> @@ -104,6 +126,11 @@
> function = "canfd0";
> };
>
> + i2c0_pins: i2c0 {
> + groups = "i2c0";
> + function = "i2c0";
> + };
> +
> mmc_pins: mmc {
> groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> function = "mmc";
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-29 13:10 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:10 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio at 20 {
Hi Sergei,
I'm a little confused about where 0x20 and 0x21 are derived from.
Could you explain a little?
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + io_expander1: gpio at 21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-0 = <&mmc_pins>;
> pinctrl-1 = <&mmc_pins_uhs>;
> @@ -104,6 +126,11 @@
> function = "canfd0";
> };
>
> + i2c0_pins: i2c0 {
> + groups = "i2c0";
> + function = "i2c0";
> + };
> +
> mmc_pins: mmc {
> groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> function = "mmc";
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 0/2] Add R8A77980/Condor I2C support
2018-05-28 20:16 ` Sergei Shtylyov
(?)
@ 2018-05-29 13:10 ` Simon Horman
-1 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Mon, May 28, 2018 at 11:16:18PM +0300, Sergei Shtylyov wrote:
> Sorry, "v3" shouldn't be there in the subject...
Thanks, noted.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-29 13:10 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On Mon, May 28, 2018 at 11:16:18PM +0300, Sergei Shtylyov wrote:
> Sorry, "v3" shouldn't be there in the subject...
Thanks, noted.
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v3 0/2] Add R8A77980/Condor I2C support
@ 2018-05-29 13:10 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-29 13:10 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, May 28, 2018 at 11:16:18PM +0300, Sergei Shtylyov wrote:
> Sorry, "v3" shouldn't be there in the subject...
Thanks, noted.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
2018-05-29 13:10 ` Simon Horman
(?)
@ 2018-05-29 15:46 ` Sergei Shtylyov
-1 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-29 15:46 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
Hello!
On 05/29/2018 04:10 PM, Simon Horman wrote:
>> Define the Condor board dependent part of the I2C0 device node.
>>
>> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
>> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
>> the former chips now).
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> @@ -80,6 +80,28 @@
>> clock-frequency = <32768>;
>> };
>>
>> +&i2c0 {
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + io_expander0: gpio@20 {
>
> Hi Sergei,
>
> I'm a little confused about where 0x20 and 0x21 are derived from.
> Could you explain a little?
r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
I2C address in DTs.
>> + compatible = "onnn,pca9654";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +
>> + io_expander1: gpio@21 {
>> + compatible = "onnn,pca9654";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +};
>> +
>> &mmc0 {
>> pinctrl-0 = <&mmc_pins>;
>> pinctrl-1 = <&mmc_pins_uhs>;
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-29 15:46 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-29 15:46 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
Hello!
On 05/29/2018 04:10 PM, Simon Horman wrote:
>> Define the Condor board dependent part of the I2C0 device node.
>>
>> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
>> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
>> the former chips now).
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> @@ -80,6 +80,28 @@
>> clock-frequency = <32768>;
>> };
>>
>> +&i2c0 {
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + io_expander0: gpio@20 {
>
> Hi Sergei,
>
> I'm a little confused about where 0x20 and 0x21 are derived from.
> Could you explain a little?
r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
I2C address in DTs.
>> + compatible = "onnn,pca9654";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +
>> + io_expander1: gpio@21 {
>> + compatible = "onnn,pca9654";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +};
>> +
>> &mmc0 {
>> pinctrl-0 = <&mmc_pins>;
>> pinctrl-1 = <&mmc_pins_uhs>;
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-29 15:46 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-29 15:46 UTC (permalink / raw)
To: linux-arm-kernel
Hello!
On 05/29/2018 04:10 PM, Simon Horman wrote:
>> Define the Condor board dependent part of the I2C0 device node.
>>
>> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
>> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
>> the former chips now).
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> @@ -80,6 +80,28 @@
>> clock-frequency = <32768>;
>> };
>>
>> +&i2c0 {
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + io_expander0: gpio at 20 {
>
> Hi Sergei,
>
> I'm a little confused about where 0x20 and 0x21 are derived from.
> Could you explain a little?
r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
I2C address in DTs.
>> + compatible = "onnn,pca9654";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +
>> + io_expander1: gpio at 21 {
>> + compatible = "onnn,pca9654";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +};
>> +
>> &mmc0 {
>> pinctrl-0 = <&mmc_pins>;
>> pinctrl-1 = <&mmc_pins_uhs>;
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
2018-05-29 13:05 ` Simon Horman
(?)
@ 2018-05-29 16:04 ` Sergei Shtylyov
-1 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-29 16:04 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On 05/29/2018 04:05 PM, Simon Horman wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
>> 1 file changed, 111 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -135,6 +144,108 @@
[...]
>> + i2c3: i2c@e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
Hm, looking at all these manuals, I'm not even seeing V3H I2C3/4 having DMA
in v0.55E!
> Have you been able to confirm what is correct here?
No. Probably need to drop I2C3/4 DMA altogether...
> Other than that this patch looks fine to me.
TY!
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 16:04 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-29 16:04 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On 05/29/2018 04:05 PM, Simon Horman wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
>> 1 file changed, 111 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -135,6 +144,108 @@
[...]
>> + i2c3: i2c@e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
Hm, looking at all these manuals, I'm not even seeing V3H I2C3/4 having DMA
in v0.55E!
> Have you been able to confirm what is correct here?
No. Probably need to drop I2C3/4 DMA altogether...
> Other than that this patch looks fine to me.
TY!
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 16:04 ` Sergei Shtylyov
0 siblings, 0 replies; 39+ messages in thread
From: Sergei Shtylyov @ 2018-05-29 16:04 UTC (permalink / raw)
To: linux-arm-kernel
On 05/29/2018 04:05 PM, Simon Horman wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
>> 1 file changed, 111 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -135,6 +144,108 @@
[...]
>> + i2c3: i2c at e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
Hm, looking at all these manuals, I'm not even seeing V3H I2C3/4 having DMA
in v0.55E!
> Have you been able to confirm what is correct here?
No. Probably need to drop I2C3/4 DMA altogether...
> Other than that this patch looks fine to me.
TY!
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
2018-05-28 20:13 ` Sergei Shtylyov
(?)
@ 2018-05-29 16:41 ` Geert Uytterhoeven
-1 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-05-29 16:41 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, linux-arm-kernel
On Mon, May 28, 2018 at 10:13 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 16:41 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-05-29 16:41 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Mark Rutland, Magnus Damm, linux-arm-kernel
On Mon, May 28, 2018 at 10:13 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 16:41 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-05-29 16:41 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, May 28, 2018 at 10:13 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
2018-05-29 13:05 ` Simon Horman
(?)
@ 2018-05-29 16:42 ` Geert Uytterhoeven
-1 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-05-29 16:42 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Sergei Shtylyov, Catalin Marinas, Will Deacon,
Linux-Renesas, Rob Herring, linux-arm-kernel
Hi Simon,
On Tue, May 29, 2018 at 3:05 PM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> + i2c3: i2c@e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
> Have you been able to confirm what is correct here?
Given they bothered adding rows to the table, I assume they just forgot to
add checkmarks in the V3H column.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 16:42 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-05-29 16:42 UTC (permalink / raw)
To: Simon Horman
Cc: Sergei Shtylyov, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland, linux-arm-kernel
Hi Simon,
On Tue, May 29, 2018 at 3:05 PM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> + i2c3: i2c@e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
> Have you been able to confirm what is correct here?
Given they bothered adding rows to the table, I assume they just forgot to
add checkmarks in the V3H column.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
@ 2018-05-29 16:42 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-05-29 16:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
On Tue, May 29, 2018 at 3:05 PM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> + i2c3: i2c at e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
> Have you been able to confirm what is correct here?
Given they bothered adding rows to the table, I assume they just forgot to
add checkmarks in the V3H column.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
2018-05-29 15:46 ` Sergei Shtylyov
(?)
@ 2018-05-30 9:35 ` Simon Horman
-1 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-30 9:35 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Tue, May 29, 2018 at 06:46:10PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 05/29/2018 04:10 PM, Simon Horman wrote:
>
> >> Define the Condor board dependent part of the I2C0 device node.
> >>
> >> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> >> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> >> the former chips now).
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> >> 1 file changed, 27 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> @@ -80,6 +80,28 @@
> >> clock-frequency = <32768>;
> >> };
> >>
> >> +&i2c0 {
> >> + pinctrl-0 = <&i2c0_pins>;
> >> + pinctrl-names = "default";
> >> +
> >> + status = "okay";
> >> + clock-frequency = <400000>;
> >> +
> >> + io_expander0: gpio@20 {
> >
> > Hi Sergei,
> >
> > I'm a little confused about where 0x20 and 0x21 are derived from.
> > Could you explain a little?
>
> r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
> The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
> I2C address in DTs.
Thanks, this patch looks fine to me.
However, I'd like to give others a chance to review it,
and it is dependent on patch 1/2 where I have a different review question.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> >> + compatible = "onnn,pca9654";
> >> + reg = <0x20>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + };
> >> +
> >> + io_expander1: gpio@21 {
> >> + compatible = "onnn,pca9654";
> >> + reg = <0x21>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + };
> >> +};
> >> +
> >> &mmc0 {
> >> pinctrl-0 = <&mmc_pins>;
> >> pinctrl-1 = <&mmc_pins_uhs>;
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-30 9:35 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-30 9:35 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On Tue, May 29, 2018 at 06:46:10PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 05/29/2018 04:10 PM, Simon Horman wrote:
>
> >> Define the Condor board dependent part of the I2C0 device node.
> >>
> >> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> >> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> >> the former chips now).
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> >> 1 file changed, 27 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> @@ -80,6 +80,28 @@
> >> clock-frequency = <32768>;
> >> };
> >>
> >> +&i2c0 {
> >> + pinctrl-0 = <&i2c0_pins>;
> >> + pinctrl-names = "default";
> >> +
> >> + status = "okay";
> >> + clock-frequency = <400000>;
> >> +
> >> + io_expander0: gpio@20 {
> >
> > Hi Sergei,
> >
> > I'm a little confused about where 0x20 and 0x21 are derived from.
> > Could you explain a little?
>
> r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
> The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
> I2C address in DTs.
Thanks, this patch looks fine to me.
However, I'd like to give others a chance to review it,
and it is dependent on patch 1/2 where I have a different review question.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> >> + compatible = "onnn,pca9654";
> >> + reg = <0x20>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + };
> >> +
> >> + io_expander1: gpio@21 {
> >> + compatible = "onnn,pca9654";
> >> + reg = <0x21>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + };
> >> +};
> >> +
> >> &mmc0 {
> >> pinctrl-0 = <&mmc_pins>;
> >> pinctrl-1 = <&mmc_pins_uhs>;
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-05-30 9:35 ` Simon Horman
0 siblings, 0 replies; 39+ messages in thread
From: Simon Horman @ 2018-05-30 9:35 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 29, 2018 at 06:46:10PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 05/29/2018 04:10 PM, Simon Horman wrote:
>
> >> Define the Condor board dependent part of the I2C0 device node.
> >>
> >> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> >> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> >> the former chips now).
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> >> 1 file changed, 27 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> >> @@ -80,6 +80,28 @@
> >> clock-frequency = <32768>;
> >> };
> >>
> >> +&i2c0 {
> >> + pinctrl-0 = <&i2c0_pins>;
> >> + pinctrl-names = "default";
> >> +
> >> + status = "okay";
> >> + clock-frequency = <400000>;
> >> +
> >> + io_expander0: gpio at 20 {
> >
> > Hi Sergei,
> >
> > I'm a little confused about where 0x20 and 0x21 are derived from.
> > Could you explain a little?
>
> r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
> The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
> I2C address in DTs.
Thanks, this patch looks fine to me.
However, I'd like to give others a chance to review it,
and it is dependent on patch 1/2 where I have a different review question.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> >> + compatible = "onnn,pca9654";
> >> + reg = <0x20>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + };
> >> +
> >> + io_expander1: gpio at 21 {
> >> + compatible = "onnn,pca9654";
> >> + reg = <0x21>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + };
> >> +};
> >> +
> >> &mmc0 {
> >> pinctrl-0 = <&mmc_pins>;
> >> pinctrl-1 = <&mmc_pins_uhs>;
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
2018-05-28 20:14 ` Sergei Shtylyov
(?)
@ 2018-06-06 7:46 ` Geert Uytterhoeven
-1 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-06-06 7:46 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, linux-arm-kernel
Hi Sergei,
On Mon, May 28, 2018 at 10:14 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Suggestion for future improvement below.
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio@20 {
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
The bindings don't mention this (the example does have it) the optional
interrupts prototype. As this is wired to INTC-EX IRQ4, you may want to
add that. Perhaps later, as r8a77980.dtsi doesn't have INTC-EX yet.
> + };
> +
> + io_expander1: gpio@21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
Same for IRQ5.
> + };
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-06-06 7:46 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-06-06 7:46 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Mark Rutland, Magnus Damm, linux-arm-kernel
Hi Sergei,
On Mon, May 28, 2018 at 10:14 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Suggestion for future improvement below.
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio@20 {
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
The bindings don't mention this (the example does have it) the optional
interrupts prototype. As this is wired to INTC-EX IRQ4, you may want to
add that. Perhaps later, as r8a77980.dtsi doesn't have INTC-EX yet.
> + };
> +
> + io_expander1: gpio@21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
Same for IRQ5.
> + };
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
@ 2018-06-06 7:46 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2018-06-06 7:46 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sergei,
On Mon, May 28, 2018 at 10:14 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Suggestion for future improvement below.
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio at 20 {
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
The bindings don't mention this (the example does have it) the optional
interrupts prototype. As this is wired to INTC-EX IRQ4, you may want to
add that. Perhaps later, as r8a77980.dtsi doesn't have INTC-EX yet.
> + };
> +
> + io_expander1: gpio at 21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
Same for IRQ5.
> + };
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2018-06-06 7:46 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-28 20:10 [PATCH v3 0/2] Add R8A77980/Condor I2C support Sergei Shtylyov
2018-05-28 20:10 ` Sergei Shtylyov
2018-05-28 20:10 ` Sergei Shtylyov
2018-05-28 20:13 ` [PATCH 1/2] arm64: dts: renesas: r8a77980: add " Sergei Shtylyov
2018-05-28 20:13 ` Sergei Shtylyov
2018-05-28 20:13 ` Sergei Shtylyov
2018-05-29 13:05 ` Simon Horman
2018-05-29 13:05 ` Simon Horman
2018-05-29 13:05 ` Simon Horman
2018-05-29 16:04 ` Sergei Shtylyov
2018-05-29 16:04 ` Sergei Shtylyov
2018-05-29 16:04 ` Sergei Shtylyov
2018-05-29 16:42 ` Geert Uytterhoeven
2018-05-29 16:42 ` Geert Uytterhoeven
2018-05-29 16:42 ` Geert Uytterhoeven
2018-05-29 16:41 ` Geert Uytterhoeven
2018-05-29 16:41 ` Geert Uytterhoeven
2018-05-29 16:41 ` Geert Uytterhoeven
2018-05-28 20:14 ` [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support Sergei Shtylyov
2018-05-28 20:14 ` Sergei Shtylyov
2018-05-28 20:14 ` Sergei Shtylyov
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
2018-05-29 15:46 ` Sergei Shtylyov
2018-05-29 15:46 ` Sergei Shtylyov
2018-05-29 15:46 ` Sergei Shtylyov
2018-05-30 9:35 ` Simon Horman
2018-05-30 9:35 ` Simon Horman
2018-05-30 9:35 ` Simon Horman
2018-06-06 7:46 ` Geert Uytterhoeven
2018-06-06 7:46 ` Geert Uytterhoeven
2018-06-06 7:46 ` Geert Uytterhoeven
2018-05-28 20:16 ` [PATCH v3 0/2] Add R8A77980/Condor I2C support Sergei Shtylyov
2018-05-28 20:16 ` Sergei Shtylyov
2018-05-28 20:16 ` Sergei Shtylyov
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
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