* [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block
@ 2021-05-24 10:20 ` Baruch Siach
0 siblings, 0 replies; 15+ messages in thread
From: Baruch Siach @ 2021-05-24 10:20 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, linux-pwm, devicetree, linux-arm-msm,
linux-arm-kernel
Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
driver from downstream Codeaurora kernel tree. Removed support for older
(V1) variants because I have no access to that hardware.
Tested on IPQ6010 based hardware.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2:
Address Uwe Kleine-König review comments:
Fix period calculation when out of range
Don't set period larger than requested
Remove PWM disable on configuration change
Implement .apply instead of non-atomic .config/.enable/.disable
Don't modify PWM on .request/.free
Check pwm_div underflow
Fix various code and comment formatting issues
Other changes:
Use u64 divisor safe division
Remove now empty .request/.free
---
drivers/pwm/Kconfig | 12 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-ipq.c | 238 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 251 insertions(+)
create mode 100644 drivers/pwm/pwm-ipq.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 9a4f66ae8070..54ef62a27bdc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -260,6 +260,18 @@ config PWM_INTEL_LGM
To compile this driver as a module, choose M here: the module
will be called pwm-intel-lgm.
+config PWM_IPQ
+ tristate "IPQ PWM support"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on HAVE_CLK && HAS_IOMEM
+ help
+ Generic PWM framework driver for IPQ PWM block which supports
+ 4 pwm channels. Each of the these channels can be configured
+ independent of each other.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-ipq.
+
config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 6374d3b1d6f3..73eb955dea1d 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o
+obj-$(CONFIG_PWM_IPQ) += pwm-ipq.o
obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
new file mode 100644
index 000000000000..cedbd682a5c7
--- /dev/null
+++ b/drivers/pwm/pwm-ipq.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+/*
+ * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/math64.h>
+#include <linux/of_device.h>
+
+#define CLK_SRC_FREQ (100*1000*1000)
+#define MAX_PWM_DEVICES 4
+
+/*
+ * Enable bit is set to enable output toggling in pwm device.
+ * Update bit is set to reflect the changed divider and high duration
+ * values in register.
+ */
+#define PWM_ENABLE 0x80000000
+#define PWM_UPDATE 0x40000000
+
+/* The frequency range supported is 1Hz to 100MHz */
+#define MIN_PERIOD_NS 10
+#define MAX_PERIOD_NS 1000000000
+
+/*
+ * The max value specified for each field is based on the number of bits
+ * in the pwm control register for that field
+ */
+#define MAX_PWM_CFG 0xFFFF
+
+#define PWM_CTRL_HI_SHIFT 16
+
+#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/
+#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/
+
+struct ipq_pwm_chip {
+ struct pwm_chip chip;
+ struct clk *clk;
+ void __iomem *mem;
+};
+
+static struct ipq_pwm_chip *to_ipq_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct ipq_pwm_chip, chip);
+}
+
+static unsigned ipq_pwm_reg_offset(struct pwm_device *pwm, unsigned reg)
+{
+ return ((pwm->hwpwm * 2) + reg) * 4;
+}
+
+static void config_div_and_duty(struct pwm_device *pwm, int pre_div,
+ unsigned long long pwm_div, unsigned long period_ns,
+ unsigned long long duty_ns)
+{
+ unsigned long hi_dur;
+ unsigned long long quotient;
+ unsigned long val = 0;
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+
+ /*
+ * high duration = pwm duty * (pwm div + 1)
+ * pwm duty = duty_ns / period_ns
+ */
+ quotient = (pwm_div + 1) * duty_ns;
+ hi_dur = div64_u64(quotient, period_ns);
+
+ val |= ((hi_dur & MAX_PWM_CFG) << PWM_CTRL_HI_SHIFT);
+ val |= (pwm_div & MAX_PWM_CFG);
+ writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG0));
+ val = pre_div & MAX_PWM_CFG;
+ writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG1));
+}
+
+static int ipq_pwm_enable(struct pwm_device *pwm)
+{
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+ unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
+ unsigned long val;
+
+ val = readl(ipq_chip->mem + offset);
+ val |= PWM_ENABLE | PWM_UPDATE;
+ writel(val, ipq_chip->mem + offset);
+
+ return 0;
+}
+
+static void ipq_pwm_disable(struct pwm_device *pwm)
+{
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+ unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
+ unsigned long val;
+
+ val = readl(ipq_chip->mem + offset);
+ val |= PWM_UPDATE;
+ val &= ~PWM_ENABLE;
+ writel(val, ipq_chip->mem + offset);
+}
+
+static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
+ unsigned long freq;
+ int pre_div, close_pre_div, close_pwm_div;
+ int pwm_div;
+ long long diff;
+ unsigned long rate = clk_get_rate(ipq_chip->clk);
+ unsigned long min_diff = rate;
+ uint64_t fin_ps;
+ u64 period_ns, duty_ns;
+
+ if (state->period < MIN_PERIOD_NS)
+ return -ERANGE;
+
+ period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
+ duty_ns = min_t(u64, state->duty_cycle, period_ns);
+
+ /* freq in Hz for period in nano second*/
+ freq = NSEC_PER_SEC / period_ns;
+ fin_ps = div64_u64(NSEC_PER_SEC * 1000, rate);
+ close_pre_div = MAX_PWM_CFG;
+ close_pwm_div = MAX_PWM_CFG;
+
+ for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
+ pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
+ fin_ps * (pre_div + 1));
+ pwm_div--;
+ if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
+ continue;
+
+ diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
+ - (uint64_t)rate;
+
+ if (diff < 0) /* period larger than requested */
+ continue;
+ if (diff == 0) { /* bingo */
+ close_pre_div = pre_div;
+ close_pwm_div = pwm_div;
+ break;
+ }
+ if (diff < min_diff) {
+ min_diff = diff;
+ close_pre_div = pre_div;
+ close_pwm_div = pwm_div;
+ }
+ }
+
+ /* config divider values for the closest possible frequency */
+ config_div_and_duty(pwm, close_pre_div, close_pwm_div,
+ period_ns, duty_ns);
+ if (state->enabled)
+ ipq_pwm_enable(pwm);
+ else
+ ipq_pwm_disable(pwm);
+
+ return 0;
+}
+
+static struct pwm_ops ipq_pwm_ops = {
+ .apply = ipq_pwm_apply,
+ .owner = THIS_MODULE,
+};
+
+static int ipq_pwm_probe(struct platform_device *pdev)
+{
+ struct ipq_pwm_chip *pwm;
+ struct device *dev;
+ int ret;
+
+ dev = &pdev->dev;
+ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pwm);
+
+ pwm->mem = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pwm->mem))
+ return PTR_ERR(pwm->mem);
+
+ pwm->clk = devm_clk_get(dev, "core");
+ if (IS_ERR(pwm->clk))
+ return PTR_ERR(pwm->clk);
+
+ ret = clk_set_rate(pwm->clk, CLK_SRC_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_prepare_enable(pwm->clk);
+ if (ret)
+ return ret;
+
+ pwm->chip.dev = dev;
+ pwm->chip.ops = &ipq_pwm_ops;
+ pwm->chip.npwm = MAX_PWM_DEVICES;
+
+ ret = pwmchip_add(&pwm->chip);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "pwmchip_add() failed\n");
+ clk_disable_unprepare(pwm->clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ipq_pwm_remove(struct platform_device *pdev)
+{
+ struct ipq_pwm_chip *pwm = platform_get_drvdata(pdev);
+
+ pwmchip_remove(&pwm->chip);
+
+ return 0;
+}
+
+static const struct of_device_id pwm_ipq_dt_match[] = {
+ { .compatible = "qcom,pwm-ipq6018", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
+
+static struct platform_driver ipq_pwm_driver = {
+ .driver = {
+ .name = "ipq-pwm",
+ .owner = THIS_MODULE,
+ .of_match_table = pwm_ipq_dt_match,
+ },
+ .probe = ipq_pwm_probe,
+ .remove = ipq_pwm_remove,
+};
+
+module_platform_driver(ipq_pwm_driver);
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.30.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block
@ 2021-05-24 10:20 ` Baruch Siach
0 siblings, 0 replies; 15+ messages in thread
From: Baruch Siach @ 2021-05-24 10:20 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, linux-pwm, devicetree, linux-arm-msm,
linux-arm-kernel
Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
driver from downstream Codeaurora kernel tree. Removed support for older
(V1) variants because I have no access to that hardware.
Tested on IPQ6010 based hardware.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2:
Address Uwe Kleine-König review comments:
Fix period calculation when out of range
Don't set period larger than requested
Remove PWM disable on configuration change
Implement .apply instead of non-atomic .config/.enable/.disable
Don't modify PWM on .request/.free
Check pwm_div underflow
Fix various code and comment formatting issues
Other changes:
Use u64 divisor safe division
Remove now empty .request/.free
---
drivers/pwm/Kconfig | 12 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-ipq.c | 238 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 251 insertions(+)
create mode 100644 drivers/pwm/pwm-ipq.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 9a4f66ae8070..54ef62a27bdc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -260,6 +260,18 @@ config PWM_INTEL_LGM
To compile this driver as a module, choose M here: the module
will be called pwm-intel-lgm.
+config PWM_IPQ
+ tristate "IPQ PWM support"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on HAVE_CLK && HAS_IOMEM
+ help
+ Generic PWM framework driver for IPQ PWM block which supports
+ 4 pwm channels. Each of the these channels can be configured
+ independent of each other.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-ipq.
+
config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 6374d3b1d6f3..73eb955dea1d 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o
+obj-$(CONFIG_PWM_IPQ) += pwm-ipq.o
obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
new file mode 100644
index 000000000000..cedbd682a5c7
--- /dev/null
+++ b/drivers/pwm/pwm-ipq.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+/*
+ * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/math64.h>
+#include <linux/of_device.h>
+
+#define CLK_SRC_FREQ (100*1000*1000)
+#define MAX_PWM_DEVICES 4
+
+/*
+ * Enable bit is set to enable output toggling in pwm device.
+ * Update bit is set to reflect the changed divider and high duration
+ * values in register.
+ */
+#define PWM_ENABLE 0x80000000
+#define PWM_UPDATE 0x40000000
+
+/* The frequency range supported is 1Hz to 100MHz */
+#define MIN_PERIOD_NS 10
+#define MAX_PERIOD_NS 1000000000
+
+/*
+ * The max value specified for each field is based on the number of bits
+ * in the pwm control register for that field
+ */
+#define MAX_PWM_CFG 0xFFFF
+
+#define PWM_CTRL_HI_SHIFT 16
+
+#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/
+#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/
+
+struct ipq_pwm_chip {
+ struct pwm_chip chip;
+ struct clk *clk;
+ void __iomem *mem;
+};
+
+static struct ipq_pwm_chip *to_ipq_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct ipq_pwm_chip, chip);
+}
+
+static unsigned ipq_pwm_reg_offset(struct pwm_device *pwm, unsigned reg)
+{
+ return ((pwm->hwpwm * 2) + reg) * 4;
+}
+
+static void config_div_and_duty(struct pwm_device *pwm, int pre_div,
+ unsigned long long pwm_div, unsigned long period_ns,
+ unsigned long long duty_ns)
+{
+ unsigned long hi_dur;
+ unsigned long long quotient;
+ unsigned long val = 0;
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+
+ /*
+ * high duration = pwm duty * (pwm div + 1)
+ * pwm duty = duty_ns / period_ns
+ */
+ quotient = (pwm_div + 1) * duty_ns;
+ hi_dur = div64_u64(quotient, period_ns);
+
+ val |= ((hi_dur & MAX_PWM_CFG) << PWM_CTRL_HI_SHIFT);
+ val |= (pwm_div & MAX_PWM_CFG);
+ writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG0));
+ val = pre_div & MAX_PWM_CFG;
+ writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG1));
+}
+
+static int ipq_pwm_enable(struct pwm_device *pwm)
+{
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+ unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
+ unsigned long val;
+
+ val = readl(ipq_chip->mem + offset);
+ val |= PWM_ENABLE | PWM_UPDATE;
+ writel(val, ipq_chip->mem + offset);
+
+ return 0;
+}
+
+static void ipq_pwm_disable(struct pwm_device *pwm)
+{
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+ unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
+ unsigned long val;
+
+ val = readl(ipq_chip->mem + offset);
+ val |= PWM_UPDATE;
+ val &= ~PWM_ENABLE;
+ writel(val, ipq_chip->mem + offset);
+}
+
+static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
+ unsigned long freq;
+ int pre_div, close_pre_div, close_pwm_div;
+ int pwm_div;
+ long long diff;
+ unsigned long rate = clk_get_rate(ipq_chip->clk);
+ unsigned long min_diff = rate;
+ uint64_t fin_ps;
+ u64 period_ns, duty_ns;
+
+ if (state->period < MIN_PERIOD_NS)
+ return -ERANGE;
+
+ period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
+ duty_ns = min_t(u64, state->duty_cycle, period_ns);
+
+ /* freq in Hz for period in nano second*/
+ freq = NSEC_PER_SEC / period_ns;
+ fin_ps = div64_u64(NSEC_PER_SEC * 1000, rate);
+ close_pre_div = MAX_PWM_CFG;
+ close_pwm_div = MAX_PWM_CFG;
+
+ for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
+ pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
+ fin_ps * (pre_div + 1));
+ pwm_div--;
+ if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
+ continue;
+
+ diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
+ - (uint64_t)rate;
+
+ if (diff < 0) /* period larger than requested */
+ continue;
+ if (diff == 0) { /* bingo */
+ close_pre_div = pre_div;
+ close_pwm_div = pwm_div;
+ break;
+ }
+ if (diff < min_diff) {
+ min_diff = diff;
+ close_pre_div = pre_div;
+ close_pwm_div = pwm_div;
+ }
+ }
+
+ /* config divider values for the closest possible frequency */
+ config_div_and_duty(pwm, close_pre_div, close_pwm_div,
+ period_ns, duty_ns);
+ if (state->enabled)
+ ipq_pwm_enable(pwm);
+ else
+ ipq_pwm_disable(pwm);
+
+ return 0;
+}
+
+static struct pwm_ops ipq_pwm_ops = {
+ .apply = ipq_pwm_apply,
+ .owner = THIS_MODULE,
+};
+
+static int ipq_pwm_probe(struct platform_device *pdev)
+{
+ struct ipq_pwm_chip *pwm;
+ struct device *dev;
+ int ret;
+
+ dev = &pdev->dev;
+ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pwm);
+
+ pwm->mem = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pwm->mem))
+ return PTR_ERR(pwm->mem);
+
+ pwm->clk = devm_clk_get(dev, "core");
+ if (IS_ERR(pwm->clk))
+ return PTR_ERR(pwm->clk);
+
+ ret = clk_set_rate(pwm->clk, CLK_SRC_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_prepare_enable(pwm->clk);
+ if (ret)
+ return ret;
+
+ pwm->chip.dev = dev;
+ pwm->chip.ops = &ipq_pwm_ops;
+ pwm->chip.npwm = MAX_PWM_DEVICES;
+
+ ret = pwmchip_add(&pwm->chip);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "pwmchip_add() failed\n");
+ clk_disable_unprepare(pwm->clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ipq_pwm_remove(struct platform_device *pdev)
+{
+ struct ipq_pwm_chip *pwm = platform_get_drvdata(pdev);
+
+ pwmchip_remove(&pwm->chip);
+
+ return 0;
+}
+
+static const struct of_device_id pwm_ipq_dt_match[] = {
+ { .compatible = "qcom,pwm-ipq6018", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
+
+static struct platform_driver ipq_pwm_driver = {
+ .driver = {
+ .name = "ipq-pwm",
+ .owner = THIS_MODULE,
+ .of_match_table = pwm_ipq_dt_match,
+ },
+ .probe = ipq_pwm_probe,
+ .remove = ipq_pwm_remove,
+};
+
+module_platform_driver(ipq_pwm_driver);
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
2021-05-24 10:20 ` Baruch Siach
@ 2021-05-24 10:20 ` Baruch Siach
-1 siblings, 0 replies; 15+ messages in thread
From: Baruch Siach @ 2021-05-24 10:20 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, linux-pwm, devicetree, linux-arm-msm,
linux-arm-kernel
DT binding for the PWM block in Qualcomm IPQ6018 SoC.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2: Make #pwm-cells const (Rob Herring)
---
.../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
new file mode 100644
index 000000000000..f85ce808a14e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ6018 PWM controller
+
+maintainers:
+ - Baruch Siach <baruch@tkos.co.il>
+
+properties:
+ "#pwm-cells":
+ const: 2
+
+ compatible:
+ const: qcom,pwm-ipq6018
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: core
+
+required:
+ - "#pwm-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pwm@1941010 {
+ #pwm-cells = <2>;
+ compatible = "qcom,pwm-ipq6018";
+ reg = <0x0 0x1941010 0x0 0x20>;
+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ clock-names = "core";
+ };
+ };
--
2.30.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
@ 2021-05-24 10:20 ` Baruch Siach
0 siblings, 0 replies; 15+ messages in thread
From: Baruch Siach @ 2021-05-24 10:20 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, linux-pwm, devicetree, linux-arm-msm,
linux-arm-kernel
DT binding for the PWM block in Qualcomm IPQ6018 SoC.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2: Make #pwm-cells const (Rob Herring)
---
.../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
new file mode 100644
index 000000000000..f85ce808a14e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ6018 PWM controller
+
+maintainers:
+ - Baruch Siach <baruch@tkos.co.il>
+
+properties:
+ "#pwm-cells":
+ const: 2
+
+ compatible:
+ const: qcom,pwm-ipq6018
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: core
+
+required:
+ - "#pwm-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pwm@1941010 {
+ #pwm-cells = <2>;
+ compatible = "qcom,pwm-ipq6018";
+ reg = <0x0 0x1941010 0x0 0x20>;
+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ clock-names = "core";
+ };
+ };
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
2021-05-24 10:20 ` Baruch Siach
@ 2021-06-02 19:47 ` Rob Herring
-1 siblings, 0 replies; 15+ messages in thread
From: Rob Herring @ 2021-06-02 19:47 UTC (permalink / raw)
To: Baruch Siach
Cc: Thierry Reding, Uwe Kleine-König, Lee Jones, Andy Gross,
Bjorn Andersson, Balaji Prakash J, Robert Marko, linux-pwm,
devicetree, linux-arm-msm, linux-arm-kernel
On Mon, May 24, 2021 at 01:20:43PM +0300, Baruch Siach wrote:
> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v2: Make #pwm-cells const (Rob Herring)
> ---
> .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> new file mode 100644
> index 000000000000..f85ce808a14e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ6018 PWM controller
> +
> +maintainers:
> + - Baruch Siach <baruch@tkos.co.il>
> +
> +properties:
> + "#pwm-cells":
> + const: 2
> +
> + compatible:
> + const: qcom,pwm-ipq6018
qcom,ipq6018-pwm is the normal ordering.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: core
> +
> +required:
> + - "#pwm-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pwm@1941010 {
> + #pwm-cells = <2>;
> + compatible = "qcom,pwm-ipq6018";
> + reg = <0x0 0x1941010 0x0 0x20>;
> + clocks = <&gcc GCC_ADSS_PWM_CLK>;
> + clock-names = "core";
> + };
> + };
> --
> 2.30.2
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
@ 2021-06-02 19:47 ` Rob Herring
0 siblings, 0 replies; 15+ messages in thread
From: Rob Herring @ 2021-06-02 19:47 UTC (permalink / raw)
To: Baruch Siach
Cc: Thierry Reding, Uwe Kleine-König, Lee Jones, Andy Gross,
Bjorn Andersson, Balaji Prakash J, Robert Marko, linux-pwm,
devicetree, linux-arm-msm, linux-arm-kernel
On Mon, May 24, 2021 at 01:20:43PM +0300, Baruch Siach wrote:
> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v2: Make #pwm-cells const (Rob Herring)
> ---
> .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> new file mode 100644
> index 000000000000..f85ce808a14e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ6018 PWM controller
> +
> +maintainers:
> + - Baruch Siach <baruch@tkos.co.il>
> +
> +properties:
> + "#pwm-cells":
> + const: 2
> +
> + compatible:
> + const: qcom,pwm-ipq6018
qcom,ipq6018-pwm is the normal ordering.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: core
> +
> +required:
> + - "#pwm-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pwm@1941010 {
> + #pwm-cells = <2>;
> + compatible = "qcom,pwm-ipq6018";
> + reg = <0x0 0x1941010 0x0 0x20>;
> + clocks = <&gcc GCC_ADSS_PWM_CLK>;
> + clock-names = "core";
> + };
> + };
> --
> 2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
2021-05-24 10:20 ` Baruch Siach
@ 2021-06-02 23:05 ` Bjorn Andersson
-1 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2021-06-02 23:05 UTC (permalink / raw)
To: Baruch Siach, Rob Herring
Cc: Thierry Reding, Uwe Kleine-K?nig, Lee Jones, Andy Gross,
Balaji Prakash J, Robert Marko, linux-pwm, devicetree,
linux-arm-msm, linux-arm-kernel
On Mon 24 May 05:20 CDT 2021, Baruch Siach wrote:
> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v2: Make #pwm-cells const (Rob Herring)
> ---
> .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> new file mode 100644
> index 000000000000..f85ce808a14e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ6018 PWM controller
> +
> +maintainers:
> + - Baruch Siach <baruch@tkos.co.il>
> +
> +properties:
> + "#pwm-cells":
> + const: 2
> +
> + compatible:
> + const: qcom,pwm-ipq6018
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: core
> +
> +required:
> + - "#pwm-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pwm@1941010 {
> + #pwm-cells = <2>;
> + compatible = "qcom,pwm-ipq6018";
> + reg = <0x0 0x1941010 0x0 0x20>;
These 32 bytes are in the middle of the TCSR block, which is already
partially described by the &tcsr_q6 node, which is described as only
compatible = "syscon" - something no longer accepted by the DT
maintainers.
As such, I think we should adjust the &tcsr_q6 definition to cover the
entire TCSR: 0x01937000 of size 0x21000.
@Rob, should we represent the entire tcsr as a simple-mfd and then have
the pwm and q6 region as children of that? Or can we make the whole
thing as a simple-mfd and a syscon and only describe the pwm as a child?
Regards,
Bjorn
> + clocks = <&gcc GCC_ADSS_PWM_CLK>;
> + clock-names = "core";
> + };
> + };
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
@ 2021-06-02 23:05 ` Bjorn Andersson
0 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2021-06-02 23:05 UTC (permalink / raw)
To: Baruch Siach, Rob Herring
Cc: Thierry Reding, Uwe Kleine-K?nig, Lee Jones, Andy Gross,
Balaji Prakash J, Robert Marko, linux-pwm, devicetree,
linux-arm-msm, linux-arm-kernel
On Mon 24 May 05:20 CDT 2021, Baruch Siach wrote:
> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v2: Make #pwm-cells const (Rob Herring)
> ---
> .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> new file mode 100644
> index 000000000000..f85ce808a14e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ6018 PWM controller
> +
> +maintainers:
> + - Baruch Siach <baruch@tkos.co.il>
> +
> +properties:
> + "#pwm-cells":
> + const: 2
> +
> + compatible:
> + const: qcom,pwm-ipq6018
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: core
> +
> +required:
> + - "#pwm-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pwm@1941010 {
> + #pwm-cells = <2>;
> + compatible = "qcom,pwm-ipq6018";
> + reg = <0x0 0x1941010 0x0 0x20>;
These 32 bytes are in the middle of the TCSR block, which is already
partially described by the &tcsr_q6 node, which is described as only
compatible = "syscon" - something no longer accepted by the DT
maintainers.
As such, I think we should adjust the &tcsr_q6 definition to cover the
entire TCSR: 0x01937000 of size 0x21000.
@Rob, should we represent the entire tcsr as a simple-mfd and then have
the pwm and q6 region as children of that? Or can we make the whole
thing as a simple-mfd and a syscon and only describe the pwm as a child?
Regards,
Bjorn
> + clocks = <&gcc GCC_ADSS_PWM_CLK>;
> + clock-names = "core";
> + };
> + };
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding
2021-06-02 23:05 ` Bjorn Andersson
(?)
@ 2021-06-30 14:46 ` Kathiravan T
-1 siblings, 0 replies; 15+ messages in thread
From: Kathiravan T @ 2021-06-30 14:46 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Baruch Siach, Rob Herring, Thierry Reding, Uwe Kleine-K?nig,
Lee Jones, Andy Gross, Balaji Prakash J, Robert Marko, linux-pwm,
devicetree, linux-arm-msm, linux-arm-kernel
On 2021-06-03 04:35, Bjorn Andersson wrote:
> On Mon 24 May 05:20 CDT 2021, Baruch Siach wrote:
>
>> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
>>
>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>> ---
>> v2: Make #pwm-cells const (Rob Herring)
>> ---
>> .../devicetree/bindings/pwm/ipq-pwm.yaml | 52
>> +++++++++++++++++++
>> 1 file changed, 52 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>> b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>> new file mode 100644
>> index 000000000000..f85ce808a14e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>> @@ -0,0 +1,52 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm IPQ6018 PWM controller
>> +
>> +maintainers:
>> + - Baruch Siach <baruch@tkos.co.il>
>> +
>> +properties:
>> + "#pwm-cells":
>> + const: 2
>> +
>> + compatible:
>> + const: qcom,pwm-ipq6018
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + const: core
>> +
>> +required:
>> + - "#pwm-cells"
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + pwm@1941010 {
>> + #pwm-cells = <2>;
>> + compatible = "qcom,pwm-ipq6018";
>> + reg = <0x0 0x1941010 0x0 0x20>;
>
> These 32 bytes are in the middle of the TCSR block, which is already
> partially described by the &tcsr_q6 node, which is described as only
> compatible = "syscon" - something no longer accepted by the DT
> maintainers.
>
> As such, I think we should adjust the &tcsr_q6 definition to cover the
> entire TCSR: 0x01937000 of size 0x21000.
>
To my knowledge, we can cover the entire TCSR region, so that we can use
it
for the other features like qcom,dload-mode as well.
>
> @Rob, should we represent the entire tcsr as a simple-mfd and then have
> the pwm and q6 region as children of that? Or can we make the whole
> thing as a simple-mfd and a syscon and only describe the pwm as a
> child?
>
> Regards,
> Bjorn
>
>> + clocks = <&gcc GCC_ADSS_PWM_CLK>;
>> + clock-names = "core";
>> + };
>> + };
>> --
>> 2.30.2
>>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/3] arm64: dts: ipq6018: add pwm node
2021-05-24 10:20 ` Baruch Siach
@ 2021-05-24 10:20 ` Baruch Siach
-1 siblings, 0 replies; 15+ messages in thread
From: Baruch Siach @ 2021-05-24 10:20 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, linux-pwm, devicetree, linux-arm-msm,
linux-arm-kernel
Describe the PWM block on IPQ6018.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 6ee7b99c21ec..2da75bb558ff 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -355,6 +355,15 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
status = "disabled";
};
+ pwm: pwm@1941010 {
+ #pwm-cells = <2>;
+ compatible = "qcom,pwm-ipq6018";
+ reg = <0x0 0x1941010 0x0 0x20>;
+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07984000 0x0 0x1a000>;
--
2.30.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 3/3] arm64: dts: ipq6018: add pwm node
@ 2021-05-24 10:20 ` Baruch Siach
0 siblings, 0 replies; 15+ messages in thread
From: Baruch Siach @ 2021-05-24 10:20 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, linux-pwm, devicetree, linux-arm-msm,
linux-arm-kernel
Describe the PWM block on IPQ6018.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 6ee7b99c21ec..2da75bb558ff 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -355,6 +355,15 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
status = "disabled";
};
+ pwm: pwm@1941010 {
+ #pwm-cells = <2>;
+ compatible = "qcom,pwm-ipq6018";
+ reg = <0x0 0x1941010 0x0 0x20>;
+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07984000 0x0 0x1a000>;
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block
2021-05-24 10:20 ` Baruch Siach
@ 2021-05-24 14:48 ` kernel test robot
-1 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2021-05-24 14:48 UTC (permalink / raw)
To: Baruch Siach, Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: kbuild-all, Baruch Siach, Andy Gross, Bjorn Andersson,
Balaji Prakash J, Rob Herring, Robert Marko, linux-pwm
[-- Attachment #1: Type: text/plain, Size: 3902 bytes --]
Hi Baruch,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pwm/for-next]
[also build test WARNING on robh/for-next v5.13-rc3 next-20210524]
[cannot apply to agross-msm/qcom/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Baruch-Siach/pwm-driver-for-qualcomm-ipq6018-pwm-block/20210524-182306
base: https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/fd963192953e74575c0bba469b6a1ef769db9d33
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Baruch-Siach/pwm-driver-for-qualcomm-ipq6018-pwm-block/20210524-182306
git checkout fd963192953e74575c0bba469b6a1ef769db9d33
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/pwm/pwm-ipq.c: In function 'ipq_pwm_apply':
>> drivers/pwm/pwm-ipq.c:125:34: warning: integer overflow in expression of type 'long int' results in '-727379968' [-Woverflow]
125 | fin_ps = div64_u64(NSEC_PER_SEC * 1000, rate);
| ^
vim +125 drivers/pwm/pwm-ipq.c
103
104 static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
105 const struct pwm_state *state)
106 {
107 struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
108 unsigned long freq;
109 int pre_div, close_pre_div, close_pwm_div;
110 int pwm_div;
111 long long diff;
112 unsigned long rate = clk_get_rate(ipq_chip->clk);
113 unsigned long min_diff = rate;
114 uint64_t fin_ps;
115 u64 period_ns, duty_ns;
116
117 if (state->period < MIN_PERIOD_NS)
118 return -ERANGE;
119
120 period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
121 duty_ns = min_t(u64, state->duty_cycle, period_ns);
122
123 /* freq in Hz for period in nano second*/
124 freq = NSEC_PER_SEC / period_ns;
> 125 fin_ps = div64_u64(NSEC_PER_SEC * 1000, rate);
126 close_pre_div = MAX_PWM_CFG;
127 close_pwm_div = MAX_PWM_CFG;
128
129 for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
130 pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
131 fin_ps * (pre_div + 1));
132 pwm_div--;
133 if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
134 continue;
135
136 diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
137 - (uint64_t)rate;
138
139 if (diff < 0) /* period larger than requested */
140 continue;
141 if (diff == 0) { /* bingo */
142 close_pre_div = pre_div;
143 close_pwm_div = pwm_div;
144 break;
145 }
146 if (diff < min_diff) {
147 min_diff = diff;
148 close_pre_div = pre_div;
149 close_pwm_div = pwm_div;
150 }
151 }
152
153 /* config divider values for the closest possible frequency */
154 config_div_and_duty(pwm, close_pre_div, close_pwm_div,
155 period_ns, duty_ns);
156 if (state->enabled)
157 ipq_pwm_enable(pwm);
158 else
159 ipq_pwm_disable(pwm);
160
161 return 0;
162 }
163
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 67491 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block
@ 2021-05-24 14:48 ` kernel test robot
0 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2021-05-24 14:48 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4007 bytes --]
Hi Baruch,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pwm/for-next]
[also build test WARNING on robh/for-next v5.13-rc3 next-20210524]
[cannot apply to agross-msm/qcom/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Baruch-Siach/pwm-driver-for-qualcomm-ipq6018-pwm-block/20210524-182306
base: https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/fd963192953e74575c0bba469b6a1ef769db9d33
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Baruch-Siach/pwm-driver-for-qualcomm-ipq6018-pwm-block/20210524-182306
git checkout fd963192953e74575c0bba469b6a1ef769db9d33
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/pwm/pwm-ipq.c: In function 'ipq_pwm_apply':
>> drivers/pwm/pwm-ipq.c:125:34: warning: integer overflow in expression of type 'long int' results in '-727379968' [-Woverflow]
125 | fin_ps = div64_u64(NSEC_PER_SEC * 1000, rate);
| ^
vim +125 drivers/pwm/pwm-ipq.c
103
104 static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
105 const struct pwm_state *state)
106 {
107 struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
108 unsigned long freq;
109 int pre_div, close_pre_div, close_pwm_div;
110 int pwm_div;
111 long long diff;
112 unsigned long rate = clk_get_rate(ipq_chip->clk);
113 unsigned long min_diff = rate;
114 uint64_t fin_ps;
115 u64 period_ns, duty_ns;
116
117 if (state->period < MIN_PERIOD_NS)
118 return -ERANGE;
119
120 period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
121 duty_ns = min_t(u64, state->duty_cycle, period_ns);
122
123 /* freq in Hz for period in nano second*/
124 freq = NSEC_PER_SEC / period_ns;
> 125 fin_ps = div64_u64(NSEC_PER_SEC * 1000, rate);
126 close_pre_div = MAX_PWM_CFG;
127 close_pwm_div = MAX_PWM_CFG;
128
129 for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
130 pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
131 fin_ps * (pre_div + 1));
132 pwm_div--;
133 if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
134 continue;
135
136 diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
137 - (uint64_t)rate;
138
139 if (diff < 0) /* period larger than requested */
140 continue;
141 if (diff == 0) { /* bingo */
142 close_pre_div = pre_div;
143 close_pwm_div = pwm_div;
144 break;
145 }
146 if (diff < min_diff) {
147 min_diff = diff;
148 close_pre_div = pre_div;
149 close_pwm_div = pwm_div;
150 }
151 }
152
153 /* config divider values for the closest possible frequency */
154 config_div_and_duty(pwm, close_pre_div, close_pwm_div,
155 period_ns, duty_ns);
156 if (state->enabled)
157 ipq_pwm_enable(pwm);
158 else
159 ipq_pwm_disable(pwm);
160
161 return 0;
162 }
163
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 67491 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block
2021-05-24 10:20 ` Baruch Siach
@ 2021-05-24 16:08 ` kernel test robot
-1 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2021-05-24 16:08 UTC (permalink / raw)
To: Baruch Siach, Thierry Reding, Uwe Kleine-König, Lee Jones
Cc: kbuild-all, Baruch Siach, Andy Gross, Bjorn Andersson,
Balaji Prakash J, Rob Herring, Robert Marko, linux-pwm
[-- Attachment #1: Type: text/plain, Size: 2265 bytes --]
Hi Baruch,
I love your patch! Yet something to improve:
[auto build test ERROR on pwm/for-next]
[also build test ERROR on robh/for-next v5.13-rc3 next-20210524]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Baruch-Siach/pwm-driver-for-qualcomm-ipq6018-pwm-block/20210524-182306
base: https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/fd963192953e74575c0bba469b6a1ef769db9d33
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Baruch-Siach/pwm-driver-for-qualcomm-ipq6018-pwm-block/20210524-182306
git checkout fd963192953e74575c0bba469b6a1ef769db9d33
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=sh
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>, old ones prefixed by <<):
ERROR: modpost: "__delay" [drivers/net/mdio/mdio-cavium.ko] undefined!
>> ERROR: modpost: "__udivdi3" [drivers/pwm/pwm-ipq.ko] undefined!
>> ERROR: modpost: "__divdi3" [drivers/pwm/pwm-ipq.ko] undefined!
ERROR: modpost: "__udivdi3" [fs/btrfs/btrfs.ko] undefined!
ERROR: modpost: "__umoddi3" [fs/btrfs/btrfs.ko] undefined!
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for SND_ATMEL_SOC_PDC
Depends on SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC && HAS_DMA
Selected by
- SND_ATMEL_SOC_SSC && SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC
- SND_ATMEL_SOC_SSC_PDC && SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC && ATMEL_SSC
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 54169 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-06-30 14:46 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-24 10:20 [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block Baruch Siach
2021-05-24 10:20 ` Baruch Siach
2021-05-24 10:20 ` [PATCH v2 2/3] dt-bindings: pwm: add IPQ6018 binding Baruch Siach
2021-05-24 10:20 ` Baruch Siach
2021-06-02 19:47 ` Rob Herring
2021-06-02 19:47 ` Rob Herring
2021-06-02 23:05 ` Bjorn Andersson
2021-06-02 23:05 ` Bjorn Andersson
2021-06-30 14:46 ` Kathiravan T
2021-05-24 10:20 ` [PATCH v2 3/3] arm64: dts: ipq6018: add pwm node Baruch Siach
2021-05-24 10:20 ` Baruch Siach
2021-05-24 14:48 ` [PATCH v2 1/3] pwm: driver for qualcomm ipq6018 pwm block kernel test robot
2021-05-24 14:48 ` kernel test robot
2021-05-24 16:08 ` kernel test robot
2021-05-24 16:08 ` kernel test robot
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.